src/gallium/drivers/nv50/nv50_tex.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "nv50_context.h"
  24 #include "nv50_texture.h"
  25
  26 #include "nouveau/nouveau_stateobj.h"
  27
  28 #include "util/u_format.h"
  29
  30 #define _MIXED(pf, t0, t1, t2, t3, cr, cg, cb, ca, f)           \
  31 {                                                               \
  32         PIPE_FORMAT_##pf,                                       \
  33         NV50TIC_0_0_MAPR_##cr | NV50TIC_0_0_TYPER_##t0 |        \
  34         NV50TIC_0_0_MAPG_##cg | NV50TIC_0_0_TYPEG_##t1 |        \
  35         NV50TIC_0_0_MAPB_##cb | NV50TIC_0_0_TYPEB_##t2 |        \
  36         NV50TIC_0_0_MAPA_##ca | NV50TIC_0_0_TYPEA_##t3 |        \
  37         NV50TIC_0_0_FMT_##f                                     \
  38 }
  39
  40 #define _(pf, t, cr, cg, cb, ca, f) _MIXED(pf, t, t, t, t, cr, cg, cb, ca, f)
  41
  42 struct nv50_texture_format {
  43         enum pipe_format pf;
  44         uint32_t hw;
  45 };
  46
  47 #define NV50_TEX_FORMAT_LIST_SIZE \
  48         (sizeof(nv50_tex_format_list) / sizeof(struct nv50_texture_format))
  49
  50 static const struct nv50_texture_format nv50_tex_format_list[] =
  51 {
  52         _(A8R8G8B8_UNORM, UNORM, C2, C1, C0, C3,  8_8_8_8),
  53         _(A8R8G8B8_SRGB,  UNORM, C2, C1, C0, C3,  8_8_8_8),
  54         _(X8R8G8B8_UNORM, UNORM, C2, C1, C0, ONE, 8_8_8_8),
  55         _(X8R8G8B8_SRGB,  UNORM, C2, C1, C0, ONE, 8_8_8_8),
  56         _(A1R5G5B5_UNORM, UNORM, C2, C1, C0, C3,  1_5_5_5),
  57         _(A4R4G4B4_UNORM, UNORM, C2, C1, C0, C3,  4_4_4_4),
  58
  59         _(R5G6B5_UNORM, UNORM, C2, C1, C0, ONE, 5_6_5),
  60
  61         _(L8_UNORM, UNORM, C0, C0, C0, ONE, 8),
  62         _(A8_UNORM, UNORM, ZERO, ZERO, ZERO, C0, 8),
  63         _(I8_UNORM, UNORM, C0, C0, C0, C0, 8),
  64
  65         _(A8L8_UNORM, UNORM, C0, C0, C0, C1, 8_8),
  66
  67         _(DXT1_RGB, UNORM, C0, C1, C2, ONE, DXT1),
  68         _(DXT1_RGBA, UNORM, C0, C1, C2, C3, DXT1),
  69         _(DXT3_RGBA, UNORM, C0, C1, C2, C3, DXT3),
  70         _(DXT5_RGBA, UNORM, C0, C1, C2, C3, DXT5),
  71
  72         _MIXED(Z24S8_UNORM, UINT, UNORM, UINT, UINT, C1, C1, C1, ONE, 24_8),
  73         _MIXED(S8Z24_UNORM, UNORM, UINT, UINT, UINT, C0, C0, C0, ONE, 8_24),
  74
  75         _(R16G16B16A16_SNORM, UNORM, C0, C1, C2, C3, 16_16_16_16),
  76         _(R16G16B16A16_UNORM, SNORM, C0, C1, C2, C3, 16_16_16_16),
  77         _(R32G32B32A32_FLOAT, FLOAT, C0, C1, C2, C3, 32_32_32_32),
  78
  79         _(R16G16_SNORM, SNORM, C0, C1, ZERO, ONE, 16_16),
  80         _(R16G16_UNORM, UNORM, C0, C1, ZERO, ONE, 16_16),
  81
  82         _MIXED(Z32_FLOAT, FLOAT, UINT, UINT, UINT, C0, C0, C0, ONE, 32_DEPTH)
  83
  84 };
  85
  86 #undef _
  87 #undef _MIXED
  88
  89 static int
  90 nv50_tex_construct(struct nv50_context *nv50, struct nouveau_stateobj *so,
  91                    struct nv50_miptree *mt, int unit, unsigned p)
  92 {
  93         unsigned i;
  94         uint32_t mode;
  95         const struct util_format_description *desc;
  96
  97         for (i = 0; i < NV50_TEX_FORMAT_LIST_SIZE; i++)
  98                 if (nv50_tex_format_list[i].pf == mt->base.base.format)
  99                         break;
 100         if (i == NV50_TEX_FORMAT_LIST_SIZE)
 101                 return 1;
 102
 103         if (nv50->sampler[p][unit]->normalized)
 104                 mode = 0x50001000 | (1 << 31);
 105         else {
 106                 mode = 0x50001000 | (7 << 14);
 107                 assert(mt->base.base.target == PIPE_TEXTURE_2D);
 108         }
 109
 110         mode |= ((mt->base.bo->tile_mode & 0x0f) << 22) |
 111                 ((mt->base.bo->tile_mode & 0xf0) << 21);
 112
 113         desc = util_format_description(mt->base.base.format);
 114         assert(desc);
 115
 116         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 117                 mode |= 0x0400;
 118
 119         switch (mt->base.base.target) {
 120         case PIPE_TEXTURE_1D:
 121                 break;
 122         case PIPE_TEXTURE_2D:
 123                 mode |= (1 << 14);
 124                 break;
 125         case PIPE_TEXTURE_3D:
 126                 mode |= (2 << 14);
 127                 break;
 128         case PIPE_TEXTURE_CUBE:
 129                 mode |= (3 << 14);
 130                 break;
 131         default:
 132                 assert(!"unsupported texture target");
 133                 break;
 134         }
 135
 136         so_data (so, nv50_tex_format_list[i].hw);
 137         so_reloc(so, mt->base.bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW |
 138                  NOUVEAU_BO_RD, 0, 0);
 139         so_data (so, mode);
 140         so_data (so, 0x00300000);
 141         so_data (so, mt->base.base.width0 | (1 << 31));
 142         so_data (so, (mt->base.base.last_level << 28) |
 143                  (mt->base.base.depth0 << 16) | mt->base.base.height0);
 144         so_data (so, 0x03000000);
 145         so_data (so, mt->base.base.last_level << 4);
 146
 147         return 0;
 148 }
 149
 150 #ifndef NV50TCL_BIND_TIC
 151 #define NV50TCL_BIND_TIC(n) (0x1448 + 8 * n)
 152 #endif
 153
 154 static boolean
 155 nv50_validate_textures(struct nv50_context *nv50, struct nouveau_stateobj *so,
 156                        unsigned p)
 157 {
 158         static const unsigned p_remap[PIPE_SHADER_TYPES] = { 0, 2, 1 };
 159
 160         struct nouveau_grobj *eng2d = nv50->screen->eng2d;
 161         struct nouveau_grobj *tesla = nv50->screen->tesla;
 162         unsigned unit, j, p_hw = p_remap[p];
 163
 164         nv50_so_init_sifc(nv50, so, nv50->screen->tic, NOUVEAU_BO_VRAM,
 165                           p * (32 * 8 * 4), nv50->miptree_nr[p] * 8 * 4);
 166
 167         for (unit = 0; unit < nv50->miptree_nr[p]; ++unit) {
 168                 struct nv50_miptree *mt = nv50->miptree[p][unit];
 169
 170                 so_method(so, eng2d, NV50_2D_SIFC_DATA | (2 << 29), 8);
 171                 if (mt) {
 172                         if (nv50_tex_construct(nv50, so, mt, unit, p))
 173                                 return FALSE;
 174                         /* Set TEX insn $t src binding $unit in program type p
 175                          * to TIC, TSC entry (32 * p + unit), mark valid (1).
 176                          */
 177                         so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1);
 178                         so_data  (so, ((32 * p + unit) << 9) | (unit << 1) | 1);
 179                 } else {
 180                         for (j = 0; j < 8; ++j)
 181                                 so_data(so, 0);
 182                         so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1);
 183                         so_data  (so, (unit << 1) | 0);
 184                 }
 185         }
 186
 187         for (; unit < nv50->state.miptree_nr[p]; unit++) {
 188                 /* Make other bindings invalid. */
 189                 so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1);
 190                 so_data  (so, (unit << 1) | 0);
 191         }
 192
 193         nv50->state.miptree_nr[p] = nv50->miptree_nr[p];
 194         return TRUE;
 195 }
 196
 197 void
 198 nv50_tex_validate(struct nv50_context *nv50)
 199 {
 200         struct nouveau_stateobj *so;
 201         struct nouveau_grobj *tesla = nv50->screen->tesla;
 202         unsigned p, start, push, nrlc;
 203
 204         for (nrlc = 0, start = 0, push = 0, p = 0; p < PIPE_SHADER_TYPES; ++p) {
 205                 start += MAX2(nv50->miptree_nr[p], nv50->state.miptree_nr[p]);
 206                 push += MAX2(nv50->miptree_nr[p], nv50->state.miptree_nr[p]);
 207                 nrlc += nv50->miptree_nr[p];
 208         }
 209         start = start * 2 + 4 * PIPE_SHADER_TYPES + 2;
 210         push = push * 9 + 19 * PIPE_SHADER_TYPES + 2;
 211         nrlc = nrlc * 2 + 2 * PIPE_SHADER_TYPES;
 212
 213         so = so_new(start, push, nrlc);
 214
 215         if (nv50_validate_textures(nv50, so, PIPE_SHADER_VERTEX) == FALSE ||
 216             nv50_validate_textures(nv50, so, PIPE_SHADER_FRAGMENT) == FALSE) {
 217                 so_ref(NULL, &so);
 218
 219                 NOUVEAU_ERR("failed tex validate\n");
 220                 return;
 221         }
 222
 223         so_method(so, tesla, 0x1330, 1); /* flush TIC */
 224         so_data  (so, 0);
 225
 226         so_ref(so, &nv50->state.tic_upload);
 227         so_ref(NULL, &so);
 228 }