src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nvc0_context.h"
  31 #include "nvc0_screen.h"
  32
  33 #include "nouveau/nv_object.xml.h"
  34 #include "nvc0_graph_macros.h"
  35
  36 static boolean
  37 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  38                                 enum pipe_format format,
  39                                 enum pipe_texture_target target,
  40                                 unsigned sample_count,
  41                                 unsigned bindings)
  42 {
  43    if (sample_count > 2 && sample_count != 4 && sample_count != 8)
  44       return FALSE;
  45
  46    if (!util_format_is_supported(format, bindings))
  47       return FALSE;
  48
  49    /* transfers & shared are always supported */
  50    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  51                  PIPE_BIND_TRANSFER_WRITE |
  52                  PIPE_BIND_SHARED);
  53
  54    return (nvc0_format_table[format].usage & bindings) == bindings;
  55 }
  56
  57 static int
  58 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  59 {
  60    switch (param) {
  61    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  62    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  63       return 32;
  64    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  65       return 64;
  66    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  67       return 13;
  68    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  69       return 10;
  70    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  71       return 13;
  72    case PIPE_CAP_ARRAY_TEXTURES:
  73       return 1;
  74    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  75    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  76    case PIPE_CAP_TEXTURE_SWIZZLE:
  77    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  78    case PIPE_CAP_NPOT_TEXTURES:
  79    case PIPE_CAP_ANISOTROPIC_FILTER:
  80    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  81       return 1;
  82    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  83       return 0;
  84    case PIPE_CAP_TWO_SIDED_STENCIL:
  85    case PIPE_CAP_DEPTH_CLAMP:
  86    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  87    case PIPE_CAP_POINT_SPRITE:
  88       return 1;
  89    case PIPE_CAP_GLSL:
  90    case PIPE_CAP_SM3:
  91       return 1;
  92    case PIPE_CAP_MAX_RENDER_TARGETS:
  93       return 8;
  94    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  95       return 1;
  96    case PIPE_CAP_TIMER_QUERY:
  97    case PIPE_CAP_OCCLUSION_QUERY:
  98       return 1;
  99    case PIPE_CAP_STREAM_OUTPUT:
 100       return 0;
 101    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 102    case PIPE_CAP_INDEP_BLEND_ENABLE:
 103    case PIPE_CAP_INDEP_BLEND_FUNC:
 104       return 1;
 105    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 106    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 107       return 1;
 108    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 109    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 110       return 0;
 111    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 112       return 0;
 113    case PIPE_CAP_PRIMITIVE_RESTART:
 114    case PIPE_CAP_TGSI_INSTANCEID:
 115    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 116    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 117       return 1;
 118    default:
 119       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 120       return 0;
 121    }
 122 }
 123
 124 static int
 125 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 126                              enum pipe_shader_cap param)
 127 {
 128    switch (shader) {
 129    case PIPE_SHADER_VERTEX:
 130       /*
 131    case PIPE_SHADER_TESSELLATION_CONTROL:
 132    case PIPE_SHADER_TESSELLATION_EVALUATION:
 133       */
 134    case PIPE_SHADER_GEOMETRY:
 135    case PIPE_SHADER_FRAGMENT:
 136       break;
 137    default:
 138       return 0;
 139    }
 140
 141    switch (param) {
 142    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 143    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 144    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 145    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 146       return 16384;
 147    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 148       return 4;
 149    case PIPE_SHADER_CAP_MAX_INPUTS:
 150       if (shader == PIPE_SHADER_VERTEX)
 151          return 32;
 152       return 0x300 / 16;
 153    case PIPE_SHADER_CAP_MAX_CONSTS:
 154       return 65536 / 16;
 155    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 156       return 14;
 157    case PIPE_SHADER_CAP_MAX_ADDRS:
 158       return 1;
 159    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 160    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 161       return shader != PIPE_SHADER_FRAGMENT;
 162    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 163    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 164       return 1;
 165    case PIPE_SHADER_CAP_MAX_PREDS:
 166       return 0;
 167    case PIPE_SHADER_CAP_MAX_TEMPS:
 168       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 169    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 170       return 1;
 171    case PIPE_SHADER_CAP_SUBROUTINES:
 172       return 0; /* please inline, or provide function declarations */
 173    case PIPE_SHADER_CAP_INTEGERS:
 174       return 0;
 175    default:
 176       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 177       return 0;
 178    }
 179 }
 180
 181 static float
 182 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 183 {
 184    switch (param) {
 185    case PIPE_CAP_MAX_LINE_WIDTH:
 186    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 187       return 10.0f;
 188    case PIPE_CAP_MAX_POINT_WIDTH:
 189    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 190       return 64.0f;
 191    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 192       return 16.0f;
 193    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 194       return 4.0f;
 195    default:
 196       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 197       return 0.0f;
 198    }
 199 }
 200
 201 static void
 202 nvc0_screen_destroy(struct pipe_screen *pscreen)
 203 {
 204    struct nvc0_screen *screen = nvc0_screen(pscreen);
 205
 206    if (screen->base.fence.current) {
 207       nouveau_fence_wait(screen->base.fence.current);
 208       nouveau_fence_ref(NULL, &screen->base.fence.current);
 209    }
 210    screen->base.channel->user_private = NULL;
 211
 212    nouveau_bo_ref(NULL, &screen->text);
 213    nouveau_bo_ref(NULL, &screen->tls);
 214    nouveau_bo_ref(NULL, &screen->txc);
 215    nouveau_bo_ref(NULL, &screen->fence.bo);
 216    nouveau_bo_ref(NULL, &screen->vfetch_cache);
 217
 218    nouveau_resource_destroy(&screen->text_heap);
 219
 220    if (screen->tic.entries)
 221       FREE(screen->tic.entries);
 222
 223    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 224
 225    nouveau_grobj_free(&screen->fermi);
 226    nouveau_grobj_free(&screen->eng2d);
 227    nouveau_grobj_free(&screen->m2mf);
 228
 229    nouveau_screen_fini(&screen->base);
 230
 231    FREE(screen);
 232 }
 233
 234 static int
 235 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 236                      unsigned size, const uint32_t *data)
 237 {
 238    struct nouveau_channel *chan = screen->base.channel;
 239
 240    size /= 4;
 241
 242    BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
 243    OUT_RING  (chan, (m - 0x3800) / 8);
 244    OUT_RING  (chan, pos);
 245    BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 246    OUT_RING  (chan, pos);
 247    OUT_RINGp (chan, data, size);
 248
 249    return pos + size;
 250 }
 251
 252 static void
 253 nvc0_magic_3d_init(struct nouveau_channel *chan)
 254 {
 255    BEGIN_RING(chan, RING_3D_(0x10cc), 1);
 256    OUT_RING  (chan, 0xff);
 257    BEGIN_RING(chan, RING_3D_(0x10e0), 2);
 258    OUT_RING(chan, 0xff);
 259    OUT_RING(chan, 0xff);
 260    BEGIN_RING(chan, RING_3D_(0x10ec), 2);
 261    OUT_RING(chan, 0xff);
 262    OUT_RING(chan, 0xff);
 263    BEGIN_RING(chan, RING_3D_(0x074c), 1);
 264    OUT_RING  (chan, 0x3f);
 265
 266    BEGIN_RING(chan, RING_3D_(0x16a8), 1);
 267    OUT_RING  (chan, (3 << 16) | 3);
 268    BEGIN_RING(chan, RING_3D_(0x1794), 1);
 269    OUT_RING  (chan, (2 << 16) | 2);
 270    BEGIN_RING(chan, RING_3D_(0x0de8), 1);
 271    OUT_RING  (chan, 1);
 272
 273 #if 0 /* software method */
 274    BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
 275    OUT_RING  (chan, 0);
 276 #endif
 277
 278    BEGIN_RING(chan, RING_3D_(0x12ac), 1);
 279    OUT_RING  (chan, 0);
 280    BEGIN_RING(chan, RING_3D_(0x0218), 1);
 281    OUT_RING  (chan, 0x10);
 282    BEGIN_RING(chan, RING_3D_(0x10fc), 1);
 283    OUT_RING  (chan, 0x10);
 284    BEGIN_RING(chan, RING_3D_(0x1290), 1);
 285    OUT_RING  (chan, 0x10);
 286    BEGIN_RING(chan, RING_3D_(0x12d8), 2);
 287    OUT_RING  (chan, 0x10);
 288    OUT_RING  (chan, 0x10);
 289    BEGIN_RING(chan, RING_3D_(0x06d4), 1);
 290    OUT_RING  (chan, 8);
 291    BEGIN_RING(chan, RING_3D_(0x1140), 1);
 292    OUT_RING  (chan, 0x10);
 293    BEGIN_RING(chan, RING_3D_(0x1610), 1);
 294    OUT_RING  (chan, 0xe);
 295
 296    BEGIN_RING(chan, RING_3D_(0x164c), 1);
 297    OUT_RING  (chan, 1 << 12);
 298    BEGIN_RING(chan, RING_3D_(0x151c), 1);
 299    OUT_RING  (chan, 1);
 300    BEGIN_RING(chan, RING_3D_(0x030c), 1);
 301    OUT_RING  (chan, 0);
 302    BEGIN_RING(chan, RING_3D_(0x0300), 1);
 303    OUT_RING  (chan, 3);
 304 #if 0 /* software method */
 305    BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
 306    OUT_RING  (chan, 0);
 307 #endif
 308    BEGIN_RING(chan, RING_3D_(0x02d0), 1);
 309    OUT_RING  (chan, 0x1f40);
 310    BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
 311    OUT_RING  (chan, 1);
 312    BEGIN_RING(chan, RING_3D_(0x19c0), 1);
 313    OUT_RING  (chan, 1);
 314    BEGIN_RING(chan, RING_3D_(0x075c), 1);
 315    OUT_RING  (chan, 3);
 316 }
 317
 318 static void
 319 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 320 {
 321    struct nvc0_screen *screen = nvc0_screen(pscreen);
 322    struct nouveau_channel *chan = screen->base.channel;
 323
 324    MARK_RING (chan, 5, 2);
 325    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 326    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 327    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 328    OUT_RING  (chan, sequence);
 329    OUT_RING  (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 330               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 331 }
 332
 333 static u32
 334 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 335 {
 336    struct nvc0_screen *screen = nvc0_screen(pscreen);
 337    return screen->fence.map[0];
 338 }
 339
 340 #define FAIL_SCREEN_INIT(str, err)                    \
 341    do {                                               \
 342       NOUVEAU_ERR(str, err);                          \
 343       nvc0_screen_destroy(pscreen);                   \
 344       return NULL;                                    \
 345    } while(0)
 346
 347 struct pipe_screen *
 348 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 349 {
 350    struct nvc0_screen *screen;
 351    struct nouveau_channel *chan;
 352    struct pipe_screen *pscreen;
 353    int ret;
 354    unsigned i;
 355
 356    screen = CALLOC_STRUCT(nvc0_screen);
 357    if (!screen)
 358       return NULL;
 359    pscreen = &screen->base.base;
 360
 361    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 362
 363    ret = nouveau_screen_init(&screen->base, dev);
 364    if (ret) {
 365       nvc0_screen_destroy(pscreen);
 366       return NULL;
 367    }
 368    chan = screen->base.channel;
 369    chan->user_private = screen;
 370
 371    pscreen->winsys = ws;
 372    pscreen->destroy = nvc0_screen_destroy;
 373    pscreen->context_create = nvc0_create;
 374    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 375    pscreen->get_param = nvc0_screen_get_param;
 376    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 377    pscreen->get_paramf = nvc0_screen_get_paramf;
 378
 379    nvc0_screen_init_resource_functions(pscreen);
 380
 381    nouveau_screen_init_vdec(&screen->base);
 382
 383    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 384                         &screen->fence.bo);
 385    if (ret)
 386       goto fail;
 387    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 388    screen->fence.map = screen->fence.bo->map;
 389    nouveau_bo_unmap(screen->fence.bo);
 390    screen->base.fence.emit = nvc0_screen_fence_emit;
 391    screen->base.fence.update = nvc0_screen_fence_update;
 392
 393    for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
 394       ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
 395                            &screen->scratch.bo[i]);
 396       if (ret)
 397          goto fail;
 398    }
 399
 400    ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
 401    if (ret)
 402       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 403
 404    BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
 405    BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
 406    OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 407    OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 408    OUT_RING  (chan, 0);
 409
 410    ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
 411    if (ret)
 412       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 413
 414    BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
 415    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 416    OUT_RING  (chan, NVC0_2D_OPERATION_SRCCOPY);
 417    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 418    OUT_RING  (chan, 0);
 419    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 420    OUT_RING  (chan, 0);
 421    BEGIN_RING(chan, RING_2D_(0x0884), 1);
 422    OUT_RING  (chan, 0x3f);
 423    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 424    OUT_RING  (chan, 1);
 425
 426    ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
 427    if (ret)
 428       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 429
 430    BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
 431    BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
 432    OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 433    OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 434    OUT_RING  (chan, 0);
 435
 436    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 437    OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
 438
 439    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 440    OUT_RING  (chan, 1);
 441
 442    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 443    OUT_RING  (chan, 0);
 444    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 445    OUT_RING  (chan, 0);
 446    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 447    OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_MS1);
 448    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 449    OUT_RING  (chan, 0);
 450    BEGIN_RING(chan, RING_3D(LINE_WIDTH_SEPARATE), 1);
 451    OUT_RING  (chan, 1);
 452    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 453    OUT_RING  (chan, 0);
 454    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 455    OUT_RING  (chan, 1);
 456    BEGIN_RING(chan, RING_3D(BLEND_ENABLE_COMMON), 1);
 457    OUT_RING  (chan, 0);
 458    BEGIN_RING(chan, RING_3D(TEX_MISC), 1);
 459    OUT_RING  (chan, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 460
 461    nvc0_magic_3d_init(chan);
 462
 463    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
 464    if (ret)
 465       goto fail;
 466
 467    /* XXX: getting a page fault at the end of the code buffer every few
 468     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 469     */
 470    nouveau_resource_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 471
 472    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
 473                         &screen->uniforms);
 474    if (ret)
 475       goto fail;
 476
 477    /* auxiliary constants (6 user clip planes, base instance id) */
 478    BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 479    OUT_RING  (chan, 256);
 480    OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 481    OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 482    for (i = 0; i < 5; ++i) {
 483       BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
 484       OUT_RING  (chan, (15 << 4) | 1);
 485    }
 486
 487    screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
 488    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 489                         screen->tls_size, &screen->tls);
 490    if (ret)
 491       goto fail;
 492
 493    BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
 494    OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 495    OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 496    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
 497    OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 498    OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 499    OUT_RING  (chan, screen->tls_size >> 32);
 500    OUT_RING  (chan, screen->tls_size);
 501    BEGIN_RING(chan, RING_3D_(0x07a0), 1);
 502    OUT_RING  (chan, 0);
 503    BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
 504    OUT_RING  (chan, 0);
 505
 506    for (i = 0; i < 5; ++i) {
 507       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 508       OUT_RING  (chan, 0x54);
 509    }
 510    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 511    OUT_RING  (chan, 0);
 512
 513    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
 514                         &screen->vfetch_cache);
 515    if (ret)
 516       goto fail;
 517
 518    BEGIN_RING(chan, RING_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 519    OUT_RELOCh(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 520    OUT_RELOCl(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 521    OUT_RING  (chan, 3);
 522
 523    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
 524    if (ret)
 525       goto fail;
 526
 527    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 528    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 529    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 530    OUT_RING  (chan, NVC0_TIC_MAX_ENTRIES - 1);
 531
 532    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 533    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 534    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 535    OUT_RING  (chan, NVC0_TSC_MAX_ENTRIES - 1);
 536
 537    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 538    OUT_RING  (chan, 0);
 539    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 540    OUT_RING  (chan, 0);
 541    OUT_RING  (chan, 0);
 542    BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
 543    OUT_RING  (chan, 0x3f);
 544
 545    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 546    OUT_RING  (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 547    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 548    for (i = 0; i < 8 * 2; ++i)
 549       OUT_RING(chan, 0);
 550    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 551    OUT_RING  (chan, 0);
 552    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 553    OUT_RING  (chan, 0);
 554
 555    /* neither scissors, viewport nor stencil mask should affect clears */
 556    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 557    OUT_RING  (chan, 0);
 558
 559    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 560    OUT_RING  (chan, 1);
 561    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 562    OUT_RINGf (chan, 0.0f);
 563    OUT_RINGf (chan, 1.0f);
 564    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 565    OUT_RING  (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 566
 567    /* We use scissors instead of exact view volume clipping,
 568     * so they're always enabled.
 569     */
 570    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 571    OUT_RING  (chan, 1);
 572    OUT_RING  (chan, 8192 << 16);
 573    OUT_RING  (chan, 8192 << 16);
 574
 575 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 576
 577    i = 0;
 578    MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
 579    MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 580    MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
 581    MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
 582    MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 583    MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 584
 585    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 586    OUT_RING  (chan, 1);
 587    BEGIN_RING(chan, RING_3D(RT_SEPARATE_FRAG_DATA), 1);
 588    OUT_RING  (chan, 1);
 589    BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
 590    OUT_RING  (chan, 0x40);
 591    BEGIN_RING(chan, RING_3D(LAYER), 1);
 592    OUT_RING  (chan, 0);
 593    BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
 594    OUT_RING  (chan, 0x30);
 595    BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
 596    OUT_RING  (chan, 3);
 597    BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
 598    OUT_RING  (chan, 0x20);
 599    BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
 600    OUT_RING  (chan, 0x00);
 601
 602    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 603    OUT_RING  (chan, 0);
 604    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 605    OUT_RING  (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
 606
 607    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 608    OUT_RING  (chan, 1);
 609
 610    BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 611    OUT_RING  (chan, 0xab);
 612    OUT_RING  (chan, 0x00000000);
 613
 614    FIRE_RING (chan);
 615
 616    screen->tic.entries = CALLOC(4096, sizeof(void *));
 617    screen->tsc.entries = screen->tic.entries + 2048;
 618
 619    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 620
 621    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 622
 623    return pscreen;
 624
 625 fail:
 626    nvc0_screen_destroy(pscreen);
 627    return NULL;
 628 }
 629
 630 void
 631 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
 632 {
 633    struct nouveau_channel *chan = screen->base.channel;
 634
 635    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 636
 637    MARK_RING(chan, 5, 5);
 638    nouveau_bo_validate(chan, screen->text, flags);
 639    nouveau_bo_validate(chan, screen->uniforms, flags);
 640    nouveau_bo_validate(chan, screen->txc, flags);
 641    nouveau_bo_validate(chan, screen->vfetch_cache, flags);
 642
 643    if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
 644       nouveau_bo_validate(chan, screen->tls, flags);
 645 }
 646
 647 int
 648 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 649 {
 650    int i = screen->tic.next;
 651
 652    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 653       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 654
 655    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 656
 657    if (screen->tic.entries[i])
 658       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 659
 660    screen->tic.entries[i] = entry;
 661    return i;
 662 }
 663
 664 int
 665 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 666 {
 667    int i = screen->tsc.next;
 668
 669    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 670       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 671
 672    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 673
 674    if (screen->tsc.entries[i])
 675       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 676
 677    screen->tsc.entries[i] = entry;
 678    return i;
 679 }