src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nvc0_context.h"
  27 #include "nvc0_screen.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30 #include "nvc0_graph_macros.h"
  31
  32 static boolean
  33 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  34                                 enum pipe_format format,
  35                                 enum pipe_texture_target target,
  36                                 unsigned sample_count,
  37                                 unsigned bindings)
  38 {
  39    if (sample_count > 1)
  40       return FALSE;
  41
  42    if (!util_format_is_supported(format, bindings))
  43       return FALSE;
  44
  45    /* transfers & shared are always supported */
  46    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  47                  PIPE_BIND_TRANSFER_WRITE |
  48                  PIPE_BIND_SHARED);
  49
  50    return (nvc0_format_table[format].usage & bindings) == bindings;
  51 }
  52
  53 static int
  54 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  55 {
  56    switch (param) {
  57    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  58    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  59       return 32;
  60    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  61       return 64;
  62    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  63       return 13;
  64    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  65       return 10;
  66    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  67       return 13;
  68    case PIPE_CAP_ARRAY_TEXTURES:
  69       return 1;
  70    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  71    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  72    case PIPE_CAP_TEXTURE_SWIZZLE:
  73    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  74    case PIPE_CAP_NPOT_TEXTURES:
  75    case PIPE_CAP_ANISOTROPIC_FILTER:
  76       return 1;
  77    case PIPE_CAP_TWO_SIDED_STENCIL:
  78    case PIPE_CAP_DEPTH_CLAMP:
  79    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  80    case PIPE_CAP_POINT_SPRITE:
  81       return 1;
  82    case PIPE_CAP_GLSL:
  83    case PIPE_CAP_SM3:
  84       return 1;
  85    case PIPE_CAP_MAX_RENDER_TARGETS:
  86       return 8;
  87    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  88       return 1;
  89    case PIPE_CAP_TIMER_QUERY:
  90    case PIPE_CAP_OCCLUSION_QUERY:
  91       return 1;
  92    case PIPE_CAP_STREAM_OUTPUT:
  93       return 0;
  94    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  95    case PIPE_CAP_INDEP_BLEND_ENABLE:
  96    case PIPE_CAP_INDEP_BLEND_FUNC:
  97       return 1;
  98    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  99    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 100       return 1;
 101    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 102    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 103       return 0;
 104    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 105       return 0;
 106    case PIPE_CAP_PRIMITIVE_RESTART:
 107    case PIPE_CAP_TGSI_INSTANCEID:
 108    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 109    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 110       return 1;
 111    default:
 112       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 113       return 0;
 114    }
 115 }
 116
 117 static int
 118 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 119                              enum pipe_shader_cap param)
 120 {
 121    switch (shader) {
 122    case PIPE_SHADER_VERTEX:
 123       /*
 124    case PIPE_SHADER_TESSELLATION_CONTROL:
 125    case PIPE_SHADER_TESSELLATION_EVALUATION:
 126       */
 127    case PIPE_SHADER_GEOMETRY:
 128    case PIPE_SHADER_FRAGMENT:
 129       break;
 130    default:
 131       return 0;
 132    }
 133
 134    switch (param) {
 135    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 136    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 137    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 138    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 139       return 16384;
 140    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 141       return 4;
 142    case PIPE_SHADER_CAP_MAX_INPUTS:
 143       if (shader == PIPE_SHADER_VERTEX)
 144          return 32;
 145       return 0x300 / 16;
 146    case PIPE_SHADER_CAP_MAX_CONSTS:
 147       return 65536 / 16;
 148    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 149       return 14;
 150    case PIPE_SHADER_CAP_MAX_ADDRS:
 151       return 1;
 152    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 153    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 154       return shader != PIPE_SHADER_FRAGMENT;
 155    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 156    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 157       return 1;
 158    case PIPE_SHADER_CAP_MAX_PREDS:
 159       return 0;
 160    case PIPE_SHADER_CAP_MAX_TEMPS:
 161       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 162    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 163       return 1;
 164    case PIPE_SHADER_CAP_SUBROUTINES:
 165       return 0; /* please inline, or provide function declarations */
 166    default:
 167       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 168       return 0;
 169    }
 170 }
 171
 172 static float
 173 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 174 {
 175    switch (param) {
 176    case PIPE_CAP_MAX_LINE_WIDTH:
 177    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 178       return 10.0f;
 179    case PIPE_CAP_MAX_POINT_WIDTH:
 180    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 181       return 64.0f;
 182    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 183       return 16.0f;
 184    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 185       return 4.0f;
 186    default:
 187       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 188       return 0.0f;
 189    }
 190 }
 191
 192 static void
 193 nvc0_screen_destroy(struct pipe_screen *pscreen)
 194 {
 195    struct nvc0_screen *screen = nvc0_screen(pscreen);
 196
 197    nouveau_fence_wait(screen->base.fence.current);
 198    nouveau_fence_ref(NULL, &screen->base.fence.current);
 199
 200    nouveau_bo_ref(NULL, &screen->text);
 201    nouveau_bo_ref(NULL, &screen->tls);
 202    nouveau_bo_ref(NULL, &screen->txc);
 203    nouveau_bo_ref(NULL, &screen->fence.bo);
 204    nouveau_bo_ref(NULL, &screen->vfetch_cache);
 205
 206    nouveau_resource_destroy(&screen->text_heap);
 207
 208    if (screen->tic.entries)
 209       FREE(screen->tic.entries);
 210
 211    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 212
 213    nouveau_grobj_free(&screen->fermi);
 214    nouveau_grobj_free(&screen->eng2d);
 215    nouveau_grobj_free(&screen->m2mf);
 216
 217    nouveau_screen_fini(&screen->base);
 218
 219    FREE(screen);
 220 }
 221
 222 static int
 223 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 224                      unsigned size, const uint32_t *data)
 225 {
 226    struct nouveau_channel *chan = screen->base.channel;
 227
 228    size /= 4;
 229
 230    BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
 231    OUT_RING  (chan, (m - 0x3800) / 8);
 232    OUT_RING  (chan, pos);
 233    BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 234    OUT_RING  (chan, pos);
 235    OUT_RINGp (chan, data, size);
 236
 237    return pos + size;
 238 }
 239
 240 static void
 241 nvc0_magic_3d_init(struct nouveau_channel *chan)
 242 {
 243    BEGIN_RING(chan, RING_3D_(0x10cc), 1);
 244    OUT_RING  (chan, 0xff);
 245    BEGIN_RING(chan, RING_3D_(0x10e0), 2);
 246    OUT_RING(chan, 0xff);
 247    OUT_RING(chan, 0xff);
 248    BEGIN_RING(chan, RING_3D_(0x10ec), 2);
 249    OUT_RING(chan, 0xff);
 250    OUT_RING(chan, 0xff);
 251    BEGIN_RING(chan, RING_3D_(0x074c), 1);
 252    OUT_RING  (chan, 0x3f);
 253
 254    BEGIN_RING(chan, RING_3D_(0x16a8), 1);
 255    OUT_RING  (chan, (3 << 16) | 3);
 256    BEGIN_RING(chan, RING_3D_(0x1794), 1);
 257    OUT_RING  (chan, (2 << 16) | 2);
 258    BEGIN_RING(chan, RING_3D_(0x0de8), 1);
 259    OUT_RING  (chan, 1);
 260
 261 #if 0 /* software method */
 262    BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
 263    OUT_RING  (chan, 0);
 264 #endif
 265
 266    BEGIN_RING(chan, RING_3D_(0x12ac), 1);
 267    OUT_RING  (chan, 0);
 268    BEGIN_RING(chan, RING_3D_(0x0218), 1);
 269    OUT_RING  (chan, 0x10);
 270    BEGIN_RING(chan, RING_3D_(0x10fc), 1);
 271    OUT_RING  (chan, 0x10);
 272    BEGIN_RING(chan, RING_3D_(0x1290), 1);
 273    OUT_RING  (chan, 0x10);
 274    BEGIN_RING(chan, RING_3D_(0x12d8), 2);
 275    OUT_RING  (chan, 0x10);
 276    OUT_RING  (chan, 0x10);
 277    BEGIN_RING(chan, RING_3D_(0x06d4), 1);
 278    OUT_RING  (chan, 8);
 279    BEGIN_RING(chan, RING_3D_(0x1140), 1);
 280    OUT_RING  (chan, 0x10);
 281    BEGIN_RING(chan, RING_3D_(0x1610), 1);
 282    OUT_RING  (chan, 0xe);
 283
 284    BEGIN_RING(chan, RING_3D_(0x164c), 1);
 285    OUT_RING  (chan, 1 << 12);
 286    BEGIN_RING(chan, RING_3D_(0x151c), 1);
 287    OUT_RING  (chan, 1);
 288    BEGIN_RING(chan, RING_3D_(0x030c), 1);
 289    OUT_RING  (chan, 0);
 290    BEGIN_RING(chan, RING_3D_(0x0300), 1);
 291    OUT_RING  (chan, 3);
 292 #if 0 /* software method */
 293    BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
 294    OUT_RING  (chan, 0);
 295 #endif
 296    BEGIN_RING(chan, RING_3D_(0x02d0), 1);
 297    OUT_RING  (chan, 0x1f40);
 298    BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
 299    OUT_RING  (chan, 1);
 300    BEGIN_RING(chan, RING_3D_(0x19c0), 1);
 301    OUT_RING  (chan, 1);
 302    BEGIN_RING(chan, RING_3D_(0x075c), 1);
 303    OUT_RING  (chan, 3);
 304 }
 305
 306 static void
 307 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 308 {
 309    struct nvc0_screen *screen = nvc0_screen(pscreen);
 310    struct nouveau_channel *chan = screen->base.channel;
 311
 312    MARK_RING (chan, 5, 2);
 313    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 314    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 315    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 316    OUT_RING  (chan, sequence);
 317    OUT_RING  (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 318               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 319 }
 320
 321 static u32
 322 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 323 {
 324    struct nvc0_screen *screen = nvc0_screen(pscreen);
 325    return screen->fence.map[0];
 326 }
 327
 328 #define FAIL_SCREEN_INIT(str, err)                    \
 329    do {                                               \
 330       NOUVEAU_ERR(str, err);                          \
 331       nvc0_screen_destroy(pscreen);                   \
 332       return NULL;                                    \
 333    } while(0)
 334
 335 struct pipe_screen *
 336 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 337 {
 338    struct nvc0_screen *screen;
 339    struct nouveau_channel *chan;
 340    struct pipe_screen *pscreen;
 341    int ret;
 342    unsigned i;
 343
 344    screen = CALLOC_STRUCT(nvc0_screen);
 345    if (!screen)
 346       return NULL;
 347    pscreen = &screen->base.base;
 348
 349    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 350
 351    ret = nouveau_screen_init(&screen->base, dev);
 352    if (ret) {
 353       nvc0_screen_destroy(pscreen);
 354       return NULL;
 355    }
 356    chan = screen->base.channel;
 357
 358    pscreen->winsys = ws;
 359    pscreen->destroy = nvc0_screen_destroy;
 360    pscreen->context_create = nvc0_create;
 361    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 362    pscreen->get_param = nvc0_screen_get_param;
 363    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 364    pscreen->get_paramf = nvc0_screen_get_paramf;
 365
 366    nvc0_screen_init_resource_functions(pscreen);
 367
 368    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 369                         &screen->fence.bo);
 370    if (ret)
 371       goto fail;
 372    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 373    screen->fence.map = screen->fence.bo->map;
 374    nouveau_bo_unmap(screen->fence.bo);
 375    screen->base.fence.emit = nvc0_screen_fence_emit;
 376    screen->base.fence.update = nvc0_screen_fence_update;
 377
 378    for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
 379       ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
 380                            &screen->scratch.bo[i]);
 381       if (ret)
 382          goto fail;
 383    }
 384
 385    ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
 386    if (ret)
 387       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 388
 389    BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
 390    BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
 391    OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 392    OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 393    OUT_RING  (chan, 0);
 394
 395    ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
 396    if (ret)
 397       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 398
 399    BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
 400    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 401    OUT_RING  (chan, NVC0_2D_OPERATION_SRCCOPY);
 402    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 403    OUT_RING  (chan, 0);
 404    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 405    OUT_RING  (chan, 0);
 406    BEGIN_RING(chan, RING_2D_(0x0884), 1);
 407    OUT_RING  (chan, 0x3f);
 408    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 409    OUT_RING  (chan, 1);
 410
 411    ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
 412    if (ret)
 413       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 414
 415    BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
 416    BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
 417    OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 418    OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 419    OUT_RING  (chan, 0);
 420
 421    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 422    OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
 423
 424    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 425    OUT_RING  (chan, 1);
 426
 427    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 428    OUT_RING  (chan, 0);
 429    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 430    OUT_RING  (chan, 0);
 431    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 432    OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
 433    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 434    OUT_RING  (chan, 0);
 435    BEGIN_RING(chan, RING_3D(LINE_WIDTH_SEPARATE), 1);
 436    OUT_RING  (chan, 1);
 437    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 438    OUT_RING  (chan, 0);
 439    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 440    OUT_RING  (chan, 1);
 441    BEGIN_RING(chan, RING_3D(BLEND_ENABLE_COMMON), 1);
 442    OUT_RING  (chan, 0);
 443
 444    nvc0_magic_3d_init(chan);
 445
 446    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
 447    if (ret)
 448       goto fail;
 449
 450    nouveau_resource_init(&screen->text_heap, 0, 1 << 20);
 451
 452    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
 453                         &screen->uniforms);
 454    if (ret)
 455       goto fail;
 456
 457    /* auxiliary constants (6 user clip planes, base instance id) */
 458    BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 459    OUT_RING  (chan, 256);
 460    OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 461    OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 462    for (i = 0; i < 5; ++i) {
 463       BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
 464       OUT_RING  (chan, (15 << 4) | 1);
 465    }
 466
 467    screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
 468    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 469                         screen->tls_size, &screen->tls);
 470    if (ret)
 471       goto fail;
 472
 473    BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
 474    OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 475    OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 476    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
 477    OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 478    OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 479    OUT_RING  (chan, screen->tls_size >> 32);
 480    OUT_RING  (chan, screen->tls_size);
 481    BEGIN_RING(chan, RING_3D_(0x07a0), 1);
 482    OUT_RING  (chan, 0);
 483    BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
 484    OUT_RING  (chan, 0);
 485
 486    for (i = 0; i < 5; ++i) {
 487       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 488       OUT_RING  (chan, 0x54);
 489    }
 490    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 491    OUT_RING  (chan, 0);
 492
 493    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
 494                         &screen->vfetch_cache);
 495    if (ret)
 496       goto fail;
 497
 498    BEGIN_RING(chan, RING_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 499    OUT_RELOCh(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 500    OUT_RELOCl(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 501    OUT_RING  (chan, 3);
 502
 503    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
 504    if (ret)
 505       goto fail;
 506
 507    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 508    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 509    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 510    OUT_RING  (chan, NVC0_TIC_MAX_ENTRIES - 1);
 511
 512    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 513    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 514    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 515    OUT_RING  (chan, NVC0_TSC_MAX_ENTRIES - 1);
 516
 517    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 518    OUT_RING  (chan, 0);
 519    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 520    OUT_RING  (chan, 0);
 521    OUT_RING  (chan, 0);
 522    BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
 523    OUT_RING  (chan, 0x3f);
 524
 525    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 526    OUT_RING  (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 527    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 528    for (i = 0; i < 8 * 2; ++i)
 529       OUT_RING(chan, 0);
 530    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 531    OUT_RING  (chan, 0);
 532    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 533    OUT_RING  (chan, 0);
 534
 535    /* neither scissors, viewport nor stencil mask should affect clears */
 536    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 537    OUT_RING  (chan, 0);
 538
 539    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 540    OUT_RING  (chan, 1);
 541    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 542    OUT_RINGf (chan, 0.0f);
 543    OUT_RINGf (chan, 1.0f);
 544    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 545    OUT_RING  (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 546
 547    /* We use scissors instead of exact view volume clipping,
 548     * so they're always enabled.
 549     */
 550    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 551    OUT_RING  (chan, 1);
 552    OUT_RING  (chan, 8192 << 16);
 553    OUT_RING  (chan, 8192 << 16);
 554
 555 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 556
 557    i = 0;
 558    MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
 559    MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 560    MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
 561    MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
 562    MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 563    MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 564
 565    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 566    OUT_RING  (chan, 1);
 567    BEGIN_RING(chan, RING_3D(RT_SEPARATE_FRAG_DATA), 1);
 568    OUT_RING  (chan, 1);
 569    BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
 570    OUT_RING  (chan, 0x40);
 571    BEGIN_RING(chan, RING_3D(LAYER), 1);
 572    OUT_RING  (chan, 0);
 573    BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
 574    OUT_RING  (chan, 0x30);
 575    BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
 576    OUT_RING  (chan, 3);
 577    BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
 578    OUT_RING  (chan, 0x20);
 579    BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
 580    OUT_RING  (chan, 0x00);
 581
 582    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 583    OUT_RING  (chan, 0);
 584    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 585    OUT_RING  (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
 586
 587    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 588    OUT_RING  (chan, 1);
 589
 590    BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 591    OUT_RING  (chan, 0xab);
 592    OUT_RING  (chan, 0x00000000);
 593
 594    FIRE_RING (chan);
 595
 596    screen->tic.entries = CALLOC(4096, sizeof(void *));
 597    screen->tsc.entries = screen->tic.entries + 2048;
 598
 599    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 600
 601    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 602
 603    return pscreen;
 604
 605 fail:
 606    nvc0_screen_destroy(pscreen);
 607    return NULL;
 608 }
 609
 610 void
 611 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
 612 {
 613    struct nouveau_channel *chan = screen->base.channel;
 614
 615    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 616
 617    MARK_RING(chan, 5, 5);
 618    nouveau_bo_validate(chan, screen->text, flags);
 619    nouveau_bo_validate(chan, screen->uniforms, flags);
 620    nouveau_bo_validate(chan, screen->txc, flags);
 621    nouveau_bo_validate(chan, screen->vfetch_cache, flags);
 622
 623    if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
 624       nouveau_bo_validate(chan, screen->tls, flags);
 625 }
 626
 627 int
 628 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 629 {
 630    int i = screen->tic.next;
 631
 632    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 633       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 634
 635    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 636
 637    if (screen->tic.entries[i])
 638       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 639
 640    screen->tic.entries[i] = entry;
 641    return i;
 642 }
 643
 644 int
 645 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 646 {
 647    int i = screen->tsc.next;
 648
 649    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 650       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 651
 652    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 653
 654    if (screen->tsc.entries[i])
 655       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 656
 657    screen->tsc.entries[i] = entry;
 658    return i;
 659 }