src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nvc0_context.h"
  27 #include "nvc0_screen.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30 #include "nvc0_graph_macros.h"
  31
  32 static boolean
  33 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  34                                 enum pipe_format format,
  35                                 enum pipe_texture_target target,
  36                                 unsigned sample_count,
  37                                 unsigned bindings)
  38 {
  39    if (sample_count > 1)
  40       return FALSE;
  41
  42    if (!util_format_s3tc_enabled) {
  43       switch (format) {
  44       case PIPE_FORMAT_DXT1_RGB:
  45       case PIPE_FORMAT_DXT1_RGBA:
  46       case PIPE_FORMAT_DXT3_RGBA:
  47       case PIPE_FORMAT_DXT5_RGBA:
  48          return FALSE;
  49       default:
  50          break;
  51       }
  52    }
  53
  54    /* transfers & shared are always supported */
  55    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  56                  PIPE_BIND_TRANSFER_WRITE |
  57                  PIPE_BIND_SHARED);
  58
  59    return (nvc0_format_table[format].usage & bindings) == bindings;
  60 }
  61
  62 static int
  63 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  64 {
  65    switch (param) {
  66    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  67    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  68       return 32;
  69    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  70       return 64;
  71    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  72       return 13;
  73    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  74       return 10;
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 13;
  77    case PIPE_CAP_ARRAY_TEXTURES:
  78       return 1;
  79    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  80    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  81    case PIPE_CAP_TEXTURE_SWIZZLE:
  82    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  83    case PIPE_CAP_NPOT_TEXTURES:
  84    case PIPE_CAP_ANISOTROPIC_FILTER:
  85       return 1;
  86    case PIPE_CAP_TWO_SIDED_STENCIL:
  87    case PIPE_CAP_DEPTH_CLAMP:
  88    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  89    case PIPE_CAP_POINT_SPRITE:
  90       return 1;
  91    case PIPE_CAP_GLSL:
  92    case PIPE_CAP_SM3:
  93       return 1;
  94    case PIPE_CAP_MAX_RENDER_TARGETS:
  95       return 8;
  96    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  97       return 1;
  98    case PIPE_CAP_TIMER_QUERY:
  99    case PIPE_CAP_OCCLUSION_QUERY:
 100       return 1;
 101    case PIPE_CAP_STREAM_OUTPUT:
 102       return 0;
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104    case PIPE_CAP_INDEP_BLEND_ENABLE:
 105    case PIPE_CAP_INDEP_BLEND_FUNC:
 106       return 1;
 107    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 108    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 109       return 1;
 110    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 111    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 112       return 0;
 113    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 114       return 0;
 115    case PIPE_CAP_PRIMITIVE_RESTART:
 116    case PIPE_CAP_TGSI_INSTANCEID:
 117    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 118    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 119       return 1;
 120    default:
 121       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 122       return 0;
 123    }
 124 }
 125
 126 static int
 127 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 128                              enum pipe_shader_cap param)
 129 {
 130    switch (shader) {
 131    case PIPE_SHADER_VERTEX:
 132       /*
 133    case PIPE_SHADER_TESSELLATION_CONTROL:
 134    case PIPE_SHADER_TESSELLATION_EVALUATION:
 135       */
 136    case PIPE_SHADER_GEOMETRY:
 137    case PIPE_SHADER_FRAGMENT:
 138       break;
 139    default:
 140       return 0;
 141    }
 142
 143    switch (param) {
 144    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 145    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 146    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 147    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 148       return 16384;
 149    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 150       return 4;
 151    case PIPE_SHADER_CAP_MAX_INPUTS:
 152       if (shader == PIPE_SHADER_VERTEX)
 153          return 32;
 154       return 0x300 / 16;
 155    case PIPE_SHADER_CAP_MAX_CONSTS:
 156       return 65536 / 16;
 157    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 158       return 14;
 159    case PIPE_SHADER_CAP_MAX_ADDRS:
 160       return 1;
 161    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 162    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 163       return shader != PIPE_SHADER_FRAGMENT;
 164    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 165    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 166       return 1;
 167    case PIPE_SHADER_CAP_MAX_PREDS:
 168       return 0;
 169    case PIPE_SHADER_CAP_MAX_TEMPS:
 170       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 171    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 172       return 1;
 173    case PIPE_SHADER_CAP_SUBROUTINES:
 174       return 0; /* please inline, or provide function declarations */
 175    default:
 176       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 177       return 0;
 178    }
 179 }
 180
 181 static float
 182 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 183 {
 184    switch (param) {
 185    case PIPE_CAP_MAX_LINE_WIDTH:
 186    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 187       return 10.0f;
 188    case PIPE_CAP_MAX_POINT_WIDTH:
 189    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 190       return 64.0f;
 191    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 192       return 16.0f;
 193    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 194       return 4.0f;
 195    default:
 196       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 197       return 0.0f;
 198    }
 199 }
 200
 201 static void
 202 nvc0_screen_destroy(struct pipe_screen *pscreen)
 203 {
 204    struct nvc0_screen *screen = nvc0_screen(pscreen);
 205
 206    nouveau_fence_wait(screen->base.fence.current);
 207    nouveau_fence_ref(NULL, &screen->base.fence.current);
 208
 209    nouveau_bo_ref(NULL, &screen->text);
 210    nouveau_bo_ref(NULL, &screen->tls);
 211    nouveau_bo_ref(NULL, &screen->txc);
 212    nouveau_bo_ref(NULL, &screen->fence.bo);
 213    nouveau_bo_ref(NULL, &screen->vfetch_cache);
 214
 215    nouveau_resource_destroy(&screen->text_heap);
 216
 217    if (screen->tic.entries)
 218       FREE(screen->tic.entries);
 219
 220    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 221
 222    nouveau_grobj_free(&screen->fermi);
 223    nouveau_grobj_free(&screen->eng2d);
 224    nouveau_grobj_free(&screen->m2mf);
 225
 226    nouveau_screen_fini(&screen->base);
 227
 228    FREE(screen);
 229 }
 230
 231 static int
 232 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 233                      unsigned size, const uint32_t *data)
 234 {
 235    struct nouveau_channel *chan = screen->base.channel;
 236
 237    size /= 4;
 238
 239    BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
 240    OUT_RING  (chan, (m - 0x3800) / 8);
 241    OUT_RING  (chan, pos);
 242    BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 243    OUT_RING  (chan, pos);
 244    OUT_RINGp (chan, data, size);
 245
 246    return pos + size;
 247 }
 248
 249 static void
 250 nvc0_magic_3d_init(struct nouveau_channel *chan)
 251 {
 252    BEGIN_RING(chan, RING_3D_(0x10cc), 1);
 253    OUT_RING  (chan, 0xff);
 254    BEGIN_RING(chan, RING_3D_(0x10e0), 2);
 255    OUT_RING(chan, 0xff);
 256    OUT_RING(chan, 0xff);
 257    BEGIN_RING(chan, RING_3D_(0x10ec), 2);
 258    OUT_RING(chan, 0xff);
 259    OUT_RING(chan, 0xff);
 260    BEGIN_RING(chan, RING_3D_(0x074c), 1);
 261    OUT_RING  (chan, 0x3f);
 262
 263    BEGIN_RING(chan, RING_3D_(0x16a8), 1);
 264    OUT_RING  (chan, (3 << 16) | 3);
 265    BEGIN_RING(chan, RING_3D_(0x1794), 1);
 266    OUT_RING  (chan, (2 << 16) | 2);
 267    BEGIN_RING(chan, RING_3D_(0x0de8), 1);
 268    OUT_RING  (chan, 1);
 269
 270 #if 0 /* software method */
 271    BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
 272    OUT_RING  (chan, 0);
 273 #endif
 274
 275    BEGIN_RING(chan, RING_3D_(0x12ac), 1);
 276    OUT_RING  (chan, 0);
 277    BEGIN_RING(chan, RING_3D_(0x0218), 1);
 278    OUT_RING  (chan, 0x10);
 279    BEGIN_RING(chan, RING_3D_(0x10fc), 1);
 280    OUT_RING  (chan, 0x10);
 281    BEGIN_RING(chan, RING_3D_(0x1290), 1);
 282    OUT_RING  (chan, 0x10);
 283    BEGIN_RING(chan, RING_3D_(0x12d8), 2);
 284    OUT_RING  (chan, 0x10);
 285    OUT_RING  (chan, 0x10);
 286    BEGIN_RING(chan, RING_3D_(0x06d4), 1);
 287    OUT_RING  (chan, 8);
 288    BEGIN_RING(chan, RING_3D_(0x1140), 1);
 289    OUT_RING  (chan, 0x10);
 290    BEGIN_RING(chan, RING_3D_(0x1610), 1);
 291    OUT_RING  (chan, 0xe);
 292
 293    BEGIN_RING(chan, RING_3D_(0x164c), 1);
 294    OUT_RING  (chan, 1 << 12);
 295    BEGIN_RING(chan, RING_3D_(0x151c), 1);
 296    OUT_RING  (chan, 1);
 297    BEGIN_RING(chan, RING_3D_(0x030c), 1);
 298    OUT_RING  (chan, 0);
 299    BEGIN_RING(chan, RING_3D_(0x0300), 1);
 300    OUT_RING  (chan, 3);
 301 #if 0 /* software method */
 302    BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
 303    OUT_RING  (chan, 0);
 304 #endif
 305    BEGIN_RING(chan, RING_3D_(0x02d0), 1);
 306    OUT_RING  (chan, 0x1f40);
 307    BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
 308    OUT_RING  (chan, 1);
 309    BEGIN_RING(chan, RING_3D_(0x19c0), 1);
 310    OUT_RING  (chan, 1);
 311    BEGIN_RING(chan, RING_3D_(0x075c), 1);
 312    OUT_RING  (chan, 3);
 313
 314    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 315    OUT_RING  (chan, 0);
 316 }
 317
 318 static void
 319 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 320 {
 321    struct nvc0_screen *screen = nvc0_screen(pscreen);
 322    struct nouveau_channel *chan = screen->base.channel;
 323
 324    MARK_RING (chan, 5, 2);
 325    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 326    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 327    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 328    OUT_RING  (chan, sequence);
 329    OUT_RING  (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 330               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 331 }
 332
 333 static u32
 334 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 335 {
 336    struct nvc0_screen *screen = nvc0_screen(pscreen);
 337    return screen->fence.map[0];
 338 }
 339
 340 #define FAIL_SCREEN_INIT(str, err)                    \
 341    do {                                               \
 342       NOUVEAU_ERR(str, err);                          \
 343       nvc0_screen_destroy(pscreen);                   \
 344       return NULL;                                    \
 345    } while(0)
 346
 347 struct pipe_screen *
 348 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 349 {
 350    struct nvc0_screen *screen;
 351    struct nouveau_channel *chan;
 352    struct pipe_screen *pscreen;
 353    int ret;
 354    unsigned i;
 355
 356    screen = CALLOC_STRUCT(nvc0_screen);
 357    if (!screen)
 358       return NULL;
 359    pscreen = &screen->base.base;
 360
 361    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 362
 363    ret = nouveau_screen_init(&screen->base, dev);
 364    if (ret) {
 365       nvc0_screen_destroy(pscreen);
 366       return NULL;
 367    }
 368    chan = screen->base.channel;
 369
 370    pscreen->winsys = ws;
 371    pscreen->destroy = nvc0_screen_destroy;
 372    pscreen->context_create = nvc0_create;
 373    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 374    pscreen->get_param = nvc0_screen_get_param;
 375    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 376    pscreen->get_paramf = nvc0_screen_get_paramf;
 377
 378    nvc0_screen_init_resource_functions(pscreen);
 379
 380    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 381                         &screen->fence.bo);
 382    if (ret)
 383       goto fail;
 384    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 385    screen->fence.map = screen->fence.bo->map;
 386    nouveau_bo_unmap(screen->fence.bo);
 387    screen->base.fence.emit = nvc0_screen_fence_emit;
 388    screen->base.fence.update = nvc0_screen_fence_update;
 389
 390    for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
 391       ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
 392                            &screen->scratch.bo[i]);
 393       if (ret)
 394          goto fail;
 395    }
 396
 397    ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
 398    if (ret)
 399       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 400
 401    BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
 402    BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
 403    OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 404    OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 405    OUT_RING  (chan, 0);
 406
 407    ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
 408    if (ret)
 409       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 410
 411    BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
 412    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 413    OUT_RING  (chan, NVC0_2D_OPERATION_SRCCOPY);
 414    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 415    OUT_RING  (chan, 0);
 416    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 417    OUT_RING  (chan, 0);
 418    BEGIN_RING(chan, RING_2D_(0x0884), 1);
 419    OUT_RING  (chan, 0x3f);
 420    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 421    OUT_RING  (chan, 1);
 422
 423    ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
 424    if (ret)
 425       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 426
 427    BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
 428    BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
 429    OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 430    OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 431    OUT_RING  (chan, 0);
 432
 433    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 434    OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
 435
 436    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 437    OUT_RING  (chan, 1);
 438
 439    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 440    OUT_RING  (chan, 0);
 441    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 442    OUT_RING  (chan, 0);
 443    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 444    OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
 445    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 446    OUT_RING  (chan, 0);
 447    BEGIN_RING(chan, RING_3D(LINE_WIDTH_SEPARATE), 1);
 448    OUT_RING  (chan, 1);
 449    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 450    OUT_RING  (chan, 0);
 451    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 452    OUT_RING  (chan, 1);
 453    BEGIN_RING(chan, RING_3D(BLEND_ENABLE_COMMON), 1);
 454    OUT_RING  (chan, 0);
 455
 456    nvc0_magic_3d_init(chan);
 457
 458    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
 459    if (ret)
 460       goto fail;
 461
 462    nouveau_resource_init(&screen->text_heap, 0, 1 << 20);
 463
 464    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
 465                         &screen->uniforms);
 466    if (ret)
 467       goto fail;
 468
 469    /* auxiliary constants (6 user clip planes, base instance id) */
 470    BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 471    OUT_RING  (chan, 256);
 472    OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 473    OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 474    for (i = 0; i < 5; ++i) {
 475       BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
 476       OUT_RING  (chan, (15 << 4) | 1);
 477    }
 478
 479    screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
 480    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 481                         screen->tls_size, &screen->tls);
 482    if (ret)
 483       goto fail;
 484
 485    BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
 486    OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 487    OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 488    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
 489    OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 490    OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 491    OUT_RING  (chan, screen->tls_size >> 32);
 492    OUT_RING  (chan, screen->tls_size);
 493    BEGIN_RING(chan, RING_3D_(0x07a0), 1);
 494    OUT_RING  (chan, 0);
 495    BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
 496    OUT_RING  (chan, 0);
 497
 498    for (i = 0; i < 5; ++i) {
 499       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 500       OUT_RING  (chan, 0x54);
 501    }
 502    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 503    OUT_RING  (chan, 0);
 504
 505    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
 506                         &screen->vfetch_cache);
 507    if (ret)
 508       goto fail;
 509
 510    BEGIN_RING(chan, RING_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 511    OUT_RELOCh(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 512    OUT_RELOCl(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 513    OUT_RING  (chan, 3);
 514
 515    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
 516    if (ret)
 517       goto fail;
 518
 519    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 520    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 521    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 522    OUT_RING  (chan, NVC0_TIC_MAX_ENTRIES - 1);
 523
 524    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 525    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 526    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 527    OUT_RING  (chan, NVC0_TSC_MAX_ENTRIES - 1);
 528
 529    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 530    OUT_RING  (chan, 0);
 531    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 532    OUT_RING  (chan, 0);
 533    OUT_RING  (chan, 0);
 534    BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
 535    OUT_RING  (chan, 0x3f);
 536
 537    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 538    OUT_RING  (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 539    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 540    for (i = 0; i < 8 * 2; ++i)
 541       OUT_RING(chan, 0);
 542    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 543    OUT_RING  (chan, 0);
 544    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 545    OUT_RING  (chan, 0);
 546
 547    /* neither scissors, viewport nor stencil mask should affect clears */
 548    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 549    OUT_RING  (chan, 0);
 550
 551    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 552    OUT_RING  (chan, 1);
 553    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 554    OUT_RINGf (chan, 0.0f);
 555    OUT_RINGf (chan, 1.0f);
 556    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 557    OUT_RING  (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 558
 559    /* We use scissors instead of exact view volume clipping,
 560     * so they're always enabled.
 561     */
 562    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 563    OUT_RING  (chan, 1);
 564    OUT_RING  (chan, 8192 << 16);
 565    OUT_RING  (chan, 8192 << 16);
 566
 567    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 568    OUT_RING  (chan, 0);
 569    BEGIN_RING(chan, RING_3D_(0x3484), 1);
 570    OUT_RING  (chan, 0);
 571    BEGIN_RING(chan, RING_3D_(0x0dbc), 1);
 572    OUT_RING  (chan, 0x00010000);
 573    BEGIN_RING(chan, RING_3D_(0x0dd8), 1);
 574    OUT_RING  (chan, 0xff800006);
 575    BEGIN_RING(chan, RING_3D_(0x3488), 1);
 576    OUT_RING  (chan, 0);
 577
 578 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 579
 580    i = 0;
 581    MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
 582    MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 583    MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
 584    MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
 585    MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 586    MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 587
 588    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 589    OUT_RING  (chan, 1);
 590    BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
 591    OUT_RING  (chan, 0x40);
 592    BEGIN_RING(chan, RING_3D(LAYER), 1);
 593    OUT_RING  (chan, 0);
 594    BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
 595    OUT_RING  (chan, 0x30);
 596    BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
 597    OUT_RING  (chan, 3);
 598    BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
 599    OUT_RING  (chan, 0x20);
 600    BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
 601    OUT_RING  (chan, 0x00);
 602
 603    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 604    OUT_RING  (chan, 0);
 605    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 606    OUT_RING  (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
 607
 608    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 609    OUT_RING  (chan, 1);
 610
 611    BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 612    OUT_RING  (chan, 0xab);
 613    OUT_RING  (chan, 0x00000000);
 614
 615    FIRE_RING (chan);
 616
 617    screen->tic.entries = CALLOC(4096, sizeof(void *));
 618    screen->tsc.entries = screen->tic.entries + 2048;
 619
 620    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 621
 622    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 623
 624    return pscreen;
 625
 626 fail:
 627    nvc0_screen_destroy(pscreen);
 628    return NULL;
 629 }
 630
 631 void
 632 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
 633 {
 634    struct nouveau_channel *chan = screen->base.channel;
 635
 636    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 637
 638    MARK_RING(chan, 5, 5);
 639    nouveau_bo_validate(chan, screen->text, flags);
 640    nouveau_bo_validate(chan, screen->uniforms, flags);
 641    nouveau_bo_validate(chan, screen->txc, flags);
 642    nouveau_bo_validate(chan, screen->vfetch_cache, flags);
 643
 644    if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
 645       nouveau_bo_validate(chan, screen->tls, flags);
 646 }
 647
 648 int
 649 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 650 {
 651    int i = screen->tic.next;
 652
 653    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 654       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 655
 656    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 657
 658    if (screen->tic.entries[i])
 659       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 660
 661    screen->tic.entries[i] = entry;
 662    return i;
 663 }
 664
 665 int
 666 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 667 {
 668    int i = screen->tsc.next;
 669
 670    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 671       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 672
 673    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 674
 675    if (screen->tsc.entries[i])
 676       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 677
 678    screen->tsc.entries[i] = entry;
 679    return i;
 680 }