src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nvc0_context.h"
  27 #include "nvc0_screen.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30 #include "nvc0_graph_macros.h"
  31
  32 static boolean
  33 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  34                                 enum pipe_format format,
  35                                 enum pipe_texture_target target,
  36                                 unsigned sample_count,
  37                                 unsigned bindings)
  38 {
  39    if (sample_count > 1)
  40       return FALSE;
  41
  42    if (!util_format_s3tc_enabled) {
  43       switch (format) {
  44       case PIPE_FORMAT_DXT1_RGB:
  45       case PIPE_FORMAT_DXT1_RGBA:
  46       case PIPE_FORMAT_DXT3_RGBA:
  47       case PIPE_FORMAT_DXT5_RGBA:
  48          return FALSE;
  49       default:
  50          break;
  51       }
  52    }
  53
  54    /* transfers & shared are always supported */
  55    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  56                  PIPE_BIND_TRANSFER_WRITE |
  57                  PIPE_BIND_SHARED);
  58
  59    return (nvc0_format_table[format].usage & bindings) == bindings;
  60 }
  61
  62 static int
  63 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  64 {
  65    switch (param) {
  66    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  67    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  68       return 32;
  69    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  70       return 64;
  71    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  72       return 13;
  73    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  74       return 10;
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 13;
  77    case PIPE_CAP_ARRAY_TEXTURES:
  78       return 1;
  79    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  80    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  81    case PIPE_CAP_TEXTURE_SWIZZLE:
  82    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  83    case PIPE_CAP_NPOT_TEXTURES:
  84    case PIPE_CAP_ANISOTROPIC_FILTER:
  85       return 1;
  86    case PIPE_CAP_TWO_SIDED_STENCIL:
  87    case PIPE_CAP_DEPTH_CLAMP:
  88    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  89    case PIPE_CAP_POINT_SPRITE:
  90       return 1;
  91    case PIPE_CAP_GLSL:
  92    case PIPE_CAP_SM3:
  93       return 1;
  94    case PIPE_CAP_MAX_RENDER_TARGETS:
  95       return 8;
  96    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  97       return 1;
  98    case PIPE_CAP_TIMER_QUERY:
  99    case PIPE_CAP_OCCLUSION_QUERY:
 100       return 1;
 101    case PIPE_CAP_STREAM_OUTPUT:
 102       return 0;
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104    case PIPE_CAP_INDEP_BLEND_ENABLE:
 105    case PIPE_CAP_INDEP_BLEND_FUNC:
 106       return 1;
 107    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 108    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 109       return 1;
 110    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 111    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 112       return 0;
 113    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 114       return 0;
 115    case PIPE_CAP_PRIMITIVE_RESTART:
 116    case PIPE_CAP_TGSI_INSTANCEID:
 117    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 118       return 1;
 119    default:
 120       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 121       return 0;
 122    }
 123 }
 124
 125 static int
 126 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 127                              enum pipe_shader_cap param)
 128 {
 129    switch (shader) {
 130    case PIPE_SHADER_VERTEX:
 131       /*
 132    case PIPE_SHADER_TESSELLATION_CONTROL:
 133    case PIPE_SHADER_TESSELLATION_EVALUATION:
 134       */
 135    case PIPE_SHADER_GEOMETRY:
 136    case PIPE_SHADER_FRAGMENT:
 137       break;
 138    default:
 139       return 0;
 140    }
 141
 142    switch (param) {
 143    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 144    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 145    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 146    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 147       return 16384;
 148    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 149       return 4;
 150    case PIPE_SHADER_CAP_MAX_INPUTS:
 151       if (shader == PIPE_SHADER_VERTEX)
 152          return 32;
 153       return 0x300 / 16;
 154    case PIPE_SHADER_CAP_MAX_CONSTS:
 155       return 65536 / 16;
 156    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 157       return 14;
 158    case PIPE_SHADER_CAP_MAX_ADDRS:
 159       return 1;
 160    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 161    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 162       return shader != PIPE_SHADER_FRAGMENT;
 163    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 164    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 165       return 1;
 166    case PIPE_SHADER_CAP_MAX_PREDS:
 167       return 0;
 168    case PIPE_SHADER_CAP_MAX_TEMPS:
 169       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 170    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 171       return 1;
 172    case PIPE_SHADER_CAP_SUBROUTINES:
 173       return 0; /* please inline, or provide function declarations */
 174    default:
 175       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 176       return 0;
 177    }
 178 }
 179
 180 static float
 181 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 182 {
 183    switch (param) {
 184    case PIPE_CAP_MAX_LINE_WIDTH:
 185    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 186       return 10.0f;
 187    case PIPE_CAP_MAX_POINT_WIDTH:
 188    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 189       return 64.0f;
 190    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 191       return 16.0f;
 192    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 193       return 4.0f;
 194    default:
 195       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 196       return 0.0f;
 197    }
 198 }
 199
 200 static void
 201 nvc0_screen_destroy(struct pipe_screen *pscreen)
 202 {
 203    struct nvc0_screen *screen = nvc0_screen(pscreen);
 204
 205    nouveau_fence_wait(screen->base.fence.current);
 206    nouveau_fence_ref(NULL, &screen->base.fence.current);
 207
 208    nouveau_bo_ref(NULL, &screen->text);
 209    nouveau_bo_ref(NULL, &screen->tls);
 210    nouveau_bo_ref(NULL, &screen->txc);
 211    nouveau_bo_ref(NULL, &screen->fence.bo);
 212    nouveau_bo_ref(NULL, &screen->vfetch_cache);
 213
 214    nouveau_resource_destroy(&screen->text_heap);
 215
 216    if (screen->tic.entries)
 217       FREE(screen->tic.entries);
 218
 219    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 220
 221    nouveau_grobj_free(&screen->fermi);
 222    nouveau_grobj_free(&screen->eng2d);
 223    nouveau_grobj_free(&screen->m2mf);
 224
 225    nouveau_screen_fini(&screen->base);
 226
 227    FREE(screen);
 228 }
 229
 230 static int
 231 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 232                      unsigned size, const uint32_t *data)
 233 {
 234    struct nouveau_channel *chan = screen->base.channel;
 235
 236    size /= 4;
 237
 238    BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
 239    OUT_RING  (chan, (m - 0x3800) / 8);
 240    OUT_RING  (chan, pos);
 241    BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 242    OUT_RING  (chan, pos);
 243    OUT_RINGp (chan, data, size);
 244
 245    return pos + size;
 246 }
 247
 248 static void
 249 nvc0_magic_3d_init(struct nouveau_channel *chan)
 250 {
 251    BEGIN_RING(chan, RING_3D_(0x10cc), 1);
 252    OUT_RING  (chan, 0xff);
 253    BEGIN_RING(chan, RING_3D_(0x10e0), 2);
 254    OUT_RING(chan, 0xff);
 255    OUT_RING(chan, 0xff);
 256    BEGIN_RING(chan, RING_3D_(0x10ec), 2);
 257    OUT_RING(chan, 0xff);
 258    OUT_RING(chan, 0xff);
 259    BEGIN_RING(chan, RING_3D_(0x074c), 1);
 260    OUT_RING  (chan, 0x3f);
 261
 262    BEGIN_RING(chan, RING_3D_(0x16a8), 1);
 263    OUT_RING  (chan, (3 << 16) | 3);
 264    BEGIN_RING(chan, RING_3D_(0x1794), 1);
 265    OUT_RING  (chan, (2 << 16) | 2);
 266    BEGIN_RING(chan, RING_3D_(0x0de8), 1);
 267    OUT_RING  (chan, 1);
 268
 269 #if 0 /* software method */
 270    BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
 271    OUT_RING  (chan, 0);
 272 #endif
 273
 274    BEGIN_RING(chan, RING_3D_(0x12ac), 1);
 275    OUT_RING  (chan, 0);
 276    BEGIN_RING(chan, RING_3D_(0x0218), 1);
 277    OUT_RING  (chan, 0x10);
 278    BEGIN_RING(chan, RING_3D_(0x10fc), 1);
 279    OUT_RING  (chan, 0x10);
 280    BEGIN_RING(chan, RING_3D_(0x1290), 1);
 281    OUT_RING  (chan, 0x10);
 282    BEGIN_RING(chan, RING_3D_(0x12d8), 2);
 283    OUT_RING  (chan, 0x10);
 284    OUT_RING  (chan, 0x10);
 285    BEGIN_RING(chan, RING_3D_(0x06d4), 1);
 286    OUT_RING  (chan, 8);
 287    BEGIN_RING(chan, RING_3D_(0x1140), 1);
 288    OUT_RING  (chan, 0x10);
 289    BEGIN_RING(chan, RING_3D_(0x1610), 1);
 290    OUT_RING  (chan, 0xe);
 291
 292    BEGIN_RING(chan, RING_3D_(0x164c), 1);
 293    OUT_RING  (chan, 1 << 12);
 294    BEGIN_RING(chan, RING_3D_(0x151c), 1);
 295    OUT_RING  (chan, 1);
 296    BEGIN_RING(chan, RING_3D_(0x020c), 1);
 297    OUT_RING  (chan, 1);
 298    BEGIN_RING(chan, RING_3D_(0x030c), 1);
 299    OUT_RING  (chan, 0);
 300    BEGIN_RING(chan, RING_3D_(0x0300), 1);
 301    OUT_RING  (chan, 3);
 302 #if 0 /* software method */
 303    BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
 304    OUT_RING  (chan, 0);
 305 #endif
 306    BEGIN_RING(chan, RING_3D_(0x02d0), 1);
 307    OUT_RING  (chan, 0x1f40);
 308    BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
 309    OUT_RING  (chan, 1);
 310    BEGIN_RING(chan, RING_3D_(0x19c0), 1);
 311    OUT_RING  (chan, 1);
 312    BEGIN_RING(chan, RING_3D_(0x075c), 1);
 313    OUT_RING  (chan, 3);
 314
 315    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 316    OUT_RING  (chan, 0);
 317    BEGIN_RING(chan, RING_3D_(0x0f90), 1);
 318    OUT_RING  (chan, 0);
 319 }
 320
 321 static void
 322 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 323 {
 324    struct nvc0_screen *screen = nvc0_screen(pscreen);
 325    struct nouveau_channel *chan = screen->base.channel;
 326
 327    MARK_RING (chan, 5, 2);
 328    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 329    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 330    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 331    OUT_RING  (chan, sequence);
 332    OUT_RING  (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 333               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 334 }
 335
 336 static u32
 337 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 338 {
 339    struct nvc0_screen *screen = nvc0_screen(pscreen);
 340    return screen->fence.map[0];
 341 }
 342
 343 #define FAIL_SCREEN_INIT(str, err)                    \
 344    do {                                               \
 345       NOUVEAU_ERR(str, err);                          \
 346       nvc0_screen_destroy(pscreen);                   \
 347       return NULL;                                    \
 348    } while(0)
 349
 350 struct pipe_screen *
 351 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 352 {
 353    struct nvc0_screen *screen;
 354    struct nouveau_channel *chan;
 355    struct pipe_screen *pscreen;
 356    int ret;
 357    unsigned i;
 358
 359    screen = CALLOC_STRUCT(nvc0_screen);
 360    if (!screen)
 361       return NULL;
 362    pscreen = &screen->base.base;
 363
 364    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 365
 366    ret = nouveau_screen_init(&screen->base, dev);
 367    if (ret) {
 368       nvc0_screen_destroy(pscreen);
 369       return NULL;
 370    }
 371    chan = screen->base.channel;
 372
 373    pscreen->winsys = ws;
 374    pscreen->destroy = nvc0_screen_destroy;
 375    pscreen->context_create = nvc0_create;
 376    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 377    pscreen->get_param = nvc0_screen_get_param;
 378    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 379    pscreen->get_paramf = nvc0_screen_get_paramf;
 380
 381    nvc0_screen_init_resource_functions(pscreen);
 382
 383    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 384                         &screen->fence.bo);
 385    if (ret)
 386       goto fail;
 387    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 388    screen->fence.map = screen->fence.bo->map;
 389    nouveau_bo_unmap(screen->fence.bo);
 390    screen->base.fence.emit = nvc0_screen_fence_emit;
 391    screen->base.fence.update = nvc0_screen_fence_update;
 392
 393    for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
 394       ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
 395                            &screen->scratch.bo[i]);
 396       if (ret)
 397          goto fail;
 398    }
 399
 400    ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
 401    if (ret)
 402       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 403
 404    BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
 405    BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
 406    OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 407    OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 408    OUT_RING  (chan, 0);
 409
 410    ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
 411    if (ret)
 412       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 413
 414    BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
 415    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 416    OUT_RING  (chan, NVC0_2D_OPERATION_SRCCOPY);
 417    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 418    OUT_RING  (chan, 0);
 419    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 420    OUT_RING  (chan, 0);
 421    BEGIN_RING(chan, RING_2D_(0x0884), 1);
 422    OUT_RING  (chan, 0x3f);
 423    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 424    OUT_RING  (chan, 1);
 425
 426    ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
 427    if (ret)
 428       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 429
 430    BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
 431    BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
 432    OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 433    OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 434    OUT_RING  (chan, 0);
 435
 436    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 437    OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
 438
 439    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 440    OUT_RING  (chan, 1);
 441
 442    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 443    OUT_RING  (chan, 0);
 444    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 445    OUT_RING  (chan, 0);
 446    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 447    OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
 448    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 449    OUT_RING  (chan, 0);
 450
 451    nvc0_magic_3d_init(chan);
 452
 453    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
 454    if (ret)
 455       goto fail;
 456
 457    nouveau_resource_init(&screen->text_heap, 0, 1 << 20);
 458
 459    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
 460                         &screen->uniforms);
 461    if (ret)
 462       goto fail;
 463
 464    /* auxiliary constants (6 user clip planes, base instance id) */
 465    BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 466    OUT_RING  (chan, 256);
 467    OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 468    OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 469    for (i = 0; i < 5; ++i) {
 470       BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
 471       OUT_RING  (chan, (15 << 4) | 1);
 472    }
 473
 474    screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
 475    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 476                         screen->tls_size, &screen->tls);
 477    if (ret)
 478       goto fail;
 479
 480    BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
 481    OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 482    OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 483    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
 484    OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 485    OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 486    OUT_RING  (chan, screen->tls_size >> 32);
 487    OUT_RING  (chan, screen->tls_size);
 488    BEGIN_RING(chan, RING_3D_(0x07a0), 1);
 489    OUT_RING  (chan, 0);
 490    BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
 491    OUT_RING  (chan, 0);
 492
 493    for (i = 0; i < 5; ++i) {
 494       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 495       OUT_RING  (chan, 0x54);
 496    }
 497    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 498    OUT_RING  (chan, 0);
 499
 500    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
 501                         &screen->vfetch_cache);
 502    if (ret)
 503       goto fail;
 504
 505    BEGIN_RING(chan, RING_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 506    OUT_RELOCh(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 507    OUT_RELOCl(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 508    OUT_RING  (chan, 3);
 509
 510    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
 511    if (ret)
 512       goto fail;
 513
 514    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 515    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 516    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 517    OUT_RING  (chan, NVC0_TIC_MAX_ENTRIES - 1);
 518
 519    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 520    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 521    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 522    OUT_RING  (chan, NVC0_TSC_MAX_ENTRIES - 1);
 523
 524    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 525    OUT_RING  (chan, 0);
 526    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 527    OUT_RING  (chan, 0);
 528    OUT_RING  (chan, 0);
 529    BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
 530    OUT_RING  (chan, 0x3f);
 531
 532    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 533    OUT_RING  (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 534    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 535    for (i = 0; i < 8 * 2; ++i)
 536       OUT_RING(chan, 0);
 537    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 538    OUT_RING  (chan, 0);
 539    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 540    OUT_RING  (chan, 0);
 541
 542    /* neither scissors, viewport nor stencil mask should affect clears */
 543    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 544    OUT_RING  (chan, 0);
 545
 546    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 547    OUT_RING  (chan, 1);
 548    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 549    OUT_RINGf (chan, 0.0f);
 550    OUT_RINGf (chan, 1.0f);
 551    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 552    OUT_RING  (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 553
 554    /* We use scissors instead of exact view volume clipping,
 555     * so they're always enabled.
 556     */
 557    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 558    OUT_RING  (chan, 1);
 559    OUT_RING  (chan, 8192 << 16);
 560    OUT_RING  (chan, 8192 << 16);
 561
 562    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 563    OUT_RING  (chan, 0);
 564    BEGIN_RING(chan, RING_3D_(0x3484), 1);
 565    OUT_RING  (chan, 0);
 566    BEGIN_RING(chan, RING_3D_(0x0dbc), 1);
 567    OUT_RING  (chan, 0x00010000);
 568    BEGIN_RING(chan, RING_3D_(0x0dd8), 1);
 569    OUT_RING  (chan, 0xff800006);
 570    BEGIN_RING(chan, RING_3D_(0x3488), 1);
 571    OUT_RING  (chan, 0);
 572
 573 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 574
 575    i = 0;
 576    MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
 577    MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 578    MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
 579    MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
 580    MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 581    MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 582    MK_MACRO(NVC0_3D_COLOR_MASK_BROADCAST, nvc0_9097_color_mask_brdc);
 583
 584    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 585    OUT_RING  (chan, 1);
 586    BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
 587    OUT_RING  (chan, 0x40);
 588    BEGIN_RING(chan, RING_3D(LAYER), 1);
 589    OUT_RING  (chan, 0);
 590    BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
 591    OUT_RING  (chan, 0x30);
 592    BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
 593    OUT_RING  (chan, 3);
 594    BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
 595    OUT_RING  (chan, 0x20);
 596    BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
 597    OUT_RING  (chan, 0x00);
 598
 599    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 600    OUT_RING  (chan, 0);
 601    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 602    OUT_RING  (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
 603
 604    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 605    OUT_RING  (chan, 1);
 606
 607    BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 608    OUT_RING  (chan, 0xab);
 609    OUT_RING  (chan, 0x00000000);
 610
 611    FIRE_RING (chan);
 612
 613    screen->tic.entries = CALLOC(4096, sizeof(void *));
 614    screen->tsc.entries = screen->tic.entries + 2048;
 615
 616    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 617
 618    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 619
 620    return pscreen;
 621
 622 fail:
 623    nvc0_screen_destroy(pscreen);
 624    return NULL;
 625 }
 626
 627 void
 628 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
 629 {
 630    struct nouveau_channel *chan = screen->base.channel;
 631
 632    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 633
 634    MARK_RING(chan, 5, 5);
 635    nouveau_bo_validate(chan, screen->text, flags);
 636    nouveau_bo_validate(chan, screen->uniforms, flags);
 637    nouveau_bo_validate(chan, screen->txc, flags);
 638    nouveau_bo_validate(chan, screen->vfetch_cache, flags);
 639
 640    if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
 641       nouveau_bo_validate(chan, screen->tls, flags);
 642 }
 643
 644 int
 645 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 646 {
 647    int i = screen->tic.next;
 648
 649    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 650       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 651
 652    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 653
 654    if (screen->tic.entries[i])
 655       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 656
 657    screen->tic.entries[i] = entry;
 658    return i;
 659 }
 660
 661 int
 662 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 663 {
 664    int i = screen->tsc.next;
 665
 666    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 667       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 668
 669    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 670
 671    if (screen->tsc.entries[i])
 672       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 673
 674    screen->tsc.entries[i] = entry;
 675    return i;
 676 }