src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nvc0_fence.h"
  27 #include "nvc0_context.h"
  28 #include "nvc0_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31 #include "nvc0_graph_macros.h"
  32
  33 static boolean
  34 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  35                                 enum pipe_format format,
  36                                 enum pipe_texture_target target,
  37                                 unsigned sample_count,
  38                                 unsigned bindings, unsigned geom_flags)
  39 {
  40    if (sample_count > 1)
  41       return FALSE;
  42
  43    if (!util_format_s3tc_enabled) {
  44       switch (format) {
  45       case PIPE_FORMAT_DXT1_RGB:
  46       case PIPE_FORMAT_DXT1_RGBA:
  47       case PIPE_FORMAT_DXT3_RGBA:
  48       case PIPE_FORMAT_DXT5_RGBA:
  49          return FALSE;
  50       default:
  51          break;
  52       }
  53    }
  54
  55    /* transfers & shared are always supported */
  56    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  57                  PIPE_BIND_TRANSFER_WRITE |
  58                  PIPE_BIND_SHARED);
  59
  60    return (nvc0_format_table[format].usage & bindings) == bindings;
  61 }
  62
  63 static int
  64 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  65 {
  66    switch (param) {
  67    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  68    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  69       return 32;
  70    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  71       return 64;
  72    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  73       return 13;
  74    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  75       return 10;
  76    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  77       return 13;
  78    case PIPE_CAP_ARRAY_TEXTURES:
  79       return 1;
  80    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  81    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  82    case PIPE_CAP_TEXTURE_SWIZZLE:
  83    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  84    case PIPE_CAP_NPOT_TEXTURES:
  85    case PIPE_CAP_ANISOTROPIC_FILTER:
  86       return 1;
  87    case PIPE_CAP_TWO_SIDED_STENCIL:
  88    case PIPE_CAP_DEPTH_CLAMP:
  89    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  90    case PIPE_CAP_POINT_SPRITE:
  91       return 1;
  92    case PIPE_CAP_GLSL:
  93    case PIPE_CAP_SM3:
  94       return 1;
  95    case PIPE_CAP_MAX_RENDER_TARGETS:
  96       return 8;
  97    case PIPE_CAP_TIMER_QUERY:
  98    case PIPE_CAP_OCCLUSION_QUERY:
  99       return 1;
 100    case PIPE_CAP_STREAM_OUTPUT:
 101       return 0;
 102    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 103    case PIPE_CAP_INDEP_BLEND_ENABLE:
 104    case PIPE_CAP_INDEP_BLEND_FUNC:
 105       return 1;
 106    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 107    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 108       return 1;
 109    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 110    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 111       return 0;
 112    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 113       return 0;
 114    case PIPE_CAP_PRIMITIVE_RESTART:
 115    case PIPE_CAP_INSTANCED_DRAWING:
 116       return 1;
 117    default:
 118       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 119       return 0;
 120    }
 121 }
 122
 123 static int
 124 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 125                              enum pipe_shader_cap param)
 126 {
 127    switch (shader) {
 128    case PIPE_SHADER_VERTEX:
 129       /*
 130    case PIPE_SHADER_TESSELLATION_CONTROL:
 131    case PIPE_SHADER_TESSELLATION_EVALUATION:
 132       */
 133    case PIPE_SHADER_GEOMETRY:
 134    case PIPE_SHADER_FRAGMENT:
 135       break;
 136    default:
 137       return 0;
 138    }
 139
 140    switch (param) {
 141    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 142    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 143    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 144    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 145       return 16384;
 146    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 147       return 4;
 148    case PIPE_SHADER_CAP_MAX_INPUTS:
 149       if (shader == PIPE_SHADER_VERTEX)
 150          return 32;
 151       return 0x300 / 16;
 152    case PIPE_SHADER_CAP_MAX_CONSTS:
 153       return 65536 / 16;
 154    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 155       return 14;
 156    case PIPE_SHADER_CAP_MAX_ADDRS:
 157       return 1;
 158    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 159    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 160       return shader != PIPE_SHADER_FRAGMENT;
 161    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 162    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 163       return 1;
 164    case PIPE_SHADER_CAP_MAX_PREDS:
 165       return 0;
 166    case PIPE_SHADER_CAP_MAX_TEMPS:
 167       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 168    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 169       return 1;
 170    case PIPE_SHADER_CAP_SUBROUTINES:
 171       return 0; /* please inline, or provide function declarations */
 172    default:
 173       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 174       return 0;
 175    }
 176 }
 177
 178 static float
 179 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 180 {
 181    switch (param) {
 182    case PIPE_CAP_MAX_LINE_WIDTH:
 183    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 184       return 10.0f;
 185    case PIPE_CAP_MAX_POINT_WIDTH:
 186    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 187       return 64.0f;
 188    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 189       return 16.0f;
 190    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 191       return 4.0f;
 192    default:
 193       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 194       return 0.0f;
 195    }
 196 }
 197
 198 static void
 199 nvc0_screen_destroy(struct pipe_screen *pscreen)
 200 {
 201    struct nvc0_screen *screen = nvc0_screen(pscreen);
 202
 203    nvc0_fence_wait(screen->fence.current);
 204    nvc0_fence_reference(&screen->fence.current, NULL);
 205
 206    nouveau_bo_ref(NULL, &screen->text);
 207    nouveau_bo_ref(NULL, &screen->tls);
 208    nouveau_bo_ref(NULL, &screen->txc);
 209    nouveau_bo_ref(NULL, &screen->fence.bo);
 210    nouveau_bo_ref(NULL, &screen->mp_stack_bo);
 211
 212    nouveau_resource_destroy(&screen->text_heap);
 213
 214    if (screen->tic.entries)
 215       FREE(screen->tic.entries);
 216
 217    nvc0_mm_destroy(screen->mm_GART);
 218    nvc0_mm_destroy(screen->mm_VRAM);
 219    nvc0_mm_destroy(screen->mm_VRAM_fe0);
 220
 221    nouveau_grobj_free(&screen->fermi);
 222    nouveau_grobj_free(&screen->eng2d);
 223    nouveau_grobj_free(&screen->m2mf);
 224
 225    nouveau_screen_fini(&screen->base);
 226
 227    FREE(screen);
 228 }
 229
 230 static int
 231 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 232                      unsigned size, const uint32_t *data)
 233 {
 234    struct nouveau_channel *chan = screen->base.channel;
 235
 236    size /= 4;
 237
 238    BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
 239    OUT_RING  (chan, (m - 0x3800) / 8);
 240    OUT_RING  (chan, pos);
 241    BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 242    OUT_RING  (chan, pos);
 243    OUT_RINGp (chan, data, size);
 244
 245    return pos + size;
 246 }
 247
 248 static void
 249 nvc0_screen_fence_reference(struct pipe_screen *pscreen,
 250                             struct pipe_fence_handle **ptr,
 251                             struct pipe_fence_handle *fence)
 252 {
 253    nvc0_fence_reference((struct nvc0_fence **)ptr, nvc0_fence(fence));
 254 }
 255
 256 static int
 257 nvc0_screen_fence_signalled(struct pipe_screen *pscreen,
 258                             struct pipe_fence_handle *fence,
 259                             unsigned flags)
 260 {
 261    return !(nvc0_fence_signalled(nvc0_fence(fence)));
 262 }
 263
 264 static int
 265 nvc0_screen_fence_finish(struct pipe_screen *pscreen,
 266                          struct pipe_fence_handle *fence,
 267                          unsigned flags)
 268 {
 269    return nvc0_fence_wait((struct nvc0_fence *)fence) != TRUE;
 270 }
 271
 272 static void
 273 nvc0_magic_3d_init(struct nouveau_channel *chan)
 274 {
 275    BEGIN_RING(chan, RING_3D_(0x10cc), 1);
 276    OUT_RING  (chan, 0xff);
 277    BEGIN_RING(chan, RING_3D_(0x10e0), 2);
 278    OUT_RING(chan, 0xff);
 279    OUT_RING(chan, 0xff);
 280    BEGIN_RING(chan, RING_3D_(0x10ec), 2);
 281    OUT_RING(chan, 0xff);
 282    OUT_RING(chan, 0xff);
 283    BEGIN_RING(chan, RING_3D_(0x074c), 1);
 284    OUT_RING  (chan, 0x3f);
 285
 286    BEGIN_RING(chan, RING_3D_(0x16a8), 1);
 287    OUT_RING  (chan, (3 << 16) | 3);
 288    BEGIN_RING(chan, RING_3D_(0x1794), 1);
 289    OUT_RING  (chan, (2 << 16) | 2);
 290    BEGIN_RING(chan, RING_3D_(0x0de8), 1);
 291    OUT_RING  (chan, 1);
 292
 293 #if 0 /* software method */
 294    BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
 295    OUT_RING  (chan, 0);
 296 #endif
 297
 298    BEGIN_RING(chan, RING_3D_(0x12ac), 1);
 299    OUT_RING  (chan, 0);
 300    BEGIN_RING(chan, RING_3D_(0x0218), 1);
 301    OUT_RING  (chan, 0x10);
 302    BEGIN_RING(chan, RING_3D_(0x10fc), 1);
 303    OUT_RING  (chan, 0x10);
 304    BEGIN_RING(chan, RING_3D_(0x1290), 1);
 305    OUT_RING  (chan, 0x10);
 306    BEGIN_RING(chan, RING_3D_(0x12d8), 2);
 307    OUT_RING  (chan, 0x10);
 308    OUT_RING  (chan, 0x10);
 309    BEGIN_RING(chan, RING_3D_(0x06d4), 1);
 310    OUT_RING  (chan, 8);
 311    BEGIN_RING(chan, RING_3D_(0x1140), 1);
 312    OUT_RING  (chan, 0x10);
 313    BEGIN_RING(chan, RING_3D_(0x1610), 1);
 314    OUT_RING  (chan, 0xe);
 315
 316    BEGIN_RING(chan, RING_3D_(0x164c), 1);
 317    OUT_RING  (chan, 1 << 12);
 318    BEGIN_RING(chan, RING_3D_(0x151c), 1);
 319    OUT_RING  (chan, 1);
 320    BEGIN_RING(chan, RING_3D_(0x020c), 1);
 321    OUT_RING  (chan, 1);
 322    BEGIN_RING(chan, RING_3D_(0x030c), 1);
 323    OUT_RING  (chan, 0);
 324    BEGIN_RING(chan, RING_3D_(0x0300), 1);
 325    OUT_RING  (chan, 3);
 326 #if 0 /* software method */
 327    BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
 328    OUT_RING  (chan, 0);
 329 #endif
 330    BEGIN_RING(chan, RING_3D_(0x02d0), 1);
 331    OUT_RING  (chan, 0x1f40);
 332    BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
 333    OUT_RING  (chan, 1);
 334    BEGIN_RING(chan, RING_3D_(0x19c0), 1);
 335    OUT_RING  (chan, 1);
 336    BEGIN_RING(chan, RING_3D_(0x075c), 1);
 337    OUT_RING  (chan, 3);
 338
 339    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 340    OUT_RING  (chan, 0);
 341    BEGIN_RING(chan, RING_3D_(0x0f90), 1);
 342    OUT_RING  (chan, 0);
 343 }
 344
 345 #define FAIL_SCREEN_INIT(str, err)                    \
 346    do {                                               \
 347       NOUVEAU_ERR(str, err);                          \
 348       nvc0_screen_destroy(pscreen);                   \
 349       return NULL;                                    \
 350    } while(0)
 351
 352 struct pipe_screen *
 353 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 354 {
 355    struct nvc0_screen *screen;
 356    struct nouveau_channel *chan;
 357    struct pipe_screen *pscreen;
 358    int ret;
 359    unsigned i;
 360
 361    screen = CALLOC_STRUCT(nvc0_screen);
 362    if (!screen)
 363       return NULL;
 364    pscreen = &screen->base.base;
 365
 366    ret = nouveau_screen_init(&screen->base, dev);
 367    if (ret) {
 368       nvc0_screen_destroy(pscreen);
 369       return NULL;
 370    }
 371    chan = screen->base.channel;
 372
 373    pscreen->winsys = ws;
 374    pscreen->destroy = nvc0_screen_destroy;
 375    pscreen->context_create = nvc0_create;
 376    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 377    pscreen->get_param = nvc0_screen_get_param;
 378    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 379    pscreen->get_paramf = nvc0_screen_get_paramf;
 380    pscreen->fence_reference = nvc0_screen_fence_reference;
 381    pscreen->fence_signalled = nvc0_screen_fence_signalled;
 382    pscreen->fence_finish = nvc0_screen_fence_finish;
 383
 384    nvc0_screen_init_resource_functions(pscreen);
 385
 386    screen->base.vertex_buffer_flags = NOUVEAU_BO_GART;
 387    screen->base.index_buffer_flags = 0;
 388
 389    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 390                         &screen->fence.bo);
 391    if (ret)
 392       goto fail;
 393    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 394    screen->fence.map = screen->fence.bo->map;
 395    nouveau_bo_unmap(screen->fence.bo);
 396
 397    for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
 398       ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
 399                            &screen->scratch.bo[i]);
 400       if (ret)
 401          goto fail;
 402    }
 403
 404    ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
 405    if (ret)
 406       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 407
 408    BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
 409    BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
 410    OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 411    OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 412    OUT_RING  (chan, 0);
 413
 414    ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
 415    if (ret)
 416       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 417
 418    BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
 419    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 420    OUT_RING  (chan, NVC0_2D_OPERATION_SRCCOPY);
 421    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 422    OUT_RING  (chan, 0);
 423    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 424    OUT_RING  (chan, 0);
 425    BEGIN_RING(chan, RING_2D_(0x0884), 1);
 426    OUT_RING  (chan, 0x3f);
 427    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 428    OUT_RING  (chan, 1);
 429
 430    ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
 431    if (ret)
 432       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 433
 434    BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
 435    BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
 436    OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 437    OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 438    OUT_RING  (chan, 0);
 439
 440    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 441    OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
 442
 443    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 444    OUT_RING  (chan, 1);
 445
 446    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 447    OUT_RING  (chan, 0);
 448    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 449    OUT_RING  (chan, 0);
 450    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 451    OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
 452    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 453    OUT_RING  (chan, 0);
 454
 455    nvc0_magic_3d_init(chan);
 456
 457    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
 458    if (ret)
 459       goto fail;
 460
 461    nouveau_resource_init(&screen->text_heap, 0, 1 << 20);
 462
 463    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
 464                         &screen->uniforms);
 465    if (ret)
 466       goto fail;
 467
 468    /* auxiliary constants (6 user clip planes, base instance id) */
 469    BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 470    OUT_RING  (chan, 256);
 471    OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 472    OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 473    for (i = 0; i < 5; ++i) {
 474       BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
 475       OUT_RING  (chan, (15 << 4) | 1);
 476    }
 477
 478    screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
 479    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 480                         screen->tls_size, &screen->tls);
 481    if (ret)
 482       goto fail;
 483
 484    BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
 485    OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 486    OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 487    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
 488    OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 489    OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 490    OUT_RING  (chan, screen->tls_size >> 32);
 491    OUT_RING  (chan, screen->tls_size);
 492    BEGIN_RING(chan, RING_3D_(0x07a0), 1);
 493    OUT_RING  (chan, 0);
 494    BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
 495    OUT_RING  (chan, 0);
 496
 497    for (i = 0; i < 5; ++i) {
 498       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 499       OUT_RING  (chan, 0x54);
 500    }
 501    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 502    OUT_RING  (chan, 0);
 503
 504    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
 505                         &screen->mp_stack_bo);
 506    if (ret)
 507       goto fail;
 508
 509    BEGIN_RING(chan, RING_3D_(0x17bc), 3);
 510    OUT_RELOCh(chan, screen->mp_stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 511    OUT_RELOCl(chan, screen->mp_stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 512    OUT_RING  (chan, 1);
 513
 514    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
 515    if (ret)
 516       goto fail;
 517
 518    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 519    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 520    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 521    OUT_RING  (chan, NVC0_TIC_MAX_ENTRIES - 1);
 522
 523    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 524    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 525    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 526    OUT_RING  (chan, NVC0_TSC_MAX_ENTRIES - 1);
 527
 528    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 529    OUT_RING  (chan, 0);
 530    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 531    OUT_RING  (chan, 0);
 532    OUT_RING  (chan, 0);
 533    BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
 534    OUT_RING  (chan, 0x3f);
 535
 536    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 537    OUT_RING  (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 538    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 539    for (i = 0; i < 8 * 2; ++i)
 540       OUT_RING(chan, 0);
 541    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 542    OUT_RING  (chan, 0);
 543    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 544    OUT_RING  (chan, 0);
 545
 546    /* neither scissors, viewport nor stencil mask should affect clears */
 547    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 548    OUT_RING  (chan, 0);
 549
 550    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 551    OUT_RING  (chan, 1);
 552    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 553    OUT_RINGf (chan, 0.0f);
 554    OUT_RINGf (chan, 1.0f);
 555    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 556    OUT_RING  (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 557
 558    /* We use scissors instead of exact view volume clipping,
 559     * so they're always enabled.
 560     */
 561    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 562    OUT_RING  (chan, 1);
 563    OUT_RING  (chan, 8192 << 16);
 564    OUT_RING  (chan, 8192 << 16);
 565
 566    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 567    OUT_RING  (chan, 0);
 568    BEGIN_RING(chan, RING_3D_(0x3484), 1);
 569    OUT_RING  (chan, 0);
 570    BEGIN_RING(chan, RING_3D_(0x0dbc), 1);
 571    OUT_RING  (chan, 0x00010000);
 572    BEGIN_RING(chan, RING_3D_(0x0dd8), 1);
 573    OUT_RING  (chan, 0xff800006);
 574    BEGIN_RING(chan, RING_3D_(0x3488), 1);
 575    OUT_RING  (chan, 0);
 576
 577 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 578
 579    i = 0;
 580    MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
 581    MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 582    MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
 583    MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
 584    MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 585    MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 586    MK_MACRO(NVC0_3D_COLOR_MASK_BROADCAST, nvc0_9097_color_mask_brdc);
 587
 588    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 589    OUT_RING  (chan, 1);
 590    BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
 591    OUT_RING  (chan, 0x40);
 592    BEGIN_RING(chan, RING_3D(GP_BUILTIN_RESULT_EN), 1);
 593    OUT_RING  (chan, 0);
 594    BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
 595    OUT_RING  (chan, 0x30);
 596    BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
 597    OUT_RING  (chan, 3);
 598    BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
 599    OUT_RING  (chan, 0x20);
 600    BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
 601    OUT_RING  (chan, 0x00);
 602
 603    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 604    OUT_RING  (chan, 0);
 605    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 606    OUT_RING  (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
 607
 608    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 609    OUT_RING  (chan, 0x11111111);
 610    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 611    OUT_RING  (chan, 1);
 612
 613    BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 614    OUT_RING  (chan, 0xab);
 615    OUT_RING  (chan, 0x00000000);
 616
 617    FIRE_RING (chan);
 618
 619    screen->tic.entries = CALLOC(4096, sizeof(void *));
 620    screen->tsc.entries = screen->tic.entries + 2048;
 621
 622    screen->mm_GART = nvc0_mm_create(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 623                                     0x000);
 624    screen->mm_VRAM = nvc0_mm_create(dev, NOUVEAU_BO_VRAM, 0x000);
 625    screen->mm_VRAM_fe0 = nvc0_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 626
 627    nvc0_screen_fence_new(screen, &screen->fence.current, FALSE);
 628
 629    return pscreen;
 630
 631 fail:
 632    nvc0_screen_destroy(pscreen);
 633    return NULL;
 634 }
 635
 636 void
 637 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
 638 {
 639    struct nouveau_channel *chan = screen->base.channel;
 640
 641    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 642
 643    MARK_RING(chan, 5, 5);
 644    nouveau_bo_validate(chan, screen->text, flags);
 645    nouveau_bo_validate(chan, screen->uniforms, flags);
 646    nouveau_bo_validate(chan, screen->txc, flags);
 647    nouveau_bo_validate(chan, screen->mp_stack_bo, flags);
 648
 649    if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
 650       nouveau_bo_validate(chan, screen->tls, flags);
 651 }
 652
 653 int
 654 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 655 {
 656    int i = screen->tic.next;
 657
 658    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 659       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 660
 661    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 662
 663    if (screen->tic.entries[i])
 664       nvc0_tic_entry(screen->tic.entries[i])->id = -1;
 665
 666    screen->tic.entries[i] = entry;
 667    return i;
 668 }
 669
 670 int
 671 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 672 {
 673    int i = screen->tsc.next;
 674
 675    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 676       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 677
 678    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 679
 680    if (screen->tsc.entries[i])
 681       nvc0_tsc_entry(screen->tsc.entries[i])->id = -1;
 682
 683    screen->tsc.entries[i] = entry;
 684    return i;
 685 }