src/gallium/drivers/nvfx/nv04_surface_2d.c

   1 #include "pipe/p_context.h"
   2 #include "pipe/p_format.h"
   3 #include "util/u_format.h"
   4 #include "util/u_math.h"
   5 #include "util/u_memory.h"
   6
   7 #include "nouveau/nouveau_winsys.h"
   8 #include "nouveau/nouveau_util.h"
   9 #include "nouveau/nouveau_screen.h"
  10 #include "nv04_surface_2d.h"
  11
  12 static INLINE int
  13 nv04_surface_format(enum pipe_format format)
  14 {
  15         switch (format) {
  16         case PIPE_FORMAT_A8_UNORM:
  17         case PIPE_FORMAT_L8_UNORM:
  18         case PIPE_FORMAT_I8_UNORM:
  19                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
  20         case PIPE_FORMAT_R16_SNORM:
  21         case PIPE_FORMAT_B5G6R5_UNORM:
  22         case PIPE_FORMAT_Z16_UNORM:
  23         case PIPE_FORMAT_L8A8_UNORM:
  24                 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
  25         case PIPE_FORMAT_B8G8R8X8_UNORM:
  26         case PIPE_FORMAT_B8G8R8A8_UNORM:
  27                 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
  28         case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  29         case PIPE_FORMAT_X8Z24_UNORM:
  30                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
  31         default:
  32                 return -1;
  33         }
  34 }
  35
  36 static INLINE int
  37 nv04_rect_format(enum pipe_format format)
  38 {
  39         switch (format) {
  40         case PIPE_FORMAT_A8_UNORM:
  41                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  42         case PIPE_FORMAT_B5G6R5_UNORM:
  43         case PIPE_FORMAT_L8A8_UNORM:
  44         case PIPE_FORMAT_Z16_UNORM:
  45                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
  46         case PIPE_FORMAT_B8G8R8X8_UNORM:
  47         case PIPE_FORMAT_B8G8R8A8_UNORM:
  48         case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  49         case PIPE_FORMAT_X8Z24_UNORM:
  50                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  51         default:
  52                 return -1;
  53         }
  54 }
  55
  56 static INLINE int
  57 nv04_scaled_image_format(enum pipe_format format)
  58 {
  59         switch (format) {
  60         case PIPE_FORMAT_A8_UNORM:
  61         case PIPE_FORMAT_L8_UNORM:
  62         case PIPE_FORMAT_I8_UNORM:
  63                 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
  64         case PIPE_FORMAT_B5G5R5A1_UNORM:
  65                 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
  66         case PIPE_FORMAT_B8G8R8A8_UNORM:
  67                 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
  68         case PIPE_FORMAT_B8G8R8X8_UNORM:
  69                 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
  70         case PIPE_FORMAT_B5G6R5_UNORM:
  71         case PIPE_FORMAT_R16_SNORM:
  72         case PIPE_FORMAT_L8A8_UNORM:
  73                 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
  74         default:
  75                 return -1;
  76         }
  77 }
  78
  79 static INLINE unsigned
  80 nv04_swizzle_bits_square(unsigned x, unsigned y)
  81 {
  82         unsigned u = (x & 0x001) << 0 |
  83                      (x & 0x002) << 1 |
  84                      (x & 0x004) << 2 |
  85                      (x & 0x008) << 3 |
  86                      (x & 0x010) << 4 |
  87                      (x & 0x020) << 5 |
  88                      (x & 0x040) << 6 |
  89                      (x & 0x080) << 7 |
  90                      (x & 0x100) << 8 |
  91                      (x & 0x200) << 9 |
  92                      (x & 0x400) << 10 |
  93                      (x & 0x800) << 11;
  94
  95         unsigned v = (y & 0x001) << 1 |
  96                      (y & 0x002) << 2 |
  97                      (y & 0x004) << 3 |
  98                      (y & 0x008) << 4 |
  99                      (y & 0x010) << 5 |
 100                      (y & 0x020) << 6 |
 101                      (y & 0x040) << 7 |
 102                      (y & 0x080) << 8 |
 103                      (y & 0x100) << 9 |
 104                      (y & 0x200) << 10 |
 105                      (y & 0x400) << 11 |
 106                      (y & 0x800) << 12;
 107         return v | u;
 108 }
 109
 110 /* rectangular swizzled textures are linear concatenations of swizzled square tiles */
 111 static INLINE unsigned
 112 nv04_swizzle_bits(unsigned x, unsigned y, unsigned w, unsigned h)
 113 {
 114         unsigned s = MIN2(w, h);
 115         unsigned m = s - 1;
 116         return (((x | y) & ~m) * s) | nv04_swizzle_bits_square(x & m, y & m);
 117 }
 118
 119 static int
 120 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
 121                           struct pipe_surface *dst, int dx, int dy,
 122                           struct pipe_surface *src, int sx, int sy,
 123                           int w, int h)
 124 {
 125         struct nouveau_channel *chan = ctx->swzsurf->channel;
 126         struct nouveau_grobj *swzsurf = ctx->swzsurf;
 127         struct nouveau_grobj *sifm = ctx->sifm;
 128         struct nouveau_bo *src_bo = ctx->buf(src);
 129         struct nouveau_bo *dst_bo = ctx->buf(dst);
 130         const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 131         /* Max width & height may not be the same on all HW, but must be POT */
 132         const unsigned max_w = 1024;
 133         const unsigned max_h = 1024;
 134         unsigned sub_w = w > max_w ? max_w : w;
 135         unsigned sub_h = h > max_h ? max_h : h;
 136         unsigned x;
 137         unsigned y;
 138
 139         /* Swizzled surfaces must be POT  */
 140         assert(util_is_pot(dst->width) && util_is_pot(dst->height));
 141
 142         /* If area is too large to copy in one shot we must copy it in POT chunks to meet alignment requirements */
 143         assert(sub_w == w || util_is_pot(sub_w));
 144         assert(sub_h == h || util_is_pot(sub_h));
 145
 146         MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
 147                          ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
 148
 149         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
 150         OUT_RELOCo(chan, dst_bo,
 151                          NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 152
 153         BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
 154         OUT_RING  (chan, nv04_surface_format(dst->format) |
 155                          log2i(dst->width) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
 156                          log2i(dst->height) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
 157
 158         BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
 159         OUT_RELOCo(chan, src_bo,
 160                          NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 161         BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
 162         OUT_RING  (chan, swzsurf->handle);
 163
 164         for (y = 0; y < h; y += sub_h) {
 165           sub_h = MIN2(sub_h, h - y);
 166
 167           for (x = 0; x < w; x += sub_w) {
 168             sub_w = MIN2(sub_w, w - x);
 169
 170             assert(!(dst->offset & 63));
 171
 172             BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
 173             OUT_RELOCl(chan, dst_bo, dst->offset,
 174                              NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 175
 176             BEGIN_RING(chan, sifm, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
 177             OUT_RING  (chan, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
 178             OUT_RING  (chan, nv04_scaled_image_format(src->format));
 179             OUT_RING  (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
 180             OUT_RING  (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT));
 181             OUT_RING  (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | sub_w);
 182             OUT_RING  (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT));
 183             OUT_RING  (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | sub_w);
 184             OUT_RING  (chan, 1 << 20);
 185             OUT_RING  (chan, 1 << 20);
 186
 187             BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
 188             OUT_RING  (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | sub_w);
 189             OUT_RING  (chan, src_pitch |
 190                              NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
 191                              NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
 192             OUT_RELOCl(chan, src_bo, src->offset + (sy+y) * src_pitch + (sx+x) * util_format_get_blocksize(src->texture->format),
 193                              NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 194             OUT_RING  (chan, 0);
 195           }
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int
 202 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
 203                        struct pipe_surface *dst, int dx, int dy,
 204                        struct pipe_surface *src, int sx, int sy, int w, int h)
 205 {
 206         struct nouveau_channel *chan = ctx->m2mf->channel;
 207         struct nouveau_grobj *m2mf = ctx->m2mf;
 208         struct nouveau_bo *src_bo = ctx->buf(src);
 209         struct nouveau_bo *dst_bo = ctx->buf(dst);
 210         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 211         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 212         unsigned dst_offset = dst->offset + dy * dst_pitch +
 213                               dx * util_format_get_blocksize(dst->texture->format);
 214         unsigned src_offset = src->offset + sy * src_pitch +
 215                               sx * util_format_get_blocksize(src->texture->format);
 216
 217         MARK_RING (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2);
 218         BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
 219         OUT_RELOCo(chan, src_bo,
 220                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 221         OUT_RELOCo(chan, dst_bo,
 222                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 223
 224         while (h) {
 225                 int count = (h > 2047) ? 2047 : h;
 226
 227                 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 228                 OUT_RELOCl(chan, src_bo, src_offset,
 229                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 230                 OUT_RELOCl(chan, dst_bo, dst_offset,
 231                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
 232                 OUT_RING  (chan, src_pitch);
 233                 OUT_RING  (chan, dst_pitch);
 234                 OUT_RING  (chan, w * util_format_get_blocksize(src->texture->format));
 235                 OUT_RING  (chan, count);
 236                 OUT_RING  (chan, 0x0101);
 237                 OUT_RING  (chan, 0);
 238
 239                 h -= count;
 240                 src_offset += src_pitch * count;
 241                 dst_offset += dst_pitch * count;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int
 248 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 249                        int dx, int dy, struct pipe_surface *src, int sx, int sy,
 250                        int w, int h)
 251 {
 252         struct nouveau_channel *chan = ctx->surf2d->channel;
 253         struct nouveau_grobj *surf2d = ctx->surf2d;
 254         struct nouveau_grobj *blit = ctx->blit;
 255         struct nouveau_bo *src_bo = ctx->buf(src);
 256         struct nouveau_bo *dst_bo = ctx->buf(dst);
 257         unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
 258         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 259         int format;
 260
 261         format = nv04_surface_format(dst->format);
 262         if (format < 0)
 263                 return 1;
 264
 265         MARK_RING (chan, 12, 4);
 266         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 267         OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 268         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 269         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 270         OUT_RING  (chan, format);
 271         OUT_RING  (chan, (dst_pitch << 16) | src_pitch);
 272         OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 273         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 274
 275         BEGIN_RING(chan, blit, 0x0300, 3);
 276         OUT_RING  (chan, (sy << 16) | sx);
 277         OUT_RING  (chan, (dy << 16) | dx);
 278         OUT_RING  (chan, ( h << 16) |  w);
 279
 280         return 0;
 281 }
 282
 283 static void
 284 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 285                   int dx, int dy, struct pipe_surface *src, int sx, int sy,
 286                   int w, int h)
 287 {
 288         int src_linear = src->texture->flags & NVFX_RESOURCE_FLAG_LINEAR;
 289         int dst_linear = dst->texture->flags & NVFX_RESOURCE_FLAG_LINEAR;
 290
 291         assert(src->format == dst->format);
 292
 293         /* Setup transfer to swizzle the texture to vram if needed */
 294         if (src_linear && !dst_linear && w > 1 && h > 1) {
 295            nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
 296            return;
 297         }
 298
 299         /* Use M2MF instead of the blitter since it always works
 300          * Any possible performance drop is likely to be not very significant
 301          * and dwarfed anyway by the current buffer management problems
 302          */
 303         nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
 304 }
 305
 306 static void
 307 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
 308                   int dx, int dy, int w, int h, unsigned value)
 309 {
 310         struct nouveau_channel *chan = ctx->surf2d->channel;
 311         struct nouveau_grobj *surf2d = ctx->surf2d;
 312         struct nouveau_grobj *rect = ctx->rect;
 313         struct nouveau_bo *dst_bo = ctx->buf(dst);
 314         unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
 315         int cs2d_format, gdirect_format;
 316
 317         cs2d_format = nv04_surface_format(dst->format);
 318         assert(cs2d_format >= 0);
 319
 320         gdirect_format = nv04_rect_format(dst->format);
 321         assert(gdirect_format >= 0);
 322
 323         MARK_RING (chan, 16, 4);
 324         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 325         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 326         OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 327         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 328         OUT_RING  (chan, cs2d_format);
 329         OUT_RING  (chan, (dst_pitch << 16) | dst_pitch);
 330         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 331         OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 332
 333         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
 334         OUT_RING  (chan, gdirect_format);
 335         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
 336         OUT_RING  (chan, value);
 337         BEGIN_RING(chan, rect,
 338                    NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
 339         OUT_RING  (chan, (dx << 16) | dy);
 340         OUT_RING  (chan, ( w << 16) |  h);
 341 }
 342
 343 void
 344 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
 345 {
 346         struct nv04_surface_2d *ctx;
 347
 348         if (!pctx || !*pctx)
 349                 return;
 350         ctx = *pctx;
 351         *pctx = NULL;
 352
 353         nouveau_notifier_free(&ctx->ntfy);
 354         nouveau_grobj_free(&ctx->m2mf);
 355         nouveau_grobj_free(&ctx->surf2d);
 356         nouveau_grobj_free(&ctx->swzsurf);
 357         nouveau_grobj_free(&ctx->rect);
 358         nouveau_grobj_free(&ctx->blit);
 359         nouveau_grobj_free(&ctx->sifm);
 360
 361         FREE(ctx);
 362 }
 363
 364 struct nv04_surface_2d *
 365 nv04_surface_2d_init(struct nouveau_screen *screen)
 366 {
 367         struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
 368         struct nouveau_channel *chan = screen->channel;
 369         unsigned handle = 0x88000000, class;
 370         int ret;
 371
 372         if (!ctx)
 373                 return NULL;
 374
 375         ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
 376         if (ret) {
 377                 nv04_surface_2d_takedown(&ctx);
 378                 return NULL;
 379         }
 380
 381         ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
 382         if (ret) {
 383                 nv04_surface_2d_takedown(&ctx);
 384                 return NULL;
 385         }
 386
 387         BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
 388         OUT_RING  (chan, ctx->ntfy->handle);
 389
 390         if (chan->device->chipset < 0x10)
 391                 class = NV04_CONTEXT_SURFACES_2D;
 392         else
 393                 class = NV10_CONTEXT_SURFACES_2D;
 394
 395         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
 396         if (ret) {
 397                 nv04_surface_2d_takedown(&ctx);
 398                 return NULL;
 399         }
 400
 401         BEGIN_RING(chan, ctx->surf2d,
 402                          NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 403         OUT_RING  (chan, chan->vram->handle);
 404         OUT_RING  (chan, chan->vram->handle);
 405
 406         if (chan->device->chipset < 0x10)
 407                 class = NV04_IMAGE_BLIT;
 408         else
 409                 class = NV12_IMAGE_BLIT;
 410
 411         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
 412         if (ret) {
 413                 nv04_surface_2d_takedown(&ctx);
 414                 return NULL;
 415         }
 416
 417         BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1);
 418         OUT_RING  (chan, ctx->ntfy->handle);
 419         BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
 420         OUT_RING  (chan, ctx->surf2d->handle);
 421         BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1);
 422         OUT_RING  (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY);
 423
 424         ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
 425                                   &ctx->rect);
 426         if (ret) {
 427                 nv04_surface_2d_takedown(&ctx);
 428                 return NULL;
 429         }
 430
 431         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
 432         OUT_RING  (chan, ctx->ntfy->handle);
 433         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
 434         OUT_RING  (chan, ctx->surf2d->handle);
 435         BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
 436         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
 437         BEGIN_RING(chan, ctx->rect,
 438                          NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
 439         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
 440
 441         switch (chan->device->chipset & 0xf0) {
 442         case 0x00:
 443         case 0x10:
 444                 class = NV04_SWIZZLED_SURFACE;
 445                 break;
 446         case 0x20:
 447                 class = NV20_SWIZZLED_SURFACE;
 448                 break;
 449         case 0x30:
 450                 class = NV30_SWIZZLED_SURFACE;
 451                 break;
 452         case 0x40:
 453         case 0x60:
 454                 class = NV40_SWIZZLED_SURFACE;
 455                 break;
 456         default:
 457                 /* Famous last words: this really can't happen.. */
 458                 assert(0);
 459                 break;
 460         }
 461
 462         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
 463         if (ret) {
 464                 nv04_surface_2d_takedown(&ctx);
 465                 return NULL;
 466         }
 467
 468         switch (chan->device->chipset & 0xf0) {
 469         case 0x10:
 470         case 0x20:
 471                 class = NV10_SCALED_IMAGE_FROM_MEMORY;
 472                 break;
 473         case 0x30:
 474                 class = NV30_SCALED_IMAGE_FROM_MEMORY;
 475                 break;
 476         case 0x40:
 477         case 0x60:
 478                 class = NV40_SCALED_IMAGE_FROM_MEMORY;
 479                 break;
 480         default:
 481                 class = NV04_SCALED_IMAGE_FROM_MEMORY;
 482                 break;
 483         }
 484
 485         ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
 486         if (ret) {
 487                 nv04_surface_2d_takedown(&ctx);
 488                 return NULL;
 489         }
 490
 491         ctx->copy = nv04_surface_copy;
 492         ctx->fill = nv04_surface_fill;
 493         return ctx;
 494 }
 495
 496 struct nv04_surface*
 497 nv04_surface_wrap_for_render(struct pipe_screen *pscreen,
 498                              struct nv04_surface_2d* eng2d, struct nv04_surface* ns)
 499 {
 500         struct pipe_resource templ;
 501         struct pipe_resource* temp_tex;
 502         struct nv04_surface* temp_ns;
 503         int temp_flags;
 504
 505         temp_flags = (ns->base.usage |
 506                       PIPE_BIND_BLIT_SOURCE |
 507                       PIPE_BIND_BLIT_DESTINATION);
 508
 509         ns->base.usage = (PIPE_BIND_BLIT_SOURCE |
 510                          PIPE_BIND_BLIT_DESTINATION);
 511
 512         memset(&templ, 0, sizeof(templ));
 513         templ.format = ns->base.texture->format;
 514         templ.target = PIPE_TEXTURE_2D;
 515         templ.width0 = ns->base.width;
 516         templ.height0 = ns->base.height;
 517         templ.depth0 = 1;
 518         templ.last_level = 0;
 519
 520         // TODO: this is probably wrong and we should specifically handle multisampling somehow once it is implemented
 521         templ.nr_samples = ns->base.texture->nr_samples;
 522
 523         templ.bind = ns->base.texture->bind | PIPE_BIND_RENDER_TARGET;
 524
 525         temp_tex = pscreen->resource_create(pscreen, &templ);
 526         temp_ns = (struct nv04_surface*)pscreen->get_tex_surface(pscreen, temp_tex, 0, 0, 0, temp_flags);
 527         temp_ns->backing = ns;
 528
 529         if(ns->base.usage & PIPE_BIND_BLIT_SOURCE)
 530                 eng2d->copy(eng2d, &temp_ns->backing->base,
 531                             0, 0, &ns->base,
 532                             0, 0, ns->base.width, ns->base.height);
 533
 534         return temp_ns;
 535 }