src/gallium/drivers/nvfx/nv40_vertprog.h

   1 #ifndef __NV40_SHADER_H__
   2 #define __NV40_SHADER_H__
   3
   4 /* Vertex programs instruction set
   5  *
   6  * The NV40 instruction set is very similar to NV30.  Most fields are in
   7  * a slightly different position in the instruction however.
   8  *
   9  * Merged instructions
  10  *     In some cases it is possible to put two instructions into one opcode
  11  *     slot.  The rules for when this is OK is not entirely clear to me yet.
  12  *
  13  *     There are separate writemasks and dest temp register fields for each
  14  *     grouping of instructions.  There is however only one field with the
  15  *     ID of a result register.  Writing to temp/result regs is selected by
  16  *     setting VEC_RESULT/SCA_RESULT.
  17  *
  18  * Temporary registers
  19  *     The source/dest temp register fields have been extended by 1 bit, to
  20  *     give a total of 32 temporary registers.
  21  *
  22  * Relative Addressing
  23  *     NV40 can use an address register to index into vertex attribute regs.
  24  *     This is done by putting the offset value into INPUT_SRC and setting
  25  *     the INDEX_INPUT flag.
  26  *
  27  * Conditional execution (see NV_vertex_program{2,3} for details)
  28  *     There is a second condition code register on NV40, it's use is enabled
  29  *     by setting the COND_REG_SELECT_1 flag.
  30  *
  31  * Texture lookup
  32  *     TODO
  33  */
  34
  35 /* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
  36 #define NV40_VP_INST_VEC_RESULT                                        (1 << 30)
  37 /* uncertain.. */
  38 #define NV40_VP_INST_COND_UPDATE_ENABLE                        ((1 << 14)|1<<29)
  39 /* use address reg as index into attribs */
  40 #define NV40_VP_INST_INDEX_INPUT                                       (1 << 27)
  41 #define NV40_VP_INST_COND_REG_SELECT_1                                 (1 << 25)
  42 #define NV40_VP_INST_ADDR_REG_SELECT_1                                 (1 << 24)
  43 #define NV40_VP_INST_SRC2_ABS                                          (1 << 23)
  44 #define NV40_VP_INST_SRC1_ABS                                          (1 << 22)
  45 #define NV40_VP_INST_SRC0_ABS                                          (1 << 21)
  46 #define NV40_VP_INST_VEC_DEST_TEMP_SHIFT                                      15
  47 #define NV40_VP_INST_VEC_DEST_TEMP_MASK                             (0x1F << 15)
  48 #define NV40_VP_INST_COND_TEST_ENABLE                                  (1 << 13)
  49 #define NV40_VP_INST_COND_SHIFT                                               10
  50 #define NV40_VP_INST_COND_MASK                                       (0x7 << 10)
  51 #define NV40_VP_INST_COND_SWZ_X_SHIFT                                          8
  52 #define NV40_VP_INST_COND_SWZ_X_MASK                                    (3 << 8)
  53 #define NV40_VP_INST_COND_SWZ_Y_SHIFT                                          6
  54 #define NV40_VP_INST_COND_SWZ_Y_MASK                                    (3 << 6)
  55 #define NV40_VP_INST_COND_SWZ_Z_SHIFT                                          4
  56 #define NV40_VP_INST_COND_SWZ_Z_MASK                                    (3 << 4)
  57 #define NV40_VP_INST_COND_SWZ_W_SHIFT                                          2
  58 #define NV40_VP_INST_COND_SWZ_W_MASK                                    (3 << 2)
  59 #define NV40_VP_INST_COND_SWZ_ALL_SHIFT                                        2
  60 #define NV40_VP_INST_COND_SWZ_ALL_MASK                               (0xFF << 2)
  61 #define NV40_VP_INST_ADDR_SWZ_SHIFT                                            0
  62 #define NV40_VP_INST_ADDR_SWZ_MASK                                   (0x03 << 0)
  63 #define NV40_VP_INST0_KNOWN ( \
  64                 NV40_VP_INST_INDEX_INPUT | \
  65                 NV40_VP_INST_COND_REG_SELECT_1 | \
  66                 NV40_VP_INST_ADDR_REG_SELECT_1 | \
  67                 NV40_VP_INST_SRC2_ABS | \
  68                 NV40_VP_INST_SRC1_ABS | \
  69                 NV40_VP_INST_SRC0_ABS | \
  70                 NV40_VP_INST_VEC_DEST_TEMP_MASK | \
  71                 NV40_VP_INST_COND_TEST_ENABLE | \
  72                 NV40_VP_INST_COND_MASK | \
  73                 NV40_VP_INST_COND_SWZ_ALL_MASK | \
  74                 NV40_VP_INST_ADDR_SWZ_MASK)
  75
  76 /* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
  77 #define NV40_VP_INST_VEC_OPCODE_SHIFT                                         22
  78 #define NV40_VP_INST_VEC_OPCODE_MASK                                (0x1F << 22)
  79 #define NV40_VP_INST_SCA_OPCODE_SHIFT                                         27
  80 #define NV40_VP_INST_SCA_OPCODE_MASK                                (0x1F << 27)
  81 #define NV40_VP_INST_CONST_SRC_SHIFT                                          12
  82 #define NV40_VP_INST_CONST_SRC_MASK                                 (0xFF << 12)
  83 #define NV40_VP_INST_INPUT_SRC_SHIFT                                           8
  84 #define NV40_VP_INST_INPUT_SRC_MASK                                  (0x0F << 8)
  85 #define NV40_VP_INST_SRC0H_SHIFT                                               0
  86 #define NV40_VP_INST_SRC0H_MASK                                      (0xFF << 0)
  87 #define NV40_VP_INST1_KNOWN ( \
  88                 NV40_VP_INST_VEC_OPCODE_MASK | \
  89                 NV40_VP_INST_SCA_OPCODE_MASK | \
  90                 NV40_VP_INST_CONST_SRC_MASK  | \
  91                 NV40_VP_INST_INPUT_SRC_MASK  | \
  92                 NV40_VP_INST_SRC0H_MASK \
  93                 )
  94
  95 /* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
  96 #define NV40_VP_INST_SRC0L_SHIFT                                              23
  97 #define NV40_VP_INST_SRC0L_MASK                                    (0x1FF << 23)
  98 #define NV40_VP_INST_SRC1_SHIFT                                                6
  99 #define NV40_VP_INST_SRC1_MASK                                    (0x1FFFF << 6)
 100 #define NV40_VP_INST_SRC2H_SHIFT                                               0
 101 #define NV40_VP_INST_SRC2H_MASK                                      (0x3F << 0)
 102 #define NV40_VP_INST_IADDRH_SHIFT                                              0
 103 #define NV40_VP_INST_IADDRH_MASK                                     (0x1F << 0)
 104
 105 /* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
 106 #define NV40_VP_INST_IADDRL_SHIFT                                             29
 107 #define NV40_VP_INST_IADDRL_MASK                                       (7 << 29)
 108 #define NV40_VP_INST_SRC2L_SHIFT                                              21
 109 #define NV40_VP_INST_SRC2L_MASK                                    (0x7FF << 21)
 110 #define NV40_VP_INST_SCA_WRITEMASK_SHIFT                                      17
 111 #define NV40_VP_INST_SCA_WRITEMASK_MASK                              (0xF << 17)
 112 #    define NV40_VP_INST_SCA_WRITEMASK_X                               (1 << 20)
 113 #    define NV40_VP_INST_SCA_WRITEMASK_Y                               (1 << 19)
 114 #    define NV40_VP_INST_SCA_WRITEMASK_Z                               (1 << 18)
 115 #    define NV40_VP_INST_SCA_WRITEMASK_W                               (1 << 17)
 116 #define NV40_VP_INST_VEC_WRITEMASK_SHIFT                                      13
 117 #define NV40_VP_INST_VEC_WRITEMASK_MASK                              (0xF << 13)
 118 #    define NV40_VP_INST_VEC_WRITEMASK_X                               (1 << 16)
 119 #    define NV40_VP_INST_VEC_WRITEMASK_Y                               (1 << 15)
 120 #    define NV40_VP_INST_VEC_WRITEMASK_Z                               (1 << 14)
 121 #    define NV40_VP_INST_VEC_WRITEMASK_W                               (1 << 13)
 122 #define NV40_VP_INST_SCA_RESULT                                        (1 << 12)
 123 #define NV40_VP_INST_SCA_DEST_TEMP_SHIFT                                       7
 124 #define NV40_VP_INST_SCA_DEST_TEMP_MASK                              (0x1F << 7)
 125 #define NV40_VP_INST_DEST_SHIFT                                                2
 126 #define NV40_VP_INST_DEST_MASK                                         (31 << 2)
 127 #    define NV40_VP_INST_DEST_POS                                              0
 128 #    define NV40_VP_INST_DEST_COL0                                             1
 129 #    define NV40_VP_INST_DEST_COL1                                             2
 130 #    define NV40_VP_INST_DEST_BFC0                                             3
 131 #    define NV40_VP_INST_DEST_BFC1                                             4
 132 #    define NV40_VP_INST_DEST_FOGC                                             5
 133 #    define NV40_VP_INST_DEST_PSZ                                              6
 134 #    define NV40_VP_INST_DEST_TC0                                              7
 135 #    define NV40_VP_INST_DEST_TC(n)                                        (7+n)
 136 #    define NV40_VP_INST_DEST_TEMP                                          0x1F
 137 #define NV40_VP_INST_INDEX_CONST                                        (1 << 1)
 138 #define NV40_VP_INST3_KNOWN ( \
 139                 NV40_VP_INST_SRC2L_MASK |\
 140                 NV40_VP_INST_SCA_WRITEMASK_MASK |\
 141                 NV40_VP_INST_VEC_WRITEMASK_MASK |\
 142                 NV40_VP_INST_SCA_DEST_TEMP_MASK |\
 143                 NV40_VP_INST_DEST_MASK |\
 144                 NV40_VP_INST_INDEX_CONST)
 145
 146 /* Useful to split the source selection regs into their pieces */
 147 #define NV40_VP_SRC0_HIGH_SHIFT                                                9
 148 #define NV40_VP_SRC0_HIGH_MASK                                        0x0001FE00
 149 #define NV40_VP_SRC0_LOW_MASK                                         0x000001FF
 150 #define NV40_VP_SRC2_HIGH_SHIFT                                               11
 151 #define NV40_VP_SRC2_HIGH_MASK                                        0x0001F800
 152 #define NV40_VP_SRC2_LOW_MASK                                         0x000007FF
 153
 154 /* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
 155 #define NV40_VP_SRC_NEGATE                                             (1 << 16)
 156 #define NV40_VP_SRC_SWZ_X_SHIFT                                               14
 157 #define NV40_VP_SRC_SWZ_X_MASK                                         (3 << 14)
 158 #define NV40_VP_SRC_SWZ_Y_SHIFT                                               12
 159 #define NV40_VP_SRC_SWZ_Y_MASK                                         (3 << 12)
 160 #define NV40_VP_SRC_SWZ_Z_SHIFT                                               10
 161 #define NV40_VP_SRC_SWZ_Z_MASK                                         (3 << 10)
 162 #define NV40_VP_SRC_SWZ_W_SHIFT                                                8
 163 #define NV40_VP_SRC_SWZ_W_MASK                                          (3 << 8)
 164 #define NV40_VP_SRC_SWZ_ALL_SHIFT                                              8
 165 #define NV40_VP_SRC_SWZ_ALL_MASK                                     (0xFF << 8)
 166 #define NV40_VP_SRC_TEMP_SRC_SHIFT                                             2
 167 #define NV40_VP_SRC_TEMP_SRC_MASK                                    (0x1F << 2)
 168 #define NV40_VP_SRC_REG_TYPE_SHIFT                                             0
 169 #define NV40_VP_SRC_REG_TYPE_MASK                                       (3 << 0)
 170 #    define NV40_VP_SRC_REG_TYPE_UNK0                                          0
 171 #    define NV40_VP_SRC_REG_TYPE_TEMP                                          1
 172 #    define NV40_VP_SRC_REG_TYPE_INPUT                                         2
 173 #    define NV40_VP_SRC_REG_TYPE_CONST                                         3
 174
 175 #include "nvfx_shader.h"
 176
 177 #endif