src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6 #include "vl/vl_decoder.h"
   7 #include "vl/vl_video_buffer.h"
   8
   9 #include "nouveau/nouveau_screen.h"
  10 #include "nouveau/nv_object.xml.h"
  11 #include "nvfx_context.h"
  12 #include "nvfx_screen.h"
  13 #include "nvfx_resource.h"
  14 #include "nvfx_tex.h"
  15
  16 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  17 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  18 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  19
  20 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  21 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  22 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  23
  24 static int
  25 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  26 {
  27         struct nvfx_screen *screen = nvfx_screen(pscreen);
  28
  29         switch (param) {
  30         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  31                 return 16;
  32         case PIPE_CAP_NPOT_TEXTURES:
  33                 return screen->advertise_npot;
  34         case PIPE_CAP_TWO_SIDED_STENCIL:
  35                 return 1;
  36         case PIPE_CAP_GLSL:
  37                 return 1;
  38         case PIPE_CAP_SM3:
  39                 /* TODO: >= nv4x support Shader Model 3.0 */
  40                 return 0;
  41         case PIPE_CAP_ANISOTROPIC_FILTER:
  42                 return 1;
  43         case PIPE_CAP_POINT_SPRITE:
  44                 return 1;
  45         case PIPE_CAP_MAX_RENDER_TARGETS:
  46                 return screen->use_nv4x ? 4 : 1;
  47         case PIPE_CAP_OCCLUSION_QUERY:
  48                 return 1;
  49         case PIPE_CAP_TIMER_QUERY:
  50                 return 0;
  51         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  52                 return 1;
  53         case PIPE_CAP_TEXTURE_SWIZZLE:
  54                 return 1;
  55         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  56                 return 13;
  57         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  58                 return 10;
  59         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  60                 return 13;
  61         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  62                 return !!screen->use_nv4x;
  63         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  64                 return 1;
  65         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  66                 return 0; /* We have 4 on nv40 - but unsupported currently */
  67         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  68                 return screen->advertise_blend_equation_separate;
  69         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  70                 return 16;
  71         case PIPE_CAP_INDEP_BLEND_ENABLE:
  72                 /* TODO: on nv40 we have separate color masks */
  73                 /* TODO: nv40 mrt blending is probably broken */
  74                 return 0;
  75         case PIPE_CAP_INDEP_BLEND_FUNC:
  76                 return 0;
  77         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  78                 return 0;
  79         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  80         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  81         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  82         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  83                 return 1;
  84         case PIPE_CAP_DEPTH_CLAMP:
  85                 return 0; // TODO: implement depth clamp
  86         case PIPE_CAP_PRIMITIVE_RESTART:
  87                 return 0; // TODO: implement primitive restart
  88         case PIPE_CAP_ARRAY_TEXTURES:
  89         case PIPE_CAP_TGSI_INSTANCEID:
  90         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  91         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  92         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  93         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  94         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  95                 return 0;
  96         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  97                 return 0;
  98         default:
  99                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
 100                 return 0;
 101         }
 102 }
 103
 104 static int
 105 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 106 {
 107         struct nvfx_screen *screen = nvfx_screen(pscreen);
 108
 109         switch(shader) {
 110         case PIPE_SHADER_FRAGMENT:
 111                 switch(param) {
 112                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 113                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 114                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 115                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 116                         return 4096;
 117                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 118                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 119                          value (nv30:0/nv40:4) ? */
 120                         return screen->use_nv4x ? 4 : 0;
 121                 case PIPE_SHADER_CAP_MAX_INPUTS:
 122                         return screen->use_nv4x ? 12 : 10;
 123                 case PIPE_SHADER_CAP_MAX_CONSTS:
 124                         return screen->use_nv4x ? 224 : 32;
 125                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 126                     return 1;
 127                 case PIPE_SHADER_CAP_MAX_TEMPS:
 128                         return 32;
 129                 case PIPE_SHADER_CAP_MAX_ADDRS:
 130                         return screen->use_nv4x ? 1 : 0;
 131                 case PIPE_SHADER_CAP_MAX_PREDS:
 132                         return 0; /* we could expose these, but nothing uses them */
 133                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 134                     return 0;
 135                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 136                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 137                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 138                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 139                         return 0;
 140                 case PIPE_SHADER_CAP_SUBROUTINES:
 141                         return screen->use_nv4x ? 1 : 0;
 142                 default:
 143                         break;
 144                 }
 145                 break;
 146         case PIPE_SHADER_VERTEX:
 147                 switch(param) {
 148                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 149                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 150                         return screen->use_nv4x ? 512 : 256;
 151                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 152                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 153                         return screen->use_nv4x ? 512 : 0;
 154                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 155                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 156                          value (nv30:1/nv40:4) ? */
 157                         return screen->use_nv4x ? 4 : 1;
 158                 case PIPE_SHADER_CAP_MAX_INPUTS:
 159                         return 16;
 160                 case PIPE_SHADER_CAP_MAX_CONSTS:
 161                         /* - 6 is for clip planes; Gallium should be fixed to put
 162                          * them in the vertex shader itself, so we don't need to reserve these */
 163                         return (screen->use_nv4x ? 468 : 256) - 6;
 164                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 165                             return 1;
 166                 case PIPE_SHADER_CAP_MAX_TEMPS:
 167                         return screen->use_nv4x ? 32 : 13;
 168                 case PIPE_SHADER_CAP_MAX_ADDRS:
 169                         return 2;
 170                 case PIPE_SHADER_CAP_MAX_PREDS:
 171                         return 0; /* we could expose these, but nothing uses them */
 172                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 173                         return 1;
 174                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 175                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 176                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 177                         return 0;
 178                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 179                         return 1;
 180                 case PIPE_SHADER_CAP_SUBROUTINES:
 181                         return 1;
 182                 case PIPE_SHADER_CAP_INTEGERS:
 183                         return 0;
 184                 default:
 185                         break;
 186                 }
 187                 break;
 188         default:
 189                 break;
 190         }
 191         return 0;
 192 }
 193
 194 static float
 195 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 196 {
 197         struct nvfx_screen *screen = nvfx_screen(pscreen);
 198
 199         switch (param) {
 200         case PIPE_CAP_MAX_LINE_WIDTH:
 201         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 202                 return 10.0;
 203         case PIPE_CAP_MAX_POINT_WIDTH:
 204         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 205                 return 64.0;
 206         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 207                 return screen->use_nv4x ? 16.0 : 8.0;
 208         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 209                 return 15.0;
 210         default:
 211                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 212                 return 0.0;
 213         }
 214 }
 215
 216 static int
 217 nvfx_screen_get_video_param(struct pipe_screen *screen,
 218                                 enum pipe_video_profile profile,
 219                                 enum pipe_video_cap param)
 220 {
 221         switch (param) {
 222         case PIPE_VIDEO_CAP_SUPPORTED:
 223                 return vl_profile_supported(screen, profile);
 224         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 225                 return 0;
 226         case PIPE_VIDEO_CAP_MAX_WIDTH:
 227         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 228                 return vl_video_buffer_max_size(screen);
 229         default:
 230                 return 0;
 231         }
 232 }
 233
 234 static boolean
 235 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 236                                      enum pipe_format format,
 237                                      enum pipe_texture_target target,
 238                                      unsigned sample_count,
 239                                      unsigned bind)
 240 {
 241         struct nvfx_screen *screen = nvfx_screen(pscreen);
 242
 243         if (!util_format_is_supported(format, bind))
 244                 return FALSE;
 245
 246          if (sample_count > 1)
 247                 return FALSE;
 248
 249         if (bind & PIPE_BIND_RENDER_TARGET) {
 250                 switch (format) {
 251                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 252                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 253                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 254                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 255                 case PIPE_FORMAT_B5G6R5_UNORM:
 256                         break;
 257                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 258                         if(!screen->advertise_fp16)
 259                                 return FALSE;
 260                         break;
 261                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 262                         if(!screen->advertise_fp32)
 263                                 return FALSE;
 264                         break;
 265                 default:
 266                         return FALSE;
 267                 }
 268         }
 269
 270         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 271                 switch (format) {
 272                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 273                 case PIPE_FORMAT_X8Z24_UNORM:
 274                 case PIPE_FORMAT_Z16_UNORM:
 275                         break;
 276                 default:
 277                         return FALSE;
 278                 }
 279         }
 280
 281         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 282                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 283                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 284                         return FALSE;
 285                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 286                         return FALSE;
 287                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 288                         return FALSE;
 289                 if(screen->use_nv4x)
 290                 {
 291                         if(tf->fmt[4] < 0)
 292                                 return FALSE;
 293                 }
 294                 else
 295                 {
 296                         if(tf->fmt[0] < 0)
 297                                 return FALSE;
 298                 }
 299         }
 300
 301         // note that we do actually support everything through translate
 302         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 303                 unsigned type = nvfx_vertex_formats[format];
 304                 if(!type)
 305                         return FALSE;
 306         }
 307
 308         if (bind & PIPE_BIND_INDEX_BUFFER) {
 309                 // 8-bit indices supported, but not in hardware index buffer
 310                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 311                         return FALSE;
 312         }
 313
 314         if(bind & PIPE_BIND_STREAM_OUTPUT)
 315                 return FALSE;
 316
 317         return TRUE;
 318 }
 319
 320 static void
 321 nvfx_screen_destroy(struct pipe_screen *pscreen)
 322 {
 323         struct nvfx_screen *screen = nvfx_screen(pscreen);
 324
 325         nouveau_resource_destroy(&screen->vp_exec_heap);
 326         nouveau_resource_destroy(&screen->vp_data_heap);
 327         nouveau_resource_destroy(&screen->query_heap);
 328         nouveau_notifier_free(&screen->query);
 329         nouveau_notifier_free(&screen->sync);
 330         nouveau_grobj_free(&screen->eng3d);
 331         nvfx_screen_surface_takedown(pscreen);
 332         nouveau_bo_ref(NULL, &screen->fence);
 333
 334         nouveau_screen_fini(&screen->base);
 335
 336         FREE(pscreen);
 337 }
 338
 339 static void nv30_screen_init(struct nvfx_screen *screen)
 340 {
 341         struct nouveau_channel *chan = screen->base.channel;
 342         struct nouveau_grobj *eng3d = screen->eng3d;
 343         int i;
 344
 345         /* TODO: perhaps we should do some of this on nv40 too? */
 346         for (i=1; i<8; i++) {
 347                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 348                 OUT_RING(chan, 0);
 349                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 350                 OUT_RING(chan, 0);
 351         }
 352
 353         BEGIN_RING(chan, eng3d, 0x220, 1);
 354         OUT_RING(chan, 1);
 355
 356         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 357         OUT_RING(chan, 0x00100000);
 358         BEGIN_RING(chan, eng3d, 0x1454, 1);
 359         OUT_RING(chan, 0);
 360         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 361         OUT_RING(chan, 3);
 362         BEGIN_RING(chan, eng3d, 0x1450, 1);
 363         OUT_RING(chan, 0x00030004);
 364
 365         /* NEW */
 366         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 367         OUT_RING(chan, 0);
 368         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 369         OUT_RING(chan, fui(0.0));
 370         OUT_RING(chan, fui(0.0));
 371         OUT_RING(chan, fui(1.0));
 372         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 373         for (i=0; i<16; i++) {
 374                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 375         }
 376
 377         BEGIN_RING(chan, eng3d, 0x120, 3);
 378         OUT_RING(chan, 0);
 379         OUT_RING(chan, 1);
 380         OUT_RING(chan, 2);
 381
 382         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 383         OUT_RING(chan, 0x00001200);
 384
 385         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 386         OUT_RING(chan, 0);
 387
 388         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 389         OUT_RING(chan, fui(0.0));
 390         OUT_RING(chan, fui(1.0));
 391
 392         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 393         OUT_RING(chan, 0xffff0000);
 394
 395         /* enables use of vp rather than fixed-function somehow */
 396         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 397         OUT_RING(chan, 0x13);
 398 }
 399
 400 static void nv40_screen_init(struct nvfx_screen *screen)
 401 {
 402         struct nouveau_channel *chan = screen->base.channel;
 403         struct nouveau_grobj *eng3d = screen->eng3d;
 404
 405         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 406         OUT_RING(chan, screen->base.channel->vram->handle);
 407         OUT_RING(chan, screen->base.channel->vram->handle);
 408
 409         BEGIN_RING(chan, eng3d, 0x1450, 1);
 410         OUT_RING(chan, 0x00000004);
 411
 412         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 413         OUT_RING(chan, 0x00000010);
 414         OUT_RING(chan, 0x01000100);
 415         OUT_RING(chan, 0xff800006);
 416
 417         /* vtxprog output routing */
 418         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 419         OUT_RING(chan, 0x06144321);
 420         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 421         OUT_RING(chan, 0xedcba987);
 422         OUT_RING(chan, 0x0000006f);
 423         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 424         OUT_RING(chan, 0x00171615);
 425         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 426         OUT_RING(chan, 0x001b1a19);
 427
 428         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 429         OUT_RING(chan, 0x0020ffff);
 430         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 431         OUT_RING(chan, 0x01d300d4);
 432         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 433         OUT_RING(chan, 0x00000001);
 434
 435         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 436         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 437 }
 438
 439 static unsigned
 440 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 441 {
 442         int vram_hack_default = 0;
 443         int vram_hack;
 444         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 445         // It may also depend on the specific card or the AGP/PCIe chipset.
 446         if(screen->base.device->chipset == 0x47 /* G70 */
 447                 || screen->base.device->chipset == 0x49 /* G71 */
 448                 || screen->base.device->chipset == 0x46 /* G72 */
 449                 )
 450                 vram_hack_default = 1;
 451         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 452
 453         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 454 }
 455
 456 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 457 {
 458         struct nvfx_screen* screen = chan->user_private;
 459         struct nvfx_context* nvfx = screen->cur_ctx;
 460         if(nvfx)
 461                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 462 }
 463
 464 struct pipe_screen *
 465 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 466 {
 467         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 468         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 469         struct nouveau_channel *chan;
 470         struct pipe_screen *pscreen;
 471         unsigned eng3d_class = 0;
 472         int ret, i;
 473
 474         if (!screen)
 475                 return NULL;
 476
 477         pscreen = &screen->base.base;
 478
 479         ret = nouveau_screen_init(&screen->base, dev);
 480         if (ret) {
 481                 nvfx_screen_destroy(pscreen);
 482                 return NULL;
 483         }
 484         chan = screen->base.channel;
 485         screen->cur_ctx = NULL;
 486         chan->user_private = screen;
 487         chan->flush_notify = nvfx_channel_flush_notify;
 488
 489         pscreen->winsys = ws;
 490         pscreen->destroy = nvfx_screen_destroy;
 491         pscreen->get_param = nvfx_screen_get_param;
 492         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 493         pscreen->get_paramf = nvfx_screen_get_paramf;
 494         pscreen->get_video_param = nvfx_screen_get_video_param;
 495         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 496         pscreen->is_video_format_supported = vl_video_buffer_is_format_supported;
 497         pscreen->context_create = nvfx_create;
 498
 499         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 4096, &screen->fence);
 500         if (ret) {
 501                 nvfx_screen_destroy(pscreen);
 502                 return NULL;
 503         }
 504
 505         switch (dev->chipset & 0xf0) {
 506         case 0x30:
 507                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 508                         eng3d_class = NV30_3D;
 509                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 510                         eng3d_class = NV34_3D;
 511                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 512                         eng3d_class = NV35_3D;
 513                 break;
 514         case 0x40:
 515                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 516                         eng3d_class = NV40_3D;
 517                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 518                         eng3d_class = NV44_3D;
 519                 screen->is_nv4x = ~0;
 520                 break;
 521         case 0x60:
 522                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 523                         eng3d_class = NV44_3D;
 524                 screen->is_nv4x = ~0;
 525                 break;
 526         }
 527
 528         if (!eng3d_class) {
 529                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 530                 return NULL;
 531         }
 532
 533         screen->advertise_npot = !!screen->is_nv4x;
 534         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 535         screen->use_nv4x = screen->is_nv4x;
 536
 537         if(screen->is_nv4x) {
 538                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 539                         screen->use_nv4x = 0;
 540                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 541                         screen->advertise_npot = 0;
 542                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 543                         screen->advertise_blend_equation_separate = 0;
 544         }
 545
 546         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 547         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 548
 549         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 550         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 551         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 552
 553         /* We don't advertise these by default because filtering and blending doesn't work as
 554          * it should, due to several restrictions.
 555          * The only exception is fp16 on nv40.
 556          */
 557         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 558         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 559
 560         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 561
 562         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 563         if(eng3d_class == NV40_3D)
 564                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 565
 566         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 567                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 568
 569         nvfx_screen_init_resource_functions(pscreen);
 570
 571         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 572         if (ret) {
 573                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 574                 return FALSE;
 575         }
 576
 577         /* 2D engine setup */
 578         nvfx_screen_surface_init(pscreen);
 579
 580         /* Notifier for sync purposes */
 581         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 582         if (ret) {
 583                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 584                 nvfx_screen_destroy(pscreen);
 585                 return NULL;
 586         }
 587
 588         /* Query objects */
 589         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 590         {
 591                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 592                 if(!ret)
 593                         break;
 594         }
 595
 596         if (ret) {
 597                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 598                 nvfx_screen_destroy(pscreen);
 599                 return NULL;
 600         }
 601
 602         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 603         if (ret) {
 604                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 605                 nvfx_screen_destroy(pscreen);
 606                 return NULL;
 607         }
 608
 609         LIST_INITHEAD(&screen->query_list);
 610
 611         /* Vtxprog resources */
 612         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 613             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 614                 nvfx_screen_destroy(pscreen);
 615                 return NULL;
 616         }
 617
 618         BIND_RING(chan, screen->eng3d, 7);
 619
 620         /* Static eng3d initialisation */
 621         /* note that we just started using the channel, so we must have space in the pushbuffer */
 622         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 623         OUT_RING(chan, screen->sync->handle);
 624         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 625         OUT_RING(chan, chan->vram->handle);
 626         OUT_RING(chan, chan->gart->handle);
 627         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 628         OUT_RING(chan, chan->vram->handle);
 629         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 630         OUT_RING(chan, chan->vram->handle);
 631         OUT_RING(chan, chan->vram->handle);
 632         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 633         OUT_RING(chan, chan->vram->handle);
 634         OUT_RING(chan, chan->gart->handle);
 635
 636         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 637         OUT_RING(chan, 0);
 638         OUT_RING(chan, screen->query->handle);
 639
 640         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 641         OUT_RING(chan, chan->vram->handle);
 642         OUT_RING(chan, chan->vram->handle);
 643
 644         if(!screen->is_nv4x)
 645                 nv30_screen_init(screen);
 646         else
 647                 nv40_screen_init(screen);
 648
 649         return pscreen;
 650 }