src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_simple_screen.h"
   4
   5 #include "nouveau/nouveau_screen.h"
   6
   7 #include "nvfx_context.h"
   8 #include "nvfx_screen.h"
   9 #include "nvfx_resource.h"
  10
  11 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  12 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  13 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  14
  15 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  16 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  17 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  18 * with same number of bits everywhere.
  19 */
  20 struct nouveau_winsys {
  21         struct pipe_winsys base;
  22
  23         struct pipe_screen *pscreen;
  24
  25         struct pipe_surface *front;
  26 };
  27 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  28 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  29 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  30
  31 static int
  32 nvfx_screen_get_param(struct pipe_screen *pscreen, int param)
  33 {
  34         struct nvfx_screen *screen = nvfx_screen(pscreen);
  35
  36         switch (param) {
  37         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  38                 /* TODO: check this */
  39                 return screen->is_nv4x ? 16 : 8;
  40         case PIPE_CAP_NPOT_TEXTURES:
  41                 return !!screen->is_nv4x;
  42         case PIPE_CAP_TWO_SIDED_STENCIL:
  43                 return 1;
  44         case PIPE_CAP_GLSL:
  45                 return 0;
  46         case PIPE_CAP_ANISOTROPIC_FILTER:
  47                 return 1;
  48         case PIPE_CAP_POINT_SPRITE:
  49                 return 1;
  50         case PIPE_CAP_MAX_RENDER_TARGETS:
  51                 return screen->is_nv4x ? 4 : 2;
  52         case PIPE_CAP_OCCLUSION_QUERY:
  53                 return 1;
  54         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  55                 return 1;
  56         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  57                 return 13;
  58         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  59                 return 10;
  60         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  61                 return 13;
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63                 return !!screen->is_nv4x;
  64         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  65                 return 1;
  66         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  67                 return 0; /* We have 4 on nv40 - but unsupported currently */
  68         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  69                 return 0;
  70         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  71                 return !!screen->is_nv4x;
  72         case NOUVEAU_CAP_HW_VTXBUF:
  73                 return 0;
  74         case NOUVEAU_CAP_HW_IDXBUF:
  75                 return 0;
  76         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  77                 return 16;
  78         case PIPE_CAP_INDEP_BLEND_ENABLE:
  79                 /* TODO: on nv40 we have separate color masks */
  80                 /* TODO: nv40 mrt blending is probably broken */
  81                 return 0;
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83                 return 0;
  84         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  85         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  86                 return 1;
  87         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  88         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  89                 return 0;
  90         default:
  91                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  92                 return 0;
  93         }
  94 }
  95
  96 static float
  97 nvfx_screen_get_paramf(struct pipe_screen *pscreen, int param)
  98 {
  99         struct nvfx_screen *screen = nvfx_screen(pscreen);
 100
 101         switch (param) {
 102         case PIPE_CAP_MAX_LINE_WIDTH:
 103         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 104                 return 10.0;
 105         case PIPE_CAP_MAX_POINT_WIDTH:
 106         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 107                 return 64.0;
 108         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 109                 return screen->is_nv4x ? 16.0 : 8.0;
 110         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 111                 return screen->is_nv4x ? 16.0 : 4.0;
 112         default:
 113                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 114                 return 0.0;
 115         }
 116 }
 117
 118 static boolean
 119 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 120                                      enum pipe_format format,
 121                                      enum pipe_texture_target target,
 122                                      unsigned tex_usage, unsigned geom_flags)
 123 {
 124         struct nvfx_screen *screen = nvfx_screen(pscreen);
 125         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 126
 127         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
 128                 switch (format) {
 129                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 130                 case PIPE_FORMAT_B5G6R5_UNORM:
 131                         return TRUE;
 132                 default:
 133                         break;
 134                 }
 135         } else
 136         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 137                 switch (format) {
 138                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 139                 case PIPE_FORMAT_X8Z24_UNORM:
 140                         return TRUE;
 141                 case PIPE_FORMAT_Z16_UNORM:
 142                         /* TODO: this nv30 limitation probably does not exist */
 143                         if (!screen->is_nv4x && front)
 144                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 145                         return TRUE;
 146                 default:
 147                         break;
 148                 }
 149         } else {
 150                 switch (format) {
 151                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 152                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 153                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 154                 case PIPE_FORMAT_B5G6R5_UNORM:
 155                 case PIPE_FORMAT_L8_UNORM:
 156                 case PIPE_FORMAT_A8_UNORM:
 157                 case PIPE_FORMAT_I8_UNORM:
 158                 case PIPE_FORMAT_L8A8_UNORM:
 159                 case PIPE_FORMAT_Z16_UNORM:
 160                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 161                 case PIPE_FORMAT_DXT1_RGB:
 162                 case PIPE_FORMAT_DXT1_RGBA:
 163                 case PIPE_FORMAT_DXT3_RGBA:
 164                 case PIPE_FORMAT_DXT5_RGBA:
 165                         return TRUE;
 166                 /* TODO: does nv30 support this? */
 167                 case PIPE_FORMAT_R16_SNORM:
 168                         return !!screen->is_nv4x;
 169                 default:
 170                         break;
 171                 }
 172         }
 173
 174         return FALSE;
 175 }
 176
 177
 178 static void
 179 nvfx_screen_destroy(struct pipe_screen *pscreen)
 180 {
 181         struct nvfx_screen *screen = nvfx_screen(pscreen);
 182         unsigned i;
 183
 184         for (i = 0; i < NVFX_STATE_MAX; i++) {
 185                 if (screen->state[i])
 186                         so_ref(NULL, &screen->state[i]);
 187         }
 188
 189         nouveau_resource_destroy(&screen->vp_exec_heap);
 190         nouveau_resource_destroy(&screen->vp_data_heap);
 191         nouveau_resource_destroy(&screen->query_heap);
 192         nouveau_notifier_free(&screen->query);
 193         nouveau_notifier_free(&screen->sync);
 194         nouveau_grobj_free(&screen->eng3d);
 195         nv04_surface_2d_takedown(&screen->eng2d);
 196
 197         nouveau_screen_fini(&screen->base);
 198
 199         FREE(pscreen);
 200 }
 201
 202 static void nv30_screen_init(struct nvfx_screen *screen, struct nouveau_stateobj* so)
 203 {
 204         int i;
 205
 206         /* TODO: perhaps we should do some of this on nv40 too? */
 207         for (i=1; i<8; i++) {
 208                 so_method(so, screen->eng3d, NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1);
 209                 so_data  (so, 0);
 210                 so_method(so, screen->eng3d, NV34TCL_VIEWPORT_CLIP_VERT(i), 1);
 211                 so_data  (so, 0);
 212         }
 213
 214         so_method(so, screen->eng3d, 0x220, 1);
 215         so_data  (so, 1);
 216
 217         so_method(so, screen->eng3d, 0x03b0, 1);
 218         so_data  (so, 0x00100000);
 219         so_method(so, screen->eng3d, 0x1454, 1);
 220         so_data  (so, 0);
 221         so_method(so, screen->eng3d, 0x1d80, 1);
 222         so_data  (so, 3);
 223         so_method(so, screen->eng3d, 0x1450, 1);
 224         so_data  (so, 0x00030004);
 225
 226         /* NEW */
 227         so_method(so, screen->eng3d, 0x1e98, 1);
 228         so_data  (so, 0);
 229         so_method(so, screen->eng3d, 0x17e0, 3);
 230         so_data  (so, fui(0.0));
 231         so_data  (so, fui(0.0));
 232         so_data  (so, fui(1.0));
 233         so_method(so, screen->eng3d, 0x1f80, 16);
 234         for (i=0; i<16; i++) {
 235                 so_data  (so, (i==8) ? 0x0000ffff : 0);
 236         }
 237
 238         so_method(so, screen->eng3d, 0x120, 3);
 239         so_data  (so, 0);
 240         so_data  (so, 1);
 241         so_data  (so, 2);
 242
 243         so_method(so, screen->eng3d, 0x1d88, 1);
 244         so_data  (so, 0x00001200);
 245
 246         so_method(so, screen->eng3d, NV34TCL_RC_ENABLE, 1);
 247         so_data  (so, 0);
 248
 249         so_method(so, screen->eng3d, NV34TCL_DEPTH_RANGE_NEAR, 2);
 250         so_data  (so, fui(0.0));
 251         so_data  (so, fui(1.0));
 252
 253         so_method(so, screen->eng3d, NV34TCL_MULTISAMPLE_CONTROL, 1);
 254         so_data  (so, 0xffff0000);
 255
 256         /* enables use of vp rather than fixed-function somehow */
 257         so_method(so, screen->eng3d, 0x1e94, 1);
 258         so_data  (so, 0x13);
 259 }
 260
 261 static void nv40_screen_init(struct nvfx_screen *screen, struct nouveau_stateobj* so)
 262 {
 263         so_method(so, screen->eng3d, NV40TCL_DMA_COLOR2, 2);
 264         so_data  (so, screen->base.channel->vram->handle);
 265         so_data  (so, screen->base.channel->vram->handle);
 266
 267         so_method(so, screen->eng3d, 0x1ea4, 3);
 268         so_data  (so, 0x00000010);
 269         so_data  (so, 0x01000100);
 270         so_data  (so, 0xff800006);
 271
 272         /* vtxprog output routing */
 273         so_method(so, screen->eng3d, 0x1fc4, 1);
 274         so_data  (so, 0x06144321);
 275         so_method(so, screen->eng3d, 0x1fc8, 2);
 276         so_data  (so, 0xedcba987);
 277         so_data  (so, 0x00000021);
 278         so_method(so, screen->eng3d, 0x1fd0, 1);
 279         so_data  (so, 0x00171615);
 280         so_method(so, screen->eng3d, 0x1fd4, 1);
 281         so_data  (so, 0x001b1a19);
 282
 283         so_method(so, screen->eng3d, 0x1ef8, 1);
 284         so_data  (so, 0x0020ffff);
 285         so_method(so, screen->eng3d, 0x1d64, 1);
 286         so_data  (so, 0x00d30000);
 287         so_method(so, screen->eng3d, 0x1e94, 1);
 288         so_data  (so, 0x00000001);
 289 }
 290
 291 static void
 292 nvfx_screen_init_buffer_functions(struct nvfx_screen* screen)
 293 {
 294         int vram_hack_default = 0;
 295         int vram_hack;
 296         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 297         // It may also depend on the specific card or the AGP/PCIe chipset.
 298         if(screen->base.device->chipset == 0x47 /* G70 */
 299                 || screen->base.device->chipset == 0x49 /* G71 */
 300                 || screen->base.device->chipset == 0x46 /* G72 */
 301                 )
 302                 vram_hack_default = 1;
 303         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 304
 305 #ifdef DEBUG
 306         if(!vram_hack)
 307         {
 308                 fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
 309                         "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
 310         }
 311         else
 312         {
 313                 fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n"
 314                         "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
 315         }
 316 #endif
 317
 318         screen->vertex_buffer_flags = vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 319 }
 320
 321 struct pipe_screen *
 322 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 323 {
 324         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 325         struct nouveau_channel *chan;
 326         struct pipe_screen *pscreen;
 327         struct nouveau_stateobj *so;
 328         unsigned eng3d_class = 0;
 329         int ret;
 330
 331         if (!screen)
 332                 return NULL;
 333
 334         pscreen = &screen->base.base;
 335
 336         ret = nouveau_screen_init(&screen->base, dev);
 337         if (ret) {
 338                 nvfx_screen_destroy(pscreen);
 339                 return NULL;
 340         }
 341         chan = screen->base.channel;
 342
 343         pscreen->winsys = ws;
 344         pscreen->destroy = nvfx_screen_destroy;
 345         pscreen->get_param = nvfx_screen_get_param;
 346         pscreen->get_paramf = nvfx_screen_get_paramf;
 347         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 348         pscreen->context_create = nvfx_create;
 349
 350         switch (dev->chipset & 0xf0) {
 351         case 0x30:
 352                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 353                         eng3d_class = 0x0397;
 354                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 355                         eng3d_class = 0x0697;
 356                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 357                         eng3d_class = 0x0497;
 358                 break;
 359         case 0x40:
 360                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 361                         eng3d_class = NV40TCL;
 362                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 363                         eng3d_class = NV44TCL;
 364                 screen->is_nv4x = ~0;
 365                 break;
 366         case 0x60:
 367                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 368                         eng3d_class = NV44TCL;
 369                 screen->is_nv4x = ~0;
 370                 break;
 371         }
 372
 373         if (!eng3d_class) {
 374                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 375                 return NULL;
 376         }
 377
 378         nvfx_screen_init_resource_functions(pscreen);
 379         nvfx_screen_init_buffer_functions(screen);
 380
 381         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 382         if (ret) {
 383                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 384                 return FALSE;
 385         }
 386
 387         /* 2D engine setup */
 388         screen->eng2d = nv04_surface_2d_init(&screen->base);
 389         screen->eng2d->buf = nvfx_surface_buffer;
 390
 391         /* Notifier for sync purposes */
 392         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 393         if (ret) {
 394                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 395                 nvfx_screen_destroy(pscreen);
 396                 return NULL;
 397         }
 398
 399         /* Query objects */
 400         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 401         if (ret) {
 402                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 403                 nvfx_screen_destroy(pscreen);
 404                 return NULL;
 405         }
 406
 407         ret = nouveau_resource_init(&screen->query_heap, 0, 32);
 408         if (ret) {
 409                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 410                 nvfx_screen_destroy(pscreen);
 411                 return NULL;
 412         }
 413
 414         /* Vtxprog resources */
 415         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 416             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 417                 nvfx_screen_destroy(pscreen);
 418                 return NULL;
 419         }
 420
 421         /* Static eng3d initialisation */
 422         /* make the so big and don't worry about exact values
 423            since we it will be thrown away immediately after use */
 424         so = so_new(256, 256, 0);
 425         so_method(so, screen->eng3d, NV34TCL_DMA_NOTIFY, 1);
 426         so_data  (so, screen->sync->handle);
 427         so_method(so, screen->eng3d, NV34TCL_DMA_TEXTURE0, 2);
 428         so_data  (so, chan->vram->handle);
 429         so_data  (so, chan->gart->handle);
 430         so_method(so, screen->eng3d, NV34TCL_DMA_COLOR1, 1);
 431         so_data  (so, chan->vram->handle);
 432         so_method(so, screen->eng3d, NV34TCL_DMA_COLOR0, 2);
 433         so_data  (so, chan->vram->handle);
 434         so_data  (so, chan->vram->handle);
 435         so_method(so, screen->eng3d, NV34TCL_DMA_VTXBUF0, 2);
 436         so_data  (so, chan->vram->handle);
 437         so_data  (so, chan->gart->handle);
 438
 439         so_method(so, screen->eng3d, NV34TCL_DMA_FENCE, 2);
 440         so_data  (so, 0);
 441         so_data  (so, screen->query->handle);
 442
 443         so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY7, 2);
 444         so_data  (so, chan->vram->handle);
 445         so_data  (so, chan->vram->handle);
 446
 447         if(!screen->is_nv4x)
 448                 nv30_screen_init(screen, so);
 449         else
 450                 nv40_screen_init(screen, so);
 451
 452         so_emit(chan, so);
 453         so_ref(NULL, &so);
 454         nouveau_pushbuf_flush(chan, 0);
 455
 456         return pscreen;
 457 }