src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7
   8 #include "nvfx_context.h"
   9 #include "nvfx_screen.h"
  10 #include "nvfx_resource.h"
  11
  12 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  13 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  14 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  15
  16 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  17 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  18 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  19 * with same number of bits everywhere.
  20 */
  21 struct nouveau_winsys {
  22         struct pipe_winsys base;
  23
  24         struct pipe_screen *pscreen;
  25
  26         struct pipe_surface *front;
  27 };
  28 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  29 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  30 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  31
  32 static int
  33 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  34 {
  35         struct nvfx_screen *screen = nvfx_screen(pscreen);
  36
  37         switch (param) {
  38         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  39                 /* TODO: check this */
  40                 return screen->is_nv4x ? 16 : 8;
  41         case PIPE_CAP_NPOT_TEXTURES:
  42                 return !!screen->is_nv4x;
  43         case PIPE_CAP_TWO_SIDED_STENCIL:
  44                 return 1;
  45         case PIPE_CAP_GLSL:
  46                 return 0;
  47         case PIPE_CAP_ANISOTROPIC_FILTER:
  48                 return 1;
  49         case PIPE_CAP_POINT_SPRITE:
  50                 return 1;
  51         case PIPE_CAP_MAX_RENDER_TARGETS:
  52                 return screen->is_nv4x ? 4 : 2;
  53         case PIPE_CAP_OCCLUSION_QUERY:
  54                 return 1;
  55         case PIPE_CAP_TIMER_QUERY:
  56                 return 0;
  57         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  58                 return 1;
  59         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  60                 return 13;
  61         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  62                 return 10;
  63         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  64                 return 13;
  65         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  66                 return !!screen->is_nv4x;
  67         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  68                 return 1;
  69         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  70                 return 0; /* We have 4 on nv40 - but unsupported currently */
  71         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  72                 return 0;
  73         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  74                 return !!screen->is_nv4x;
  75         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  76                 return 16;
  77         case PIPE_CAP_INDEP_BLEND_ENABLE:
  78                 /* TODO: on nv40 we have separate color masks */
  79                 /* TODO: nv40 mrt blending is probably broken */
  80                 return 0;
  81         case PIPE_CAP_INDEP_BLEND_FUNC:
  82                 return 0;
  83         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  84         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  85                 return 1;
  86         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  87         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  88                 return 0;
  89         case PIPE_CAP_MAX_FS_INSTRUCTIONS:
  90         case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
  91         case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
  92         case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS:
  93                 return 4096;
  94         case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH:
  95                 /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
  96                    value (nv30:0/nv40:4) ? */
  97                 return screen->is_nv4x ? 4 : 0;
  98         case PIPE_CAP_MAX_FS_INPUTS:
  99                 return 10;
 100         case PIPE_CAP_MAX_FS_CONSTS:
 101                 return screen->is_nv4x ? 224 : 32;
 102         case PIPE_CAP_MAX_FS_TEMPS:
 103                 return 32;
 104         case PIPE_CAP_MAX_FS_ADDRS:
 105                 return screen->is_nv4x ? 1 : 0;
 106         case PIPE_CAP_MAX_FS_PREDS:
 107                 return screen->is_nv4x ? 1 : 0;
 108         case PIPE_CAP_MAX_VS_INSTRUCTIONS:
 109         case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
 110                 return screen->is_nv4x ? 512 : 256;
 111         case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
 112         case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
 113                 return screen->is_nv4x ? 512 : 0;
 114         case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
 115                 /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 116                    value (nv30:1/nv40:4) ? */
 117                 return screen->is_nv4x ? 4 : 1;
 118         case PIPE_CAP_MAX_VS_INPUTS:
 119                 return 16;
 120         case PIPE_CAP_MAX_VS_CONSTS:
 121                 return 256;
 122         case PIPE_CAP_MAX_VS_TEMPS:
 123                 return screen->is_nv4x ? 32 : 13;
 124         case PIPE_CAP_MAX_VS_ADDRS:
 125                 return 2;
 126         case PIPE_CAP_MAX_VS_PREDS:
 127                 return screen->is_nv4x ? 1 : 0;
 128         default:
 129                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 130                 return 0;
 131         }
 132 }
 133
 134 static float
 135 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 136 {
 137         struct nvfx_screen *screen = nvfx_screen(pscreen);
 138
 139         switch (param) {
 140         case PIPE_CAP_MAX_LINE_WIDTH:
 141         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 142                 return 10.0;
 143         case PIPE_CAP_MAX_POINT_WIDTH:
 144         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 145                 return 64.0;
 146         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 147                 return screen->is_nv4x ? 16.0 : 8.0;
 148         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 149                 return screen->is_nv4x ? 16.0 : 4.0;
 150         default:
 151                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 152                 return 0.0;
 153         }
 154 }
 155
 156 static boolean
 157 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 158                                      enum pipe_format format,
 159                                      enum pipe_texture_target target,
 160                                      unsigned sample_count,
 161                                      unsigned tex_usage, unsigned geom_flags)
 162 {
 163         struct nvfx_screen *screen = nvfx_screen(pscreen);
 164         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 165
 166          if (sample_count > 1)
 167                 return FALSE;
 168
 169         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
 170                 switch (format) {
 171                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 172                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 173                 case PIPE_FORMAT_B5G6R5_UNORM:
 174                         return TRUE;
 175                 default:
 176                         break;
 177                 }
 178         } else
 179         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 180                 switch (format) {
 181                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 182                 case PIPE_FORMAT_X8Z24_UNORM:
 183                         return TRUE;
 184                 case PIPE_FORMAT_Z16_UNORM:
 185                         /* TODO: this nv30 limitation probably does not exist */
 186                         if (!screen->is_nv4x && front)
 187                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 188                         return TRUE;
 189                 default:
 190                         break;
 191                 }
 192         } else {
 193                 switch (format) {
 194                 if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
 195                         switch (format) {
 196                         case PIPE_FORMAT_DXT1_RGB:
 197                         case PIPE_FORMAT_DXT1_RGBA:
 198                         case PIPE_FORMAT_DXT3_RGBA:
 199                         case PIPE_FORMAT_DXT5_RGBA:
 200                                 return util_format_s3tc_enabled;
 201                         default:
 202                                 break;
 203                         }
 204                 }
 205                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 206                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 207                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 208                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 209                 case PIPE_FORMAT_B5G6R5_UNORM:
 210                 case PIPE_FORMAT_L8_UNORM:
 211                 case PIPE_FORMAT_A8_UNORM:
 212                 case PIPE_FORMAT_I8_UNORM:
 213                 case PIPE_FORMAT_L8A8_UNORM:
 214                 case PIPE_FORMAT_Z16_UNORM:
 215                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 216                         return TRUE;
 217                 /* TODO: does nv30 support this? */
 218                 case PIPE_FORMAT_R16_SNORM:
 219                         return !!screen->is_nv4x;
 220                 default:
 221                         break;
 222                 }
 223         }
 224
 225         return FALSE;
 226 }
 227
 228
 229 static void
 230 nvfx_screen_destroy(struct pipe_screen *pscreen)
 231 {
 232         struct nvfx_screen *screen = nvfx_screen(pscreen);
 233
 234         nouveau_resource_destroy(&screen->vp_exec_heap);
 235         nouveau_resource_destroy(&screen->vp_data_heap);
 236         nouveau_resource_destroy(&screen->query_heap);
 237         nouveau_notifier_free(&screen->query);
 238         nouveau_notifier_free(&screen->sync);
 239         nouveau_grobj_free(&screen->eng3d);
 240         nv04_surface_2d_takedown(&screen->eng2d);
 241
 242         nouveau_screen_fini(&screen->base);
 243
 244         FREE(pscreen);
 245 }
 246
 247 static void nv30_screen_init(struct nvfx_screen *screen)
 248 {
 249         struct nouveau_channel *chan = screen->base.channel;
 250         int i;
 251
 252         /* TODO: perhaps we should do some of this on nv40 too? */
 253         for (i=1; i<8; i++) {
 254                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1));
 255                 OUT_RING(chan, 0);
 256                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1));
 257                 OUT_RING(chan, 0);
 258         }
 259
 260         OUT_RING(chan, RING_3D(0x220, 1));
 261         OUT_RING(chan, 1);
 262
 263         OUT_RING(chan, RING_3D(0x03b0, 1));
 264         OUT_RING(chan, 0x00100000);
 265         OUT_RING(chan, RING_3D(0x1454, 1));
 266         OUT_RING(chan, 0);
 267         OUT_RING(chan, RING_3D(0x1d80, 1));
 268         OUT_RING(chan, 3);
 269         OUT_RING(chan, RING_3D(0x1450, 1));
 270         OUT_RING(chan, 0x00030004);
 271
 272         /* NEW */
 273         OUT_RING(chan, RING_3D(0x1e98, 1));
 274         OUT_RING(chan, 0);
 275         OUT_RING(chan, RING_3D(0x17e0, 3));
 276         OUT_RING(chan, fui(0.0));
 277         OUT_RING(chan, fui(0.0));
 278         OUT_RING(chan, fui(1.0));
 279         OUT_RING(chan, RING_3D(0x1f80, 16));
 280         for (i=0; i<16; i++) {
 281                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 282         }
 283
 284         OUT_RING(chan, RING_3D(0x120, 3));
 285         OUT_RING(chan, 0);
 286         OUT_RING(chan, 1);
 287         OUT_RING(chan, 2);
 288
 289         OUT_RING(chan, RING_3D(0x1d88, 1));
 290         OUT_RING(chan, 0x00001200);
 291
 292         OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1));
 293         OUT_RING(chan, 0);
 294
 295         OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2));
 296         OUT_RING(chan, fui(0.0));
 297         OUT_RING(chan, fui(1.0));
 298
 299         OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1));
 300         OUT_RING(chan, 0xffff0000);
 301
 302         /* enables use of vp rather than fixed-function somehow */
 303         OUT_RING(chan, RING_3D(0x1e94, 1));
 304         OUT_RING(chan, 0x13);
 305 }
 306
 307 static void nv40_screen_init(struct nvfx_screen *screen)
 308 {
 309         struct nouveau_channel *chan = screen->base.channel;
 310
 311         OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2));
 312         OUT_RING(chan, screen->base.channel->vram->handle);
 313         OUT_RING(chan, screen->base.channel->vram->handle);
 314
 315         OUT_RING(chan, RING_3D(0x1ea4, 3));
 316         OUT_RING(chan, 0x00000010);
 317         OUT_RING(chan, 0x01000100);
 318         OUT_RING(chan, 0xff800006);
 319
 320         /* vtxprog output routing */
 321         OUT_RING(chan, RING_3D(0x1fc4, 1));
 322         OUT_RING(chan, 0x06144321);
 323         OUT_RING(chan, RING_3D(0x1fc8, 2));
 324         OUT_RING(chan, 0xedcba987);
 325         OUT_RING(chan, 0x00000021);
 326         OUT_RING(chan, RING_3D(0x1fd0, 1));
 327         OUT_RING(chan, 0x00171615);
 328         OUT_RING(chan, RING_3D(0x1fd4, 1));
 329         OUT_RING(chan, 0x001b1a19);
 330
 331         OUT_RING(chan, RING_3D(0x1ef8, 1));
 332         OUT_RING(chan, 0x0020ffff);
 333         OUT_RING(chan, RING_3D(0x1d64, 1));
 334         OUT_RING(chan, 0x00d30000);
 335         OUT_RING(chan, RING_3D(0x1e94, 1));
 336         OUT_RING(chan, 0x00000001);
 337 }
 338
 339 static unsigned
 340 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 341 {
 342         int vram_hack_default = 0;
 343         int vram_hack;
 344         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 345         // It may also depend on the specific card or the AGP/PCIe chipset.
 346         if(screen->base.device->chipset == 0x47 /* G70 */
 347                 || screen->base.device->chipset == 0x49 /* G71 */
 348                 || screen->base.device->chipset == 0x46 /* G72 */
 349                 )
 350                 vram_hack_default = 1;
 351         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 352
 353 #ifdef DEBUG
 354         if(!vram_hack)
 355         {
 356                 fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
 357                         "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
 358         }
 359         else
 360         {
 361                 fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n"
 362                         "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
 363         }
 364 #endif
 365
 366         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 367 }
 368
 369 struct pipe_screen *
 370 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 371 {
 372         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 373         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 374         struct nouveau_channel *chan;
 375         struct pipe_screen *pscreen;
 376         unsigned eng3d_class = 0;
 377         int ret, i;
 378
 379         if (!screen)
 380                 return NULL;
 381
 382         pscreen = &screen->base.base;
 383
 384         ret = nouveau_screen_init(&screen->base, dev);
 385         if (ret) {
 386                 nvfx_screen_destroy(pscreen);
 387                 return NULL;
 388         }
 389         chan = screen->base.channel;
 390
 391         pscreen->winsys = ws;
 392         pscreen->destroy = nvfx_screen_destroy;
 393         pscreen->get_param = nvfx_screen_get_param;
 394         pscreen->get_paramf = nvfx_screen_get_paramf;
 395         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 396         pscreen->context_create = nvfx_create;
 397
 398         switch (dev->chipset & 0xf0) {
 399         case 0x30:
 400                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 401                         eng3d_class = 0x0397;
 402                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 403                         eng3d_class = 0x0697;
 404                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 405                         eng3d_class = 0x0497;
 406                 break;
 407         case 0x40:
 408                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 409                         eng3d_class = NV40TCL;
 410                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 411                         eng3d_class = NV44TCL;
 412                 screen->is_nv4x = ~0;
 413                 break;
 414         case 0x60:
 415                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 416                         eng3d_class = NV44TCL;
 417                 screen->is_nv4x = ~0;
 418                 break;
 419         }
 420
 421         if (!eng3d_class) {
 422                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 423                 return NULL;
 424         }
 425
 426         screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE);
 427
 428         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 429
 430         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 431         if(eng3d_class == NV40TCL)
 432                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 433
 434         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 435                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 436
 437         nvfx_screen_init_resource_functions(pscreen);
 438
 439         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 440         if (ret) {
 441                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 442                 return FALSE;
 443         }
 444
 445         /* 2D engine setup */
 446         screen->eng2d = nv04_surface_2d_init(&screen->base);
 447         screen->eng2d->buf = nvfx_surface_buffer;
 448
 449         /* Notifier for sync purposes */
 450         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 451         if (ret) {
 452                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 453                 nvfx_screen_destroy(pscreen);
 454                 return NULL;
 455         }
 456
 457         /* Query objects */
 458         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 459         {
 460                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 461                 if(!ret)
 462                         break;
 463         }
 464
 465         if (ret) {
 466                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 467                 nvfx_screen_destroy(pscreen);
 468                 return NULL;
 469         }
 470
 471         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 472         if (ret) {
 473                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 474                 nvfx_screen_destroy(pscreen);
 475                 return NULL;
 476         }
 477
 478         LIST_INITHEAD(&screen->query_list);
 479
 480         /* Vtxprog resources */
 481         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 482             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 483                 nvfx_screen_destroy(pscreen);
 484                 return NULL;
 485         }
 486
 487         BIND_RING(chan, screen->eng3d, 7);
 488
 489         /* Static eng3d initialisation */
 490         /* note that we just started using the channel, so we must have space in the pushbuffer */
 491         OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1));
 492         OUT_RING(chan, screen->sync->handle);
 493         OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2));
 494         OUT_RING(chan, chan->vram->handle);
 495         OUT_RING(chan, chan->gart->handle);
 496         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
 497         OUT_RING(chan, chan->vram->handle);
 498         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2));
 499         OUT_RING(chan, chan->vram->handle);
 500         OUT_RING(chan, chan->vram->handle);
 501         OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2));
 502         OUT_RING(chan, chan->vram->handle);
 503         OUT_RING(chan, chan->gart->handle);
 504
 505         OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2));
 506         OUT_RING(chan, 0);
 507         OUT_RING(chan, screen->query->handle);
 508
 509         OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2));
 510         OUT_RING(chan, chan->vram->handle);
 511         OUT_RING(chan, chan->vram->handle);
 512
 513         if(!screen->is_nv4x)
 514                 nv30_screen_init(screen);
 515         else
 516                 nv40_screen_init(screen);
 517
 518         return pscreen;
 519 }