docs: Update status of GL 3.x related extensions
[mesa.git] / src / gallium / drivers / nvfx / nvfx_screen.c
1 #include "pipe/p_screen.h"
2 #include "pipe/p_state.h"
3 #include "util/u_format_s3tc.h"
4 #include "util/u_simple_screen.h"
5
6 #include "nouveau/nouveau_screen.h"
7 #include "nouveau/nv_object.xml.h"
8 #include "nvfx_context.h"
9 #include "nvfx_screen.h"
10 #include "nvfx_resource.h"
11 #include "nvfx_tex.h"
12
13 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
14 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
15 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
16
17 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
18 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
19 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
20
21 static int
22 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
23 {
24 struct nvfx_screen *screen = nvfx_screen(pscreen);
25
26 switch (param) {
27 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
28 return 16;
29 case PIPE_CAP_NPOT_TEXTURES:
30 return screen->advertise_npot;
31 case PIPE_CAP_TWO_SIDED_STENCIL:
32 return 1;
33 case PIPE_CAP_GLSL:
34 return 1;
35 case PIPE_CAP_ANISOTROPIC_FILTER:
36 return 1;
37 case PIPE_CAP_POINT_SPRITE:
38 return 1;
39 case PIPE_CAP_MAX_RENDER_TARGETS:
40 return screen->use_nv4x ? 4 : 2;
41 case PIPE_CAP_OCCLUSION_QUERY:
42 return 1;
43 case PIPE_CAP_TIMER_QUERY:
44 return 0;
45 case PIPE_CAP_TEXTURE_SHADOW_MAP:
46 return 1;
47 case PIPE_CAP_TEXTURE_SWIZZLE:
48 return 1;
49 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
50 return 13;
51 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
52 return 10;
53 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
54 return 13;
55 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
56 return !!screen->use_nv4x;
57 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
58 return 1;
59 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
60 return 0; /* We have 4 on nv40 - but unsupported currently */
61 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
62 return screen->advertise_blend_equation_separate;
63 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
64 return 16;
65 case PIPE_CAP_INDEP_BLEND_ENABLE:
66 /* TODO: on nv40 we have separate color masks */
67 /* TODO: nv40 mrt blending is probably broken */
68 return 0;
69 case PIPE_CAP_INDEP_BLEND_FUNC:
70 return 0;
71 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
72 return 0;
73 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
74 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
75 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
76 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
77 return 1;
78 case PIPE_CAP_DEPTH_CLAMP:
79 return 0; // TODO: implement depth clamp
80 default:
81 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
82 return 0;
83 }
84 }
85
86 static int
87 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
88 {
89 struct nvfx_screen *screen = nvfx_screen(pscreen);
90
91 switch(shader) {
92 case PIPE_SHADER_FRAGMENT:
93 switch(param) {
94 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
95 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
96 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
97 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
98 return 4096;
99 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
100 /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
101 value (nv30:0/nv40:4) ? */
102 return screen->use_nv4x ? 4 : 0;
103 case PIPE_SHADER_CAP_MAX_INPUTS:
104 return screen->use_nv4x ? 12 : 10;
105 case PIPE_SHADER_CAP_MAX_CONSTS:
106 return screen->use_nv4x ? 224 : 32;
107 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
108 return 1;
109 case PIPE_SHADER_CAP_MAX_TEMPS:
110 return 32;
111 case PIPE_SHADER_CAP_MAX_ADDRS:
112 return screen->use_nv4x ? 1 : 0;
113 case PIPE_SHADER_CAP_MAX_PREDS:
114 return 0; /* we could expose these, but nothing uses them */
115 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
116 return 0;
117 default:
118 break;
119 }
120 break;
121 case PIPE_SHADER_VERTEX:
122 switch(param) {
123 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
124 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
125 return screen->use_nv4x ? 512 : 256;
126 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
127 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
128 return screen->use_nv4x ? 512 : 0;
129 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
130 /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
131 value (nv30:1/nv40:4) ? */
132 return screen->use_nv4x ? 4 : 1;
133 case PIPE_SHADER_CAP_MAX_INPUTS:
134 return 16;
135 case PIPE_SHADER_CAP_MAX_CONSTS:
136 /* - 6 is for clip planes; Gallium should be fixed to put
137 * them in the vertex shader itself, so we don't need to reserve these */
138 return (screen->use_nv4x ? 468 : 256) - 6;
139 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
140 return 1;
141 case PIPE_SHADER_CAP_MAX_TEMPS:
142 return screen->use_nv4x ? 32 : 13;
143 case PIPE_SHADER_CAP_MAX_ADDRS:
144 return 2;
145 case PIPE_SHADER_CAP_MAX_PREDS:
146 return 0; /* we could expose these, but nothing uses them */
147 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
148 return 1;
149 default:
150 break;
151 }
152 break;
153 default:
154 break;
155 }
156 return 0;
157 }
158
159 static float
160 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
161 {
162 struct nvfx_screen *screen = nvfx_screen(pscreen);
163
164 switch (param) {
165 case PIPE_CAP_MAX_LINE_WIDTH:
166 case PIPE_CAP_MAX_LINE_WIDTH_AA:
167 return 10.0;
168 case PIPE_CAP_MAX_POINT_WIDTH:
169 case PIPE_CAP_MAX_POINT_WIDTH_AA:
170 return 64.0;
171 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
172 return screen->use_nv4x ? 16.0 : 8.0;
173 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
174 return 15.0;
175 default:
176 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
177 return 0.0;
178 }
179 }
180
181 static boolean
182 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
183 enum pipe_format format,
184 enum pipe_texture_target target,
185 unsigned sample_count,
186 unsigned bind, unsigned geom_flags)
187 {
188 struct nvfx_screen *screen = nvfx_screen(pscreen);
189
190 if (sample_count > 1)
191 return FALSE;
192
193 if (bind & PIPE_BIND_RENDER_TARGET) {
194 switch (format) {
195 case PIPE_FORMAT_B8G8R8A8_UNORM:
196 case PIPE_FORMAT_B8G8R8X8_UNORM:
197 case PIPE_FORMAT_R8G8B8A8_UNORM:
198 case PIPE_FORMAT_R8G8B8X8_UNORM:
199 case PIPE_FORMAT_B5G6R5_UNORM:
200 break;
201 case PIPE_FORMAT_R16G16B16A16_FLOAT:
202 if(!screen->advertise_fp16)
203 return FALSE;
204 break;
205 case PIPE_FORMAT_R32G32B32A32_FLOAT:
206 if(!screen->advertise_fp32)
207 return FALSE;
208 break;
209 default:
210 return FALSE;
211 }
212 }
213
214 if (bind & PIPE_BIND_DEPTH_STENCIL) {
215 switch (format) {
216 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
217 case PIPE_FORMAT_X8Z24_UNORM:
218 case PIPE_FORMAT_Z16_UNORM:
219 break;
220 default:
221 return FALSE;
222 }
223 }
224
225 if (bind & PIPE_BIND_SAMPLER_VIEW) {
226 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
227 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
228 return FALSE;
229 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
230 return FALSE;
231 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
232 return FALSE;
233 if(screen->use_nv4x)
234 {
235 if(tf->fmt[4] < 0)
236 return FALSE;
237 }
238 else
239 {
240 if(tf->fmt[0] < 0)
241 return FALSE;
242 }
243 }
244
245 // note that we do actually support everything through translate
246 if (bind & PIPE_BIND_VERTEX_BUFFER) {
247 unsigned type = nvfx_vertex_formats[format];
248 if(!type)
249 return FALSE;
250 }
251
252 if (bind & PIPE_BIND_INDEX_BUFFER) {
253 // 8-bit indices supported, but not in hardware index buffer
254 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
255 return FALSE;
256 }
257
258 if(bind & PIPE_BIND_STREAM_OUTPUT)
259 return FALSE;
260
261 return TRUE;
262 }
263
264 static void
265 nvfx_screen_destroy(struct pipe_screen *pscreen)
266 {
267 struct nvfx_screen *screen = nvfx_screen(pscreen);
268
269 nouveau_resource_destroy(&screen->vp_exec_heap);
270 nouveau_resource_destroy(&screen->vp_data_heap);
271 nouveau_resource_destroy(&screen->query_heap);
272 nouveau_notifier_free(&screen->query);
273 nouveau_notifier_free(&screen->sync);
274 nouveau_grobj_free(&screen->eng3d);
275 nvfx_screen_surface_takedown(pscreen);
276
277 nouveau_screen_fini(&screen->base);
278
279 FREE(pscreen);
280 }
281
282 static void nv30_screen_init(struct nvfx_screen *screen)
283 {
284 struct nouveau_channel *chan = screen->base.channel;
285 int i;
286
287 /* TODO: perhaps we should do some of this on nv40 too? */
288 for (i=1; i<8; i++) {
289 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1));
290 OUT_RING(chan, 0);
291 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1));
292 OUT_RING(chan, 0);
293 }
294
295 OUT_RING(chan, RING_3D(0x220, 1));
296 OUT_RING(chan, 1);
297
298 OUT_RING(chan, RING_3D(0x03b0, 1));
299 OUT_RING(chan, 0x00100000);
300 OUT_RING(chan, RING_3D(0x1454, 1));
301 OUT_RING(chan, 0);
302 OUT_RING(chan, RING_3D(0x1d80, 1));
303 OUT_RING(chan, 3);
304 OUT_RING(chan, RING_3D(0x1450, 1));
305 OUT_RING(chan, 0x00030004);
306
307 /* NEW */
308 OUT_RING(chan, RING_3D(0x1e98, 1));
309 OUT_RING(chan, 0);
310 OUT_RING(chan, RING_3D(0x17e0, 3));
311 OUT_RING(chan, fui(0.0));
312 OUT_RING(chan, fui(0.0));
313 OUT_RING(chan, fui(1.0));
314 OUT_RING(chan, RING_3D(0x1f80, 16));
315 for (i=0; i<16; i++) {
316 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
317 }
318
319 OUT_RING(chan, RING_3D(0x120, 3));
320 OUT_RING(chan, 0);
321 OUT_RING(chan, 1);
322 OUT_RING(chan, 2);
323
324 OUT_RING(chan, RING_3D(0x1d88, 1));
325 OUT_RING(chan, 0x00001200);
326
327 OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1));
328 OUT_RING(chan, 0);
329
330 OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2));
331 OUT_RING(chan, fui(0.0));
332 OUT_RING(chan, fui(1.0));
333
334 OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1));
335 OUT_RING(chan, 0xffff0000);
336
337 /* enables use of vp rather than fixed-function somehow */
338 OUT_RING(chan, RING_3D(0x1e94, 1));
339 OUT_RING(chan, 0x13);
340 }
341
342 static void nv40_screen_init(struct nvfx_screen *screen)
343 {
344 struct nouveau_channel *chan = screen->base.channel;
345
346 OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2));
347 OUT_RING(chan, screen->base.channel->vram->handle);
348 OUT_RING(chan, screen->base.channel->vram->handle);
349
350 OUT_RING(chan, RING_3D(0x1450, 1));
351 OUT_RING(chan, 0x00000004);
352
353 OUT_RING(chan, RING_3D(0x1ea4, 3));
354 OUT_RING(chan, 0x00000010);
355 OUT_RING(chan, 0x01000100);
356 OUT_RING(chan, 0xff800006);
357
358 /* vtxprog output routing */
359 OUT_RING(chan, RING_3D(0x1fc4, 1));
360 OUT_RING(chan, 0x06144321);
361 OUT_RING(chan, RING_3D(0x1fc8, 2));
362 OUT_RING(chan, 0xedcba987);
363 OUT_RING(chan, 0x0000006f);
364 OUT_RING(chan, RING_3D(0x1fd0, 1));
365 OUT_RING(chan, 0x00171615);
366 OUT_RING(chan, RING_3D(0x1fd4, 1));
367 OUT_RING(chan, 0x001b1a19);
368
369 OUT_RING(chan, RING_3D(0x1ef8, 1));
370 OUT_RING(chan, 0x0020ffff);
371 OUT_RING(chan, RING_3D(0x1d64, 1));
372 OUT_RING(chan, 0x01d300d4);
373 OUT_RING(chan, RING_3D(0x1e94, 1));
374 OUT_RING(chan, 0x00000001);
375
376 OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1));
377 OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
378 }
379
380 static unsigned
381 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
382 {
383 int vram_hack_default = 0;
384 int vram_hack;
385 // TODO: this is a bit of a guess; also add other cards that may need this hack.
386 // It may also depend on the specific card or the AGP/PCIe chipset.
387 if(screen->base.device->chipset == 0x47 /* G70 */
388 || screen->base.device->chipset == 0x49 /* G71 */
389 || screen->base.device->chipset == 0x46 /* G72 */
390 )
391 vram_hack_default = 1;
392 vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
393
394 return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
395 }
396
397 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
398 {
399 struct nvfx_screen* screen = chan->user_private;
400 struct nvfx_context* nvfx = screen->cur_ctx;
401 if(nvfx)
402 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
403 }
404
405 struct pipe_screen *
406 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
407 {
408 static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
409 struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
410 struct nouveau_channel *chan;
411 struct pipe_screen *pscreen;
412 unsigned eng3d_class = 0;
413 int ret, i;
414
415 if (!screen)
416 return NULL;
417
418 pscreen = &screen->base.base;
419
420 ret = nouveau_screen_init(&screen->base, dev);
421 if (ret) {
422 nvfx_screen_destroy(pscreen);
423 return NULL;
424 }
425 chan = screen->base.channel;
426 screen->cur_ctx = NULL;
427 chan->user_private = screen;
428 chan->flush_notify = nvfx_channel_flush_notify;
429
430 pscreen->winsys = ws;
431 pscreen->destroy = nvfx_screen_destroy;
432 pscreen->get_param = nvfx_screen_get_param;
433 pscreen->get_shader_param = nvfx_screen_get_shader_param;
434 pscreen->get_paramf = nvfx_screen_get_paramf;
435 pscreen->is_format_supported = nvfx_screen_is_format_supported;
436 pscreen->context_create = nvfx_create;
437
438 switch (dev->chipset & 0xf0) {
439 case 0x30:
440 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
441 eng3d_class = NV30_3D;
442 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
443 eng3d_class = NV34_3D;
444 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
445 eng3d_class = NV35_3D;
446 break;
447 case 0x40:
448 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
449 eng3d_class = NV40_3D;
450 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
451 eng3d_class = NV44_3D;
452 screen->is_nv4x = ~0;
453 break;
454 case 0x60:
455 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
456 eng3d_class = NV44_3D;
457 screen->is_nv4x = ~0;
458 break;
459 }
460
461 if (!eng3d_class) {
462 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
463 return NULL;
464 }
465
466 screen->advertise_npot = !!screen->is_nv4x;
467 screen->advertise_blend_equation_separate = !!screen->is_nv4x;
468 screen->use_nv4x = screen->is_nv4x;
469
470 if(screen->is_nv4x) {
471 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
472 screen->use_nv4x = 0;
473 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
474 screen->advertise_npot = 0;
475 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
476 screen->advertise_blend_equation_separate = 0;
477 }
478
479 screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
480 screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
481
482 screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
483 screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
484 screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
485
486 /* We don't advertise these by default because filtering and blending doesn't work as
487 * it should, due to several restrictions.
488 * The only exception is fp16 on nv40.
489 */
490 screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
491 screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
492
493 screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
494
495 /* surely both nv3x and nv44 support index buffers too: find out how and test that */
496 if(eng3d_class == NV40_3D)
497 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
498
499 if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
500 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
501
502 nvfx_screen_init_resource_functions(pscreen);
503
504 ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
505 if (ret) {
506 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
507 return FALSE;
508 }
509
510 /* 2D engine setup */
511 nvfx_screen_surface_init(pscreen);
512
513 /* Notifier for sync purposes */
514 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
515 if (ret) {
516 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
517 nvfx_screen_destroy(pscreen);
518 return NULL;
519 }
520
521 /* Query objects */
522 for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
523 {
524 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
525 if(!ret)
526 break;
527 }
528
529 if (ret) {
530 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
531 nvfx_screen_destroy(pscreen);
532 return NULL;
533 }
534
535 ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
536 if (ret) {
537 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
538 nvfx_screen_destroy(pscreen);
539 return NULL;
540 }
541
542 LIST_INITHEAD(&screen->query_list);
543
544 /* Vtxprog resources */
545 if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
546 nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
547 nvfx_screen_destroy(pscreen);
548 return NULL;
549 }
550
551 BIND_RING(chan, screen->eng3d, 7);
552
553 /* Static eng3d initialisation */
554 /* note that we just started using the channel, so we must have space in the pushbuffer */
555 OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1));
556 OUT_RING(chan, screen->sync->handle);
557 OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2));
558 OUT_RING(chan, chan->vram->handle);
559 OUT_RING(chan, chan->gart->handle);
560 OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1));
561 OUT_RING(chan, chan->vram->handle);
562 OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2));
563 OUT_RING(chan, chan->vram->handle);
564 OUT_RING(chan, chan->vram->handle);
565 OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2));
566 OUT_RING(chan, chan->vram->handle);
567 OUT_RING(chan, chan->gart->handle);
568
569 OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2));
570 OUT_RING(chan, 0);
571 OUT_RING(chan, screen->query->handle);
572
573 OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2));
574 OUT_RING(chan, chan->vram->handle);
575 OUT_RING(chan, chan->vram->handle);
576
577 if(!screen->is_nv4x)
578 nv30_screen_init(screen);
579 else
580 nv40_screen_init(screen);
581
582 return pscreen;
583 }