src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7 #include "nouveau/nv_object.xml.h"
   8 #include "nvfx_context.h"
   9 #include "nvfx_video_context.h"
  10 #include "nvfx_screen.h"
  11 #include "nvfx_resource.h"
  12 #include "nvfx_tex.h"
  13
  14 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  15 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  16 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  17
  18 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  19 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  20 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  21
  22 static int
  23 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  24 {
  25         struct nvfx_screen *screen = nvfx_screen(pscreen);
  26
  27         switch (param) {
  28         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  29                 return 16;
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_GLSL:
  35                 return 1;
  36         case PIPE_CAP_ANISOTROPIC_FILTER:
  37                 return 1;
  38         case PIPE_CAP_POINT_SPRITE:
  39                 return 1;
  40         case PIPE_CAP_MAX_RENDER_TARGETS:
  41                 return screen->use_nv4x ? 4 : 1;
  42         case PIPE_CAP_OCCLUSION_QUERY:
  43                 return 1;
  44         case PIPE_CAP_TIMER_QUERY:
  45                 return 0;
  46         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  47                 return 1;
  48         case PIPE_CAP_TEXTURE_SWIZZLE:
  49                 return 1;
  50         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  51                 return 13;
  52         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  53                 return 10;
  54         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  57                 return !!screen->use_nv4x;
  58         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  59                 return 1;
  60         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  61                 return 0; /* We have 4 on nv40 - but unsupported currently */
  62         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  63                 return screen->advertise_blend_equation_separate;
  64         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  65                 return 16;
  66         case PIPE_CAP_INDEP_BLEND_ENABLE:
  67                 /* TODO: on nv40 we have separate color masks */
  68                 /* TODO: nv40 mrt blending is probably broken */
  69                 return 0;
  70         case PIPE_CAP_INDEP_BLEND_FUNC:
  71                 return 0;
  72         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  73                 return 0;
  74         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  75         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  76         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  77         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  78                 return 1;
  79         case PIPE_CAP_DEPTH_CLAMP:
  80                 return 0; // TODO: implement depth clamp
  81         case PIPE_CAP_PRIMITIVE_RESTART:
  82                 return 0; // TODO: implement primitive restart
  83         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  84                 return 0;
  85         default:
  86                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  87                 return 0;
  88         }
  89 }
  90
  91 static int
  92 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
  93 {
  94         struct nvfx_screen *screen = nvfx_screen(pscreen);
  95
  96         switch(shader) {
  97         case PIPE_SHADER_FRAGMENT:
  98                 switch(param) {
  99                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 100                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 101                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 102                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 103                         return 4096;
 104                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 105                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 106                          value (nv30:0/nv40:4) ? */
 107                         return screen->use_nv4x ? 4 : 0;
 108                 case PIPE_SHADER_CAP_MAX_INPUTS:
 109                         return screen->use_nv4x ? 12 : 10;
 110                 case PIPE_SHADER_CAP_MAX_CONSTS:
 111                         return screen->use_nv4x ? 224 : 32;
 112                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 113                     return 1;
 114                 case PIPE_SHADER_CAP_MAX_TEMPS:
 115                         return 32;
 116                 case PIPE_SHADER_CAP_MAX_ADDRS:
 117                         return screen->use_nv4x ? 1 : 0;
 118                 case PIPE_SHADER_CAP_MAX_PREDS:
 119                         return 0; /* we could expose these, but nothing uses them */
 120                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 121                     return 0;
 122                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 123                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 124                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 125                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 126                         return 0;
 127                 case PIPE_SHADER_CAP_SUBROUTINES:
 128                         return screen->use_nv4x ? 1 : 0;
 129                 default:
 130                         break;
 131                 }
 132                 break;
 133         case PIPE_SHADER_VERTEX:
 134                 switch(param) {
 135                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 136                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 137                         return screen->use_nv4x ? 512 : 256;
 138                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 139                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 140                         return screen->use_nv4x ? 512 : 0;
 141                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 142                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 143                          value (nv30:1/nv40:4) ? */
 144                         return screen->use_nv4x ? 4 : 1;
 145                 case PIPE_SHADER_CAP_MAX_INPUTS:
 146                         return 16;
 147                 case PIPE_SHADER_CAP_MAX_CONSTS:
 148                         /* - 6 is for clip planes; Gallium should be fixed to put
 149                          * them in the vertex shader itself, so we don't need to reserve these */
 150                         return (screen->use_nv4x ? 468 : 256) - 6;
 151                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 152                             return 1;
 153                 case PIPE_SHADER_CAP_MAX_TEMPS:
 154                         return screen->use_nv4x ? 32 : 13;
 155                 case PIPE_SHADER_CAP_MAX_ADDRS:
 156                         return 2;
 157                 case PIPE_SHADER_CAP_MAX_PREDS:
 158                         return 0; /* we could expose these, but nothing uses them */
 159                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 160                         return 1;
 161                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 162                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 163                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 164                         return 0;
 165                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 166                         return 1;
 167                 case PIPE_SHADER_CAP_SUBROUTINES:
 168                         return 1;
 169                 default:
 170                         break;
 171                 }
 172                 break;
 173         default:
 174                 break;
 175         }
 176         return 0;
 177 }
 178
 179 static float
 180 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 181 {
 182         struct nvfx_screen *screen = nvfx_screen(pscreen);
 183
 184         switch (param) {
 185         case PIPE_CAP_MAX_LINE_WIDTH:
 186         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 187                 return 10.0;
 188         case PIPE_CAP_MAX_POINT_WIDTH:
 189         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 190                 return 64.0;
 191         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 192                 return screen->use_nv4x ? 16.0 : 8.0;
 193         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 194                 return 15.0;
 195         default:
 196                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 197                 return 0.0;
 198         }
 199 }
 200
 201 static boolean
 202 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 203                                      enum pipe_format format,
 204                                      enum pipe_texture_target target,
 205                                      unsigned sample_count,
 206                                      unsigned bind)
 207 {
 208         struct nvfx_screen *screen = nvfx_screen(pscreen);
 209
 210          if (sample_count > 1)
 211                 return FALSE;
 212
 213         if (bind & PIPE_BIND_RENDER_TARGET) {
 214                 switch (format) {
 215                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 216                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 217                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 218                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 219                 case PIPE_FORMAT_B5G6R5_UNORM:
 220                         break;
 221                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 222                         if(!screen->advertise_fp16)
 223                                 return FALSE;
 224                         break;
 225                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 226                         if(!screen->advertise_fp32)
 227                                 return FALSE;
 228                         break;
 229                 default:
 230                         return FALSE;
 231                 }
 232         }
 233
 234         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 235                 switch (format) {
 236                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 237                 case PIPE_FORMAT_X8Z24_UNORM:
 238                 case PIPE_FORMAT_Z16_UNORM:
 239                         break;
 240                 default:
 241                         return FALSE;
 242                 }
 243         }
 244
 245         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 246                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 247                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 248                         return FALSE;
 249                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 250                         return FALSE;
 251                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 252                         return FALSE;
 253                 if(screen->use_nv4x)
 254                 {
 255                         if(tf->fmt[4] < 0)
 256                                 return FALSE;
 257                 }
 258                 else
 259                 {
 260                         if(tf->fmt[0] < 0)
 261                                 return FALSE;
 262                 }
 263         }
 264
 265         // note that we do actually support everything through translate
 266         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 267                 unsigned type = nvfx_vertex_formats[format];
 268                 if(!type)
 269                         return FALSE;
 270         }
 271
 272         if (bind & PIPE_BIND_INDEX_BUFFER) {
 273                 // 8-bit indices supported, but not in hardware index buffer
 274                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 275                         return FALSE;
 276         }
 277
 278         if(bind & PIPE_BIND_STREAM_OUTPUT)
 279                 return FALSE;
 280
 281         return TRUE;
 282 }
 283
 284 static void
 285 nvfx_screen_destroy(struct pipe_screen *pscreen)
 286 {
 287         struct nvfx_screen *screen = nvfx_screen(pscreen);
 288
 289         nouveau_resource_destroy(&screen->vp_exec_heap);
 290         nouveau_resource_destroy(&screen->vp_data_heap);
 291         nouveau_resource_destroy(&screen->query_heap);
 292         nouveau_notifier_free(&screen->query);
 293         nouveau_notifier_free(&screen->sync);
 294         nouveau_grobj_free(&screen->eng3d);
 295         nvfx_screen_surface_takedown(pscreen);
 296
 297         nouveau_screen_fini(&screen->base);
 298
 299         FREE(pscreen);
 300 }
 301
 302 static void nv30_screen_init(struct nvfx_screen *screen)
 303 {
 304         struct nouveau_channel *chan = screen->base.channel;
 305         struct nouveau_grobj *eng3d = screen->eng3d;
 306         int i;
 307
 308         /* TODO: perhaps we should do some of this on nv40 too? */
 309         for (i=1; i<8; i++) {
 310                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 311                 OUT_RING(chan, 0);
 312                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 313                 OUT_RING(chan, 0);
 314         }
 315
 316         BEGIN_RING(chan, eng3d, 0x220, 1);
 317         OUT_RING(chan, 1);
 318
 319         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 320         OUT_RING(chan, 0x00100000);
 321         BEGIN_RING(chan, eng3d, 0x1454, 1);
 322         OUT_RING(chan, 0);
 323         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 324         OUT_RING(chan, 3);
 325         BEGIN_RING(chan, eng3d, 0x1450, 1);
 326         OUT_RING(chan, 0x00030004);
 327
 328         /* NEW */
 329         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 330         OUT_RING(chan, 0);
 331         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 332         OUT_RING(chan, fui(0.0));
 333         OUT_RING(chan, fui(0.0));
 334         OUT_RING(chan, fui(1.0));
 335         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 336         for (i=0; i<16; i++) {
 337                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 338         }
 339
 340         BEGIN_RING(chan, eng3d, 0x120, 3);
 341         OUT_RING(chan, 0);
 342         OUT_RING(chan, 1);
 343         OUT_RING(chan, 2);
 344
 345         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 346         OUT_RING(chan, 0x00001200);
 347
 348         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 349         OUT_RING(chan, 0);
 350
 351         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 352         OUT_RING(chan, fui(0.0));
 353         OUT_RING(chan, fui(1.0));
 354
 355         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 356         OUT_RING(chan, 0xffff0000);
 357
 358         /* enables use of vp rather than fixed-function somehow */
 359         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 360         OUT_RING(chan, 0x13);
 361 }
 362
 363 static void nv40_screen_init(struct nvfx_screen *screen)
 364 {
 365         struct nouveau_channel *chan = screen->base.channel;
 366         struct nouveau_grobj *eng3d = screen->eng3d;
 367
 368         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 369         OUT_RING(chan, screen->base.channel->vram->handle);
 370         OUT_RING(chan, screen->base.channel->vram->handle);
 371
 372         BEGIN_RING(chan, eng3d, 0x1450, 1);
 373         OUT_RING(chan, 0x00000004);
 374
 375         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 376         OUT_RING(chan, 0x00000010);
 377         OUT_RING(chan, 0x01000100);
 378         OUT_RING(chan, 0xff800006);
 379
 380         /* vtxprog output routing */
 381         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 382         OUT_RING(chan, 0x06144321);
 383         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 384         OUT_RING(chan, 0xedcba987);
 385         OUT_RING(chan, 0x0000006f);
 386         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 387         OUT_RING(chan, 0x00171615);
 388         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 389         OUT_RING(chan, 0x001b1a19);
 390
 391         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 392         OUT_RING(chan, 0x0020ffff);
 393         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 394         OUT_RING(chan, 0x01d300d4);
 395         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 396         OUT_RING(chan, 0x00000001);
 397
 398         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 399         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 400 }
 401
 402 static unsigned
 403 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 404 {
 405         int vram_hack_default = 0;
 406         int vram_hack;
 407         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 408         // It may also depend on the specific card or the AGP/PCIe chipset.
 409         if(screen->base.device->chipset == 0x47 /* G70 */
 410                 || screen->base.device->chipset == 0x49 /* G71 */
 411                 || screen->base.device->chipset == 0x46 /* G72 */
 412                 )
 413                 vram_hack_default = 1;
 414         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 415
 416         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 417 }
 418
 419 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 420 {
 421         struct nvfx_screen* screen = chan->user_private;
 422         struct nvfx_context* nvfx = screen->cur_ctx;
 423         if(nvfx)
 424                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 425 }
 426
 427 struct pipe_screen *
 428 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 429 {
 430         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 431         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 432         struct nouveau_channel *chan;
 433         struct pipe_screen *pscreen;
 434         unsigned eng3d_class = 0;
 435         int ret, i;
 436
 437         if (!screen)
 438                 return NULL;
 439
 440         pscreen = &screen->base.base;
 441
 442         ret = nouveau_screen_init(&screen->base, dev);
 443         if (ret) {
 444                 nvfx_screen_destroy(pscreen);
 445                 return NULL;
 446         }
 447         chan = screen->base.channel;
 448         screen->cur_ctx = NULL;
 449         chan->user_private = screen;
 450         chan->flush_notify = nvfx_channel_flush_notify;
 451
 452         pscreen->winsys = ws;
 453         pscreen->destroy = nvfx_screen_destroy;
 454         pscreen->get_param = nvfx_screen_get_param;
 455         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 456         pscreen->get_paramf = nvfx_screen_get_paramf;
 457         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 458         pscreen->context_create = nvfx_create;
 459         pscreen->video_context_create = nvfx_video_create;
 460
 461         switch (dev->chipset & 0xf0) {
 462         case 0x30:
 463                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 464                         eng3d_class = NV30_3D;
 465                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 466                         eng3d_class = NV34_3D;
 467                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 468                         eng3d_class = NV35_3D;
 469                 break;
 470         case 0x40:
 471                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 472                         eng3d_class = NV40_3D;
 473                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 474                         eng3d_class = NV44_3D;
 475                 screen->is_nv4x = ~0;
 476                 break;
 477         case 0x60:
 478                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 479                         eng3d_class = NV44_3D;
 480                 screen->is_nv4x = ~0;
 481                 break;
 482         }
 483
 484         if (!eng3d_class) {
 485                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 486                 return NULL;
 487         }
 488
 489         screen->advertise_npot = !!screen->is_nv4x;
 490         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 491         screen->use_nv4x = screen->is_nv4x;
 492
 493         if(screen->is_nv4x) {
 494                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 495                         screen->use_nv4x = 0;
 496                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 497                         screen->advertise_npot = 0;
 498                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 499                         screen->advertise_blend_equation_separate = 0;
 500         }
 501
 502         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 503         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 504
 505         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 506         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 507         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 508
 509         /* We don't advertise these by default because filtering and blending doesn't work as
 510          * it should, due to several restrictions.
 511          * The only exception is fp16 on nv40.
 512          */
 513         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 514         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 515
 516         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 517
 518         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 519         if(eng3d_class == NV40_3D)
 520                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 521
 522         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 523                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 524
 525         nvfx_screen_init_resource_functions(pscreen);
 526
 527         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 528         if (ret) {
 529                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 530                 return FALSE;
 531         }
 532
 533         /* 2D engine setup */
 534         nvfx_screen_surface_init(pscreen);
 535
 536         /* Notifier for sync purposes */
 537         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 538         if (ret) {
 539                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 540                 nvfx_screen_destroy(pscreen);
 541                 return NULL;
 542         }
 543
 544         /* Query objects */
 545         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 546         {
 547                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 548                 if(!ret)
 549                         break;
 550         }
 551
 552         if (ret) {
 553                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 554                 nvfx_screen_destroy(pscreen);
 555                 return NULL;
 556         }
 557
 558         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 559         if (ret) {
 560                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 561                 nvfx_screen_destroy(pscreen);
 562                 return NULL;
 563         }
 564
 565         LIST_INITHEAD(&screen->query_list);
 566
 567         /* Vtxprog resources */
 568         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 569             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 570                 nvfx_screen_destroy(pscreen);
 571                 return NULL;
 572         }
 573
 574         BIND_RING(chan, screen->eng3d, 7);
 575
 576         /* Static eng3d initialisation */
 577         /* note that we just started using the channel, so we must have space in the pushbuffer */
 578         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 579         OUT_RING(chan, screen->sync->handle);
 580         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 581         OUT_RING(chan, chan->vram->handle);
 582         OUT_RING(chan, chan->gart->handle);
 583         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 584         OUT_RING(chan, chan->vram->handle);
 585         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 586         OUT_RING(chan, chan->vram->handle);
 587         OUT_RING(chan, chan->vram->handle);
 588         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 589         OUT_RING(chan, chan->vram->handle);
 590         OUT_RING(chan, chan->gart->handle);
 591
 592         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 593         OUT_RING(chan, 0);
 594         OUT_RING(chan, screen->query->handle);
 595
 596         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 597         OUT_RING(chan, chan->vram->handle);
 598         OUT_RING(chan, chan->vram->handle);
 599
 600         if(!screen->is_nv4x)
 601                 nv30_screen_init(screen);
 602         else
 603                 nv40_screen_init(screen);
 604
 605         return pscreen;
 606 }