src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7 #include "nouveau/nv_object.xml.h"
   8 #include "nvfx_context.h"
   9 #include "nvfx_video_context.h"
  10 #include "nvfx_screen.h"
  11 #include "nvfx_resource.h"
  12 #include "nvfx_tex.h"
  13
  14 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  15 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  16 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  17
  18 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  19 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  20 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  21
  22 static int
  23 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  24 {
  25         struct nvfx_screen *screen = nvfx_screen(pscreen);
  26
  27         switch (param) {
  28         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  29                 return 16;
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_GLSL:
  35                 return 1;
  36         case PIPE_CAP_ANISOTROPIC_FILTER:
  37                 return 1;
  38         case PIPE_CAP_POINT_SPRITE:
  39                 return 1;
  40         case PIPE_CAP_MAX_RENDER_TARGETS:
  41                 return screen->use_nv4x ? 4 : 2;
  42         case PIPE_CAP_OCCLUSION_QUERY:
  43                 return 1;
  44         case PIPE_CAP_TIMER_QUERY:
  45                 return 0;
  46         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  47                 return 1;
  48         case PIPE_CAP_TEXTURE_SWIZZLE:
  49                 return 1;
  50         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  51                 return 13;
  52         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  53                 return 10;
  54         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  57                 return !!screen->use_nv4x;
  58         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  59                 return 1;
  60         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  61                 return 0; /* We have 4 on nv40 - but unsupported currently */
  62         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  63                 return screen->advertise_blend_equation_separate;
  64         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  65                 return 16;
  66         case PIPE_CAP_INDEP_BLEND_ENABLE:
  67                 /* TODO: on nv40 we have separate color masks */
  68                 /* TODO: nv40 mrt blending is probably broken */
  69                 return 0;
  70         case PIPE_CAP_INDEP_BLEND_FUNC:
  71                 return 0;
  72         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  73                 return 0;
  74         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  75         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  76         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  77         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  78                 return 1;
  79         case PIPE_CAP_DEPTH_CLAMP:
  80                 return 0; // TODO: implement depth clamp
  81         default:
  82                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  83                 return 0;
  84         }
  85 }
  86
  87 static int
  88 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
  89 {
  90         struct nvfx_screen *screen = nvfx_screen(pscreen);
  91
  92         switch(shader) {
  93         case PIPE_SHADER_FRAGMENT:
  94                 switch(param) {
  95                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  96                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
  97                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
  98                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
  99                         return 4096;
 100                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 101                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 102                          value (nv30:0/nv40:4) ? */
 103                         return screen->use_nv4x ? 4 : 0;
 104                 case PIPE_SHADER_CAP_MAX_INPUTS:
 105                         return screen->use_nv4x ? 12 : 10;
 106                 case PIPE_SHADER_CAP_MAX_CONSTS:
 107                         return screen->use_nv4x ? 224 : 32;
 108                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 109                     return 1;
 110                 case PIPE_SHADER_CAP_MAX_TEMPS:
 111                         return 32;
 112                 case PIPE_SHADER_CAP_MAX_ADDRS:
 113                         return screen->use_nv4x ? 1 : 0;
 114                 case PIPE_SHADER_CAP_MAX_PREDS:
 115                         return 0; /* we could expose these, but nothing uses them */
 116                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 117                     return 0;
 118                 default:
 119                         break;
 120                 }
 121                 break;
 122         case PIPE_SHADER_VERTEX:
 123                 switch(param) {
 124                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 125                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 126                         return screen->use_nv4x ? 512 : 256;
 127                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 128                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 129                         return screen->use_nv4x ? 512 : 0;
 130                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 131                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 132                          value (nv30:1/nv40:4) ? */
 133                         return screen->use_nv4x ? 4 : 1;
 134                 case PIPE_SHADER_CAP_MAX_INPUTS:
 135                         return 16;
 136                 case PIPE_SHADER_CAP_MAX_CONSTS:
 137                         /* - 6 is for clip planes; Gallium should be fixed to put
 138                          * them in the vertex shader itself, so we don't need to reserve these */
 139                         return (screen->use_nv4x ? 468 : 256) - 6;
 140                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 141                             return 1;
 142                 case PIPE_SHADER_CAP_MAX_TEMPS:
 143                         return screen->use_nv4x ? 32 : 13;
 144                 case PIPE_SHADER_CAP_MAX_ADDRS:
 145                         return 2;
 146                 case PIPE_SHADER_CAP_MAX_PREDS:
 147                         return 0; /* we could expose these, but nothing uses them */
 148                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 149                         return 1;
 150                 default:
 151                         break;
 152                 }
 153                 break;
 154         default:
 155                 break;
 156         }
 157         return 0;
 158 }
 159
 160 static float
 161 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 162 {
 163         struct nvfx_screen *screen = nvfx_screen(pscreen);
 164
 165         switch (param) {
 166         case PIPE_CAP_MAX_LINE_WIDTH:
 167         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 168                 return 10.0;
 169         case PIPE_CAP_MAX_POINT_WIDTH:
 170         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 171                 return 64.0;
 172         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 173                 return screen->use_nv4x ? 16.0 : 8.0;
 174         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 175                 return 15.0;
 176         default:
 177                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 178                 return 0.0;
 179         }
 180 }
 181
 182 static boolean
 183 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 184                                      enum pipe_format format,
 185                                      enum pipe_texture_target target,
 186                                      unsigned sample_count,
 187                                      unsigned bind, unsigned geom_flags)
 188 {
 189         struct nvfx_screen *screen = nvfx_screen(pscreen);
 190
 191          if (sample_count > 1)
 192                 return FALSE;
 193
 194         if (bind & PIPE_BIND_RENDER_TARGET) {
 195                 switch (format) {
 196                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 197                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 198                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 199                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 200                 case PIPE_FORMAT_B5G6R5_UNORM:
 201                         break;
 202                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 203                         if(!screen->advertise_fp16)
 204                                 return FALSE;
 205                         break;
 206                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 207                         if(!screen->advertise_fp32)
 208                                 return FALSE;
 209                         break;
 210                 default:
 211                         return FALSE;
 212                 }
 213         }
 214
 215         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 216                 switch (format) {
 217                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 218                 case PIPE_FORMAT_X8Z24_UNORM:
 219                 case PIPE_FORMAT_Z16_UNORM:
 220                         break;
 221                 default:
 222                         return FALSE;
 223                 }
 224         }
 225
 226         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 227                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 228                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 229                         return FALSE;
 230                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 231                         return FALSE;
 232                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 233                         return FALSE;
 234                 if(screen->use_nv4x)
 235                 {
 236                         if(tf->fmt[4] < 0)
 237                                 return FALSE;
 238                 }
 239                 else
 240                 {
 241                         if(tf->fmt[0] < 0)
 242                                 return FALSE;
 243                 }
 244         }
 245
 246         // note that we do actually support everything through translate
 247         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 248                 unsigned type = nvfx_vertex_formats[format];
 249                 if(!type)
 250                         return FALSE;
 251         }
 252
 253         if (bind & PIPE_BIND_INDEX_BUFFER) {
 254                 // 8-bit indices supported, but not in hardware index buffer
 255                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 256                         return FALSE;
 257         }
 258
 259         if(bind & PIPE_BIND_STREAM_OUTPUT)
 260                 return FALSE;
 261
 262         return TRUE;
 263 }
 264
 265 static void
 266 nvfx_screen_destroy(struct pipe_screen *pscreen)
 267 {
 268         struct nvfx_screen *screen = nvfx_screen(pscreen);
 269
 270         nouveau_resource_destroy(&screen->vp_exec_heap);
 271         nouveau_resource_destroy(&screen->vp_data_heap);
 272         nouveau_resource_destroy(&screen->query_heap);
 273         nouveau_notifier_free(&screen->query);
 274         nouveau_notifier_free(&screen->sync);
 275         nouveau_grobj_free(&screen->eng3d);
 276         nvfx_screen_surface_takedown(pscreen);
 277
 278         nouveau_screen_fini(&screen->base);
 279
 280         FREE(pscreen);
 281 }
 282
 283 static void nv30_screen_init(struct nvfx_screen *screen)
 284 {
 285         struct nouveau_channel *chan = screen->base.channel;
 286         int i;
 287
 288         /* TODO: perhaps we should do some of this on nv40 too? */
 289         for (i=1; i<8; i++) {
 290                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1));
 291                 OUT_RING(chan, 0);
 292                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1));
 293                 OUT_RING(chan, 0);
 294         }
 295
 296         OUT_RING(chan, RING_3D(0x220, 1));
 297         OUT_RING(chan, 1);
 298
 299         OUT_RING(chan, RING_3D(0x03b0, 1));
 300         OUT_RING(chan, 0x00100000);
 301         OUT_RING(chan, RING_3D(0x1454, 1));
 302         OUT_RING(chan, 0);
 303         OUT_RING(chan, RING_3D(0x1d80, 1));
 304         OUT_RING(chan, 3);
 305         OUT_RING(chan, RING_3D(0x1450, 1));
 306         OUT_RING(chan, 0x00030004);
 307
 308         /* NEW */
 309         OUT_RING(chan, RING_3D(0x1e98, 1));
 310         OUT_RING(chan, 0);
 311         OUT_RING(chan, RING_3D(0x17e0, 3));
 312         OUT_RING(chan, fui(0.0));
 313         OUT_RING(chan, fui(0.0));
 314         OUT_RING(chan, fui(1.0));
 315         OUT_RING(chan, RING_3D(0x1f80, 16));
 316         for (i=0; i<16; i++) {
 317                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 318         }
 319
 320         OUT_RING(chan, RING_3D(0x120, 3));
 321         OUT_RING(chan, 0);
 322         OUT_RING(chan, 1);
 323         OUT_RING(chan, 2);
 324
 325         OUT_RING(chan, RING_3D(0x1d88, 1));
 326         OUT_RING(chan, 0x00001200);
 327
 328         OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1));
 329         OUT_RING(chan, 0);
 330
 331         OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2));
 332         OUT_RING(chan, fui(0.0));
 333         OUT_RING(chan, fui(1.0));
 334
 335         OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1));
 336         OUT_RING(chan, 0xffff0000);
 337
 338         /* enables use of vp rather than fixed-function somehow */
 339         OUT_RING(chan, RING_3D(0x1e94, 1));
 340         OUT_RING(chan, 0x13);
 341 }
 342
 343 static void nv40_screen_init(struct nvfx_screen *screen)
 344 {
 345         struct nouveau_channel *chan = screen->base.channel;
 346
 347         OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2));
 348         OUT_RING(chan, screen->base.channel->vram->handle);
 349         OUT_RING(chan, screen->base.channel->vram->handle);
 350
 351         OUT_RING(chan, RING_3D(0x1450, 1));
 352         OUT_RING(chan, 0x00000004);
 353
 354         OUT_RING(chan, RING_3D(0x1ea4, 3));
 355         OUT_RING(chan, 0x00000010);
 356         OUT_RING(chan, 0x01000100);
 357         OUT_RING(chan, 0xff800006);
 358
 359         /* vtxprog output routing */
 360         OUT_RING(chan, RING_3D(0x1fc4, 1));
 361         OUT_RING(chan, 0x06144321);
 362         OUT_RING(chan, RING_3D(0x1fc8, 2));
 363         OUT_RING(chan, 0xedcba987);
 364         OUT_RING(chan, 0x0000006f);
 365         OUT_RING(chan, RING_3D(0x1fd0, 1));
 366         OUT_RING(chan, 0x00171615);
 367         OUT_RING(chan, RING_3D(0x1fd4, 1));
 368         OUT_RING(chan, 0x001b1a19);
 369
 370         OUT_RING(chan, RING_3D(0x1ef8, 1));
 371         OUT_RING(chan, 0x0020ffff);
 372         OUT_RING(chan, RING_3D(0x1d64, 1));
 373         OUT_RING(chan, 0x01d300d4);
 374         OUT_RING(chan, RING_3D(0x1e94, 1));
 375         OUT_RING(chan, 0x00000001);
 376
 377         OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1));
 378         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 379 }
 380
 381 static unsigned
 382 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 383 {
 384         int vram_hack_default = 0;
 385         int vram_hack;
 386         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 387         // It may also depend on the specific card or the AGP/PCIe chipset.
 388         if(screen->base.device->chipset == 0x47 /* G70 */
 389                 || screen->base.device->chipset == 0x49 /* G71 */
 390                 || screen->base.device->chipset == 0x46 /* G72 */
 391                 )
 392                 vram_hack_default = 1;
 393         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 394
 395         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 396 }
 397
 398 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 399 {
 400         struct nvfx_screen* screen = chan->user_private;
 401         struct nvfx_context* nvfx = screen->cur_ctx;
 402         if(nvfx)
 403                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 404 }
 405
 406 struct pipe_screen *
 407 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 408 {
 409         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 410         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 411         struct nouveau_channel *chan;
 412         struct pipe_screen *pscreen;
 413         unsigned eng3d_class = 0;
 414         int ret, i;
 415
 416         if (!screen)
 417                 return NULL;
 418
 419         pscreen = &screen->base.base;
 420
 421         ret = nouveau_screen_init(&screen->base, dev);
 422         if (ret) {
 423                 nvfx_screen_destroy(pscreen);
 424                 return NULL;
 425         }
 426         chan = screen->base.channel;
 427         screen->cur_ctx = NULL;
 428         chan->user_private = screen;
 429         chan->flush_notify = nvfx_channel_flush_notify;
 430
 431         pscreen->winsys = ws;
 432         pscreen->destroy = nvfx_screen_destroy;
 433         pscreen->get_param = nvfx_screen_get_param;
 434         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 435         pscreen->get_paramf = nvfx_screen_get_paramf;
 436         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 437         pscreen->context_create = nvfx_create;
 438         pscreen->video_context_create = nvfx_video_create;
 439
 440         switch (dev->chipset & 0xf0) {
 441         case 0x30:
 442                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 443                         eng3d_class = NV30_3D;
 444                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 445                         eng3d_class = NV34_3D;
 446                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 447                         eng3d_class = NV35_3D;
 448                 break;
 449         case 0x40:
 450                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 451                         eng3d_class = NV40_3D;
 452                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 453                         eng3d_class = NV44_3D;
 454                 screen->is_nv4x = ~0;
 455                 break;
 456         case 0x60:
 457                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 458                         eng3d_class = NV44_3D;
 459                 screen->is_nv4x = ~0;
 460                 break;
 461         }
 462
 463         if (!eng3d_class) {
 464                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 465                 return NULL;
 466         }
 467
 468         screen->advertise_npot = !!screen->is_nv4x;
 469         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 470         screen->use_nv4x = screen->is_nv4x;
 471
 472         if(screen->is_nv4x) {
 473                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 474                         screen->use_nv4x = 0;
 475                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 476                         screen->advertise_npot = 0;
 477                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 478                         screen->advertise_blend_equation_separate = 0;
 479         }
 480
 481         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 482         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 483
 484         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 485         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 486         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 487
 488         /* We don't advertise these by default because filtering and blending doesn't work as
 489          * it should, due to several restrictions.
 490          * The only exception is fp16 on nv40.
 491          */
 492         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 493         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 494
 495         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 496
 497         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 498         if(eng3d_class == NV40_3D)
 499                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 500
 501         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 502                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 503
 504         nvfx_screen_init_resource_functions(pscreen);
 505
 506         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 507         if (ret) {
 508                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 509                 return FALSE;
 510         }
 511
 512         /* 2D engine setup */
 513         nvfx_screen_surface_init(pscreen);
 514
 515         /* Notifier for sync purposes */
 516         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 517         if (ret) {
 518                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 519                 nvfx_screen_destroy(pscreen);
 520                 return NULL;
 521         }
 522
 523         /* Query objects */
 524         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 525         {
 526                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 527                 if(!ret)
 528                         break;
 529         }
 530
 531         if (ret) {
 532                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 533                 nvfx_screen_destroy(pscreen);
 534                 return NULL;
 535         }
 536
 537         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 538         if (ret) {
 539                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 540                 nvfx_screen_destroy(pscreen);
 541                 return NULL;
 542         }
 543
 544         LIST_INITHEAD(&screen->query_list);
 545
 546         /* Vtxprog resources */
 547         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 548             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 549                 nvfx_screen_destroy(pscreen);
 550                 return NULL;
 551         }
 552
 553         BIND_RING(chan, screen->eng3d, 7);
 554
 555         /* Static eng3d initialisation */
 556         /* note that we just started using the channel, so we must have space in the pushbuffer */
 557         OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1));
 558         OUT_RING(chan, screen->sync->handle);
 559         OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2));
 560         OUT_RING(chan, chan->vram->handle);
 561         OUT_RING(chan, chan->gart->handle);
 562         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1));
 563         OUT_RING(chan, chan->vram->handle);
 564         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2));
 565         OUT_RING(chan, chan->vram->handle);
 566         OUT_RING(chan, chan->vram->handle);
 567         OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2));
 568         OUT_RING(chan, chan->vram->handle);
 569         OUT_RING(chan, chan->gart->handle);
 570
 571         OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2));
 572         OUT_RING(chan, 0);
 573         OUT_RING(chan, screen->query->handle);
 574
 575         OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2));
 576         OUT_RING(chan, chan->vram->handle);
 577         OUT_RING(chan, chan->vram->handle);
 578
 579         if(!screen->is_nv4x)
 580                 nv30_screen_init(screen);
 581         else
 582                 nv40_screen_init(screen);
 583
 584         return pscreen;
 585 }