src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6 #include "vl/vl_decoder.h"
   7 #include "vl/vl_video_buffer.h"
   8
   9 #include "nouveau/nouveau_screen.h"
  10 #include "nouveau/nv_object.xml.h"
  11 #include "nvfx_context.h"
  12 #include "nvfx_screen.h"
  13 #include "nvfx_resource.h"
  14 #include "nvfx_tex.h"
  15
  16 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  17 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  18 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  19
  20 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  21 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  22 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  23
  24 static int
  25 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  26 {
  27         struct nvfx_screen *screen = nvfx_screen(pscreen);
  28
  29         switch (param) {
  30         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  31                 return 16;
  32         case PIPE_CAP_NPOT_TEXTURES:
  33                 return screen->advertise_npot;
  34         case PIPE_CAP_TWO_SIDED_STENCIL:
  35                 return 1;
  36         case PIPE_CAP_GLSL:
  37                 return 1;
  38         case PIPE_CAP_SM3:
  39                 /* TODO: >= nv4x support Shader Model 3.0 */
  40                 return 0;
  41         case PIPE_CAP_ANISOTROPIC_FILTER:
  42                 return 1;
  43         case PIPE_CAP_POINT_SPRITE:
  44                 return 1;
  45         case PIPE_CAP_MAX_RENDER_TARGETS:
  46                 return screen->use_nv4x ? 4 : 1;
  47         case PIPE_CAP_OCCLUSION_QUERY:
  48                 return 1;
  49         case PIPE_CAP_TIMER_QUERY:
  50                 return 0;
  51         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  52                 return 1;
  53         case PIPE_CAP_TEXTURE_SWIZZLE:
  54                 return 1;
  55         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  56                 return 13;
  57         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  58                 return 10;
  59         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  60                 return 13;
  61         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  62                 return !!screen->use_nv4x;
  63         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  64                 return 1;
  65         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  66                 return 0; /* We have 4 on nv40 - but unsupported currently */
  67         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  68                 return screen->advertise_blend_equation_separate;
  69         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  70                 return 16;
  71         case PIPE_CAP_INDEP_BLEND_ENABLE:
  72                 /* TODO: on nv40 we have separate color masks */
  73                 /* TODO: nv40 mrt blending is probably broken */
  74                 return 0;
  75         case PIPE_CAP_INDEP_BLEND_FUNC:
  76                 return 0;
  77         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  78                 return 0;
  79         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  80         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  81         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  82         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  83                 return 1;
  84         case PIPE_CAP_DEPTH_CLAMP:
  85                 return 0; // TODO: implement depth clamp
  86         case PIPE_CAP_PRIMITIVE_RESTART:
  87                 return 0; // TODO: implement primitive restart
  88         case PIPE_CAP_ARRAY_TEXTURES:
  89         case PIPE_CAP_TGSI_INSTANCEID:
  90         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  91         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  92         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  93         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  94         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  95                 return 0;
  96         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  97                 return 0;
  98         default:
  99                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
 100                 return 0;
 101         }
 102 }
 103
 104 static int
 105 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 106 {
 107         struct nvfx_screen *screen = nvfx_screen(pscreen);
 108
 109         switch(shader) {
 110         case PIPE_SHADER_FRAGMENT:
 111                 switch(param) {
 112                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 113                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 114                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 115                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 116                         return 4096;
 117                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 118                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 119                          value (nv30:0/nv40:4) ? */
 120                         return screen->use_nv4x ? 4 : 0;
 121                 case PIPE_SHADER_CAP_MAX_INPUTS:
 122                         return screen->use_nv4x ? 12 : 10;
 123                 case PIPE_SHADER_CAP_MAX_CONSTS:
 124                         return screen->use_nv4x ? 224 : 32;
 125                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 126                     return 1;
 127                 case PIPE_SHADER_CAP_MAX_TEMPS:
 128                         return 32;
 129                 case PIPE_SHADER_CAP_MAX_ADDRS:
 130                         return screen->use_nv4x ? 1 : 0;
 131                 case PIPE_SHADER_CAP_MAX_PREDS:
 132                         return 0; /* we could expose these, but nothing uses them */
 133                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 134                     return 0;
 135                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 136                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 137                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 138                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 139                         return 0;
 140                 case PIPE_SHADER_CAP_SUBROUTINES:
 141                         return screen->use_nv4x ? 1 : 0;
 142                 default:
 143                         break;
 144                 }
 145                 break;
 146         case PIPE_SHADER_VERTEX:
 147                 switch(param) {
 148                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 149                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 150                         return screen->use_nv4x ? 512 : 256;
 151                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 152                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 153                         return screen->use_nv4x ? 512 : 0;
 154                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 155                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 156                          value (nv30:1/nv40:4) ? */
 157                         return screen->use_nv4x ? 4 : 1;
 158                 case PIPE_SHADER_CAP_MAX_INPUTS:
 159                         return 16;
 160                 case PIPE_SHADER_CAP_MAX_CONSTS:
 161                         /* - 6 is for clip planes; Gallium should be fixed to put
 162                          * them in the vertex shader itself, so we don't need to reserve these */
 163                         return (screen->use_nv4x ? 468 : 256) - 6;
 164                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 165                             return 1;
 166                 case PIPE_SHADER_CAP_MAX_TEMPS:
 167                         return screen->use_nv4x ? 32 : 13;
 168                 case PIPE_SHADER_CAP_MAX_ADDRS:
 169                         return 2;
 170                 case PIPE_SHADER_CAP_MAX_PREDS:
 171                         return 0; /* we could expose these, but nothing uses them */
 172                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 173                         return 1;
 174                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 175                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 176                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 177                         return 0;
 178                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 179                         return 1;
 180                 case PIPE_SHADER_CAP_SUBROUTINES:
 181                         return 1;
 182                 default:
 183                         break;
 184                 }
 185                 break;
 186         default:
 187                 break;
 188         }
 189         return 0;
 190 }
 191
 192 static float
 193 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 194 {
 195         struct nvfx_screen *screen = nvfx_screen(pscreen);
 196
 197         switch (param) {
 198         case PIPE_CAP_MAX_LINE_WIDTH:
 199         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 200                 return 10.0;
 201         case PIPE_CAP_MAX_POINT_WIDTH:
 202         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 203                 return 64.0;
 204         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 205                 return screen->use_nv4x ? 16.0 : 8.0;
 206         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 207                 return 15.0;
 208         default:
 209                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 210                 return 0.0;
 211         }
 212 }
 213
 214 static int
 215 nvfx_screen_get_video_param(struct pipe_screen *screen,
 216                                 enum pipe_video_profile profile,
 217                                 enum pipe_video_cap param)
 218 {
 219         switch (param) {
 220         case PIPE_VIDEO_CAP_SUPPORTED:
 221                 return vl_profile_supported(screen, profile);
 222         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 223                 return 0;
 224         case PIPE_VIDEO_CAP_MAX_WIDTH:
 225         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 226                 return vl_video_buffer_max_size(screen);
 227         default:
 228                 return 0;
 229         }
 230 }
 231
 232 static boolean
 233 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 234                                      enum pipe_format format,
 235                                      enum pipe_texture_target target,
 236                                      unsigned sample_count,
 237                                      unsigned bind)
 238 {
 239         struct nvfx_screen *screen = nvfx_screen(pscreen);
 240
 241         if (!util_format_is_supported(format, bind))
 242                 return FALSE;
 243
 244          if (sample_count > 1)
 245                 return FALSE;
 246
 247         if (bind & PIPE_BIND_RENDER_TARGET) {
 248                 switch (format) {
 249                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 250                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 251                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 252                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 253                 case PIPE_FORMAT_B5G6R5_UNORM:
 254                         break;
 255                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 256                         if(!screen->advertise_fp16)
 257                                 return FALSE;
 258                         break;
 259                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 260                         if(!screen->advertise_fp32)
 261                                 return FALSE;
 262                         break;
 263                 default:
 264                         return FALSE;
 265                 }
 266         }
 267
 268         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 269                 switch (format) {
 270                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 271                 case PIPE_FORMAT_X8Z24_UNORM:
 272                 case PIPE_FORMAT_Z16_UNORM:
 273                         break;
 274                 default:
 275                         return FALSE;
 276                 }
 277         }
 278
 279         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 280                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 281                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 282                         return FALSE;
 283                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 284                         return FALSE;
 285                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 286                         return FALSE;
 287                 if(screen->use_nv4x)
 288                 {
 289                         if(tf->fmt[4] < 0)
 290                                 return FALSE;
 291                 }
 292                 else
 293                 {
 294                         if(tf->fmt[0] < 0)
 295                                 return FALSE;
 296                 }
 297         }
 298
 299         // note that we do actually support everything through translate
 300         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 301                 unsigned type = nvfx_vertex_formats[format];
 302                 if(!type)
 303                         return FALSE;
 304         }
 305
 306         if (bind & PIPE_BIND_INDEX_BUFFER) {
 307                 // 8-bit indices supported, but not in hardware index buffer
 308                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 309                         return FALSE;
 310         }
 311
 312         if(bind & PIPE_BIND_STREAM_OUTPUT)
 313                 return FALSE;
 314
 315         return TRUE;
 316 }
 317
 318 static void
 319 nvfx_screen_destroy(struct pipe_screen *pscreen)
 320 {
 321         struct nvfx_screen *screen = nvfx_screen(pscreen);
 322
 323         nouveau_resource_destroy(&screen->vp_exec_heap);
 324         nouveau_resource_destroy(&screen->vp_data_heap);
 325         nouveau_resource_destroy(&screen->query_heap);
 326         nouveau_notifier_free(&screen->query);
 327         nouveau_notifier_free(&screen->sync);
 328         nouveau_grobj_free(&screen->eng3d);
 329         nvfx_screen_surface_takedown(pscreen);
 330         nouveau_bo_ref(NULL, &screen->fence);
 331
 332         nouveau_screen_fini(&screen->base);
 333
 334         FREE(pscreen);
 335 }
 336
 337 static void nv30_screen_init(struct nvfx_screen *screen)
 338 {
 339         struct nouveau_channel *chan = screen->base.channel;
 340         struct nouveau_grobj *eng3d = screen->eng3d;
 341         int i;
 342
 343         /* TODO: perhaps we should do some of this on nv40 too? */
 344         for (i=1; i<8; i++) {
 345                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 346                 OUT_RING(chan, 0);
 347                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 348                 OUT_RING(chan, 0);
 349         }
 350
 351         BEGIN_RING(chan, eng3d, 0x220, 1);
 352         OUT_RING(chan, 1);
 353
 354         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 355         OUT_RING(chan, 0x00100000);
 356         BEGIN_RING(chan, eng3d, 0x1454, 1);
 357         OUT_RING(chan, 0);
 358         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 359         OUT_RING(chan, 3);
 360         BEGIN_RING(chan, eng3d, 0x1450, 1);
 361         OUT_RING(chan, 0x00030004);
 362
 363         /* NEW */
 364         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 365         OUT_RING(chan, 0);
 366         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 367         OUT_RING(chan, fui(0.0));
 368         OUT_RING(chan, fui(0.0));
 369         OUT_RING(chan, fui(1.0));
 370         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 371         for (i=0; i<16; i++) {
 372                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 373         }
 374
 375         BEGIN_RING(chan, eng3d, 0x120, 3);
 376         OUT_RING(chan, 0);
 377         OUT_RING(chan, 1);
 378         OUT_RING(chan, 2);
 379
 380         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 381         OUT_RING(chan, 0x00001200);
 382
 383         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 384         OUT_RING(chan, 0);
 385
 386         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 387         OUT_RING(chan, fui(0.0));
 388         OUT_RING(chan, fui(1.0));
 389
 390         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 391         OUT_RING(chan, 0xffff0000);
 392
 393         /* enables use of vp rather than fixed-function somehow */
 394         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 395         OUT_RING(chan, 0x13);
 396 }
 397
 398 static void nv40_screen_init(struct nvfx_screen *screen)
 399 {
 400         struct nouveau_channel *chan = screen->base.channel;
 401         struct nouveau_grobj *eng3d = screen->eng3d;
 402
 403         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 404         OUT_RING(chan, screen->base.channel->vram->handle);
 405         OUT_RING(chan, screen->base.channel->vram->handle);
 406
 407         BEGIN_RING(chan, eng3d, 0x1450, 1);
 408         OUT_RING(chan, 0x00000004);
 409
 410         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 411         OUT_RING(chan, 0x00000010);
 412         OUT_RING(chan, 0x01000100);
 413         OUT_RING(chan, 0xff800006);
 414
 415         /* vtxprog output routing */
 416         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 417         OUT_RING(chan, 0x06144321);
 418         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 419         OUT_RING(chan, 0xedcba987);
 420         OUT_RING(chan, 0x0000006f);
 421         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 422         OUT_RING(chan, 0x00171615);
 423         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 424         OUT_RING(chan, 0x001b1a19);
 425
 426         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 427         OUT_RING(chan, 0x0020ffff);
 428         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 429         OUT_RING(chan, 0x01d300d4);
 430         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 431         OUT_RING(chan, 0x00000001);
 432
 433         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 434         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 435 }
 436
 437 static unsigned
 438 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 439 {
 440         int vram_hack_default = 0;
 441         int vram_hack;
 442         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 443         // It may also depend on the specific card or the AGP/PCIe chipset.
 444         if(screen->base.device->chipset == 0x47 /* G70 */
 445                 || screen->base.device->chipset == 0x49 /* G71 */
 446                 || screen->base.device->chipset == 0x46 /* G72 */
 447                 )
 448                 vram_hack_default = 1;
 449         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 450
 451         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 452 }
 453
 454 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 455 {
 456         struct nvfx_screen* screen = chan->user_private;
 457         struct nvfx_context* nvfx = screen->cur_ctx;
 458         if(nvfx)
 459                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 460 }
 461
 462 struct pipe_screen *
 463 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 464 {
 465         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 466         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 467         struct nouveau_channel *chan;
 468         struct pipe_screen *pscreen;
 469         unsigned eng3d_class = 0;
 470         int ret, i;
 471
 472         if (!screen)
 473                 return NULL;
 474
 475         pscreen = &screen->base.base;
 476
 477         ret = nouveau_screen_init(&screen->base, dev);
 478         if (ret) {
 479                 nvfx_screen_destroy(pscreen);
 480                 return NULL;
 481         }
 482         chan = screen->base.channel;
 483         screen->cur_ctx = NULL;
 484         chan->user_private = screen;
 485         chan->flush_notify = nvfx_channel_flush_notify;
 486
 487         pscreen->winsys = ws;
 488         pscreen->destroy = nvfx_screen_destroy;
 489         pscreen->get_param = nvfx_screen_get_param;
 490         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 491         pscreen->get_paramf = nvfx_screen_get_paramf;
 492         pscreen->get_video_param = nvfx_screen_get_video_param;
 493         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 494         pscreen->is_video_format_supported = vl_video_buffer_is_format_supported;
 495         pscreen->context_create = nvfx_create;
 496
 497         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 4096, &screen->fence);
 498         if (ret) {
 499                 nvfx_screen_destroy(pscreen);
 500                 return NULL;
 501         }
 502
 503         switch (dev->chipset & 0xf0) {
 504         case 0x30:
 505                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 506                         eng3d_class = NV30_3D;
 507                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 508                         eng3d_class = NV34_3D;
 509                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 510                         eng3d_class = NV35_3D;
 511                 break;
 512         case 0x40:
 513                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 514                         eng3d_class = NV40_3D;
 515                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 516                         eng3d_class = NV44_3D;
 517                 screen->is_nv4x = ~0;
 518                 break;
 519         case 0x60:
 520                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 521                         eng3d_class = NV44_3D;
 522                 screen->is_nv4x = ~0;
 523                 break;
 524         }
 525
 526         if (!eng3d_class) {
 527                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 528                 return NULL;
 529         }
 530
 531         screen->advertise_npot = !!screen->is_nv4x;
 532         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 533         screen->use_nv4x = screen->is_nv4x;
 534
 535         if(screen->is_nv4x) {
 536                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 537                         screen->use_nv4x = 0;
 538                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 539                         screen->advertise_npot = 0;
 540                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 541                         screen->advertise_blend_equation_separate = 0;
 542         }
 543
 544         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 545         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 546
 547         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 548         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 549         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 550
 551         /* We don't advertise these by default because filtering and blending doesn't work as
 552          * it should, due to several restrictions.
 553          * The only exception is fp16 on nv40.
 554          */
 555         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 556         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 557
 558         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 559
 560         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 561         if(eng3d_class == NV40_3D)
 562                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 563
 564         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 565                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 566
 567         nvfx_screen_init_resource_functions(pscreen);
 568
 569         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 570         if (ret) {
 571                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 572                 return FALSE;
 573         }
 574
 575         /* 2D engine setup */
 576         nvfx_screen_surface_init(pscreen);
 577
 578         /* Notifier for sync purposes */
 579         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 580         if (ret) {
 581                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 582                 nvfx_screen_destroy(pscreen);
 583                 return NULL;
 584         }
 585
 586         /* Query objects */
 587         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 588         {
 589                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 590                 if(!ret)
 591                         break;
 592         }
 593
 594         if (ret) {
 595                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 596                 nvfx_screen_destroy(pscreen);
 597                 return NULL;
 598         }
 599
 600         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 601         if (ret) {
 602                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 603                 nvfx_screen_destroy(pscreen);
 604                 return NULL;
 605         }
 606
 607         LIST_INITHEAD(&screen->query_list);
 608
 609         /* Vtxprog resources */
 610         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 611             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 612                 nvfx_screen_destroy(pscreen);
 613                 return NULL;
 614         }
 615
 616         BIND_RING(chan, screen->eng3d, 7);
 617
 618         /* Static eng3d initialisation */
 619         /* note that we just started using the channel, so we must have space in the pushbuffer */
 620         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 621         OUT_RING(chan, screen->sync->handle);
 622         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 623         OUT_RING(chan, chan->vram->handle);
 624         OUT_RING(chan, chan->gart->handle);
 625         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 626         OUT_RING(chan, chan->vram->handle);
 627         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 628         OUT_RING(chan, chan->vram->handle);
 629         OUT_RING(chan, chan->vram->handle);
 630         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 631         OUT_RING(chan, chan->vram->handle);
 632         OUT_RING(chan, chan->gart->handle);
 633
 634         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 635         OUT_RING(chan, 0);
 636         OUT_RING(chan, screen->query->handle);
 637
 638         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 639         OUT_RING(chan, chan->vram->handle);
 640         OUT_RING(chan, chan->vram->handle);
 641
 642         if(!screen->is_nv4x)
 643                 nv30_screen_init(screen);
 644         else
 645                 nv40_screen_init(screen);
 646
 647         return pscreen;
 648 }