src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_simple_screen.h"
   4
   5 #include "nouveau/nouveau_screen.h"
   6
   7 #include "nvfx_context.h"
   8 #include "nvfx_screen.h"
   9 #include "nvfx_resource.h"
  10
  11 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  12 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  13 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  14
  15 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  16 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  17 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  18 * with same number of bits everywhere.
  19 */
  20 struct nouveau_winsys {
  21         struct pipe_winsys base;
  22
  23         struct pipe_screen *pscreen;
  24
  25         struct pipe_surface *front;
  26 };
  27 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  28 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  29 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  30
  31 static int
  32 nvfx_screen_get_param(struct pipe_screen *pscreen, int param)
  33 {
  34         struct nvfx_screen *screen = nvfx_screen(pscreen);
  35
  36         switch (param) {
  37         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  38                 /* TODO: check this */
  39                 return screen->is_nv4x ? 16 : 8;
  40         case PIPE_CAP_NPOT_TEXTURES:
  41                 return !!screen->is_nv4x;
  42         case PIPE_CAP_TWO_SIDED_STENCIL:
  43                 return 1;
  44         case PIPE_CAP_GLSL:
  45                 return 0;
  46         case PIPE_CAP_ANISOTROPIC_FILTER:
  47                 return 1;
  48         case PIPE_CAP_POINT_SPRITE:
  49                 return 1;
  50         case PIPE_CAP_MAX_RENDER_TARGETS:
  51                 return screen->is_nv4x ? 4 : 2;
  52         case PIPE_CAP_OCCLUSION_QUERY:
  53                 return 1;
  54         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  55                 return 1;
  56         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  57                 return 13;
  58         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  59                 return 10;
  60         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  61                 return 13;
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63                 return !!screen->is_nv4x;
  64         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  65                 return 1;
  66         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  67                 return 0; /* We have 4 on nv40 - but unsupported currently */
  68         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  69                 return 0;
  70         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  71                 return !!screen->is_nv4x;
  72         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  73                 return 16;
  74         case PIPE_CAP_INDEP_BLEND_ENABLE:
  75                 /* TODO: on nv40 we have separate color masks */
  76                 /* TODO: nv40 mrt blending is probably broken */
  77                 return 0;
  78         case PIPE_CAP_INDEP_BLEND_FUNC:
  79                 return 0;
  80         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  81         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  82                 return 1;
  83         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  84         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  85                 return 0;
  86         default:
  87                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  88                 return 0;
  89         }
  90 }
  91
  92 static float
  93 nvfx_screen_get_paramf(struct pipe_screen *pscreen, int param)
  94 {
  95         struct nvfx_screen *screen = nvfx_screen(pscreen);
  96
  97         switch (param) {
  98         case PIPE_CAP_MAX_LINE_WIDTH:
  99         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 100                 return 10.0;
 101         case PIPE_CAP_MAX_POINT_WIDTH:
 102         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 103                 return 64.0;
 104         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 105                 return screen->is_nv4x ? 16.0 : 8.0;
 106         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 107                 return screen->is_nv4x ? 16.0 : 4.0;
 108         default:
 109                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 110                 return 0.0;
 111         }
 112 }
 113
 114 static boolean
 115 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 116                                      enum pipe_format format,
 117                                      enum pipe_texture_target target,
 118                                      unsigned tex_usage, unsigned geom_flags)
 119 {
 120         struct nvfx_screen *screen = nvfx_screen(pscreen);
 121         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 122
 123         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
 124                 switch (format) {
 125                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 126                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 127                 case PIPE_FORMAT_B5G6R5_UNORM:
 128                         return TRUE;
 129                 default:
 130                         break;
 131                 }
 132         } else
 133         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 134                 switch (format) {
 135                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 136                 case PIPE_FORMAT_X8Z24_UNORM:
 137                         return TRUE;
 138                 case PIPE_FORMAT_Z16_UNORM:
 139                         /* TODO: this nv30 limitation probably does not exist */
 140                         if (!screen->is_nv4x && front)
 141                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 142                         return TRUE;
 143                 default:
 144                         break;
 145                 }
 146         } else {
 147                 switch (format) {
 148                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 149                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 150                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 151                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 152                 case PIPE_FORMAT_B5G6R5_UNORM:
 153                 case PIPE_FORMAT_L8_UNORM:
 154                 case PIPE_FORMAT_A8_UNORM:
 155                 case PIPE_FORMAT_I8_UNORM:
 156                 case PIPE_FORMAT_L8A8_UNORM:
 157                 case PIPE_FORMAT_Z16_UNORM:
 158                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 159                 case PIPE_FORMAT_DXT1_RGB:
 160                 case PIPE_FORMAT_DXT1_RGBA:
 161                 case PIPE_FORMAT_DXT3_RGBA:
 162                 case PIPE_FORMAT_DXT5_RGBA:
 163                         return TRUE;
 164                 /* TODO: does nv30 support this? */
 165                 case PIPE_FORMAT_R16_SNORM:
 166                         return !!screen->is_nv4x;
 167                 default:
 168                         break;
 169                 }
 170         }
 171
 172         return FALSE;
 173 }
 174
 175
 176 static void
 177 nvfx_screen_destroy(struct pipe_screen *pscreen)
 178 {
 179         struct nvfx_screen *screen = nvfx_screen(pscreen);
 180
 181         nouveau_resource_destroy(&screen->vp_exec_heap);
 182         nouveau_resource_destroy(&screen->vp_data_heap);
 183         nouveau_resource_destroy(&screen->query_heap);
 184         nouveau_notifier_free(&screen->query);
 185         nouveau_notifier_free(&screen->sync);
 186         nouveau_grobj_free(&screen->eng3d);
 187         nv04_surface_2d_takedown(&screen->eng2d);
 188
 189         nouveau_screen_fini(&screen->base);
 190
 191         FREE(pscreen);
 192 }
 193
 194 static void nv30_screen_init(struct nvfx_screen *screen)
 195 {
 196         struct nouveau_channel *chan = screen->base.channel;
 197         int i;
 198
 199         /* TODO: perhaps we should do some of this on nv40 too? */
 200         for (i=1; i<8; i++) {
 201                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1));
 202                 OUT_RING(chan, 0);
 203                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1));
 204                 OUT_RING(chan, 0);
 205         }
 206
 207         OUT_RING(chan, RING_3D(0x220, 1));
 208         OUT_RING(chan, 1);
 209
 210         OUT_RING(chan, RING_3D(0x03b0, 1));
 211         OUT_RING(chan, 0x00100000);
 212         OUT_RING(chan, RING_3D(0x1454, 1));
 213         OUT_RING(chan, 0);
 214         OUT_RING(chan, RING_3D(0x1d80, 1));
 215         OUT_RING(chan, 3);
 216         OUT_RING(chan, RING_3D(0x1450, 1));
 217         OUT_RING(chan, 0x00030004);
 218
 219         /* NEW */
 220         OUT_RING(chan, RING_3D(0x1e98, 1));
 221         OUT_RING(chan, 0);
 222         OUT_RING(chan, RING_3D(0x17e0, 3));
 223         OUT_RING(chan, fui(0.0));
 224         OUT_RING(chan, fui(0.0));
 225         OUT_RING(chan, fui(1.0));
 226         OUT_RING(chan, RING_3D(0x1f80, 16));
 227         for (i=0; i<16; i++) {
 228                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 229         }
 230
 231         OUT_RING(chan, RING_3D(0x120, 3));
 232         OUT_RING(chan, 0);
 233         OUT_RING(chan, 1);
 234         OUT_RING(chan, 2);
 235
 236         OUT_RING(chan, RING_3D(0x1d88, 1));
 237         OUT_RING(chan, 0x00001200);
 238
 239         OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1));
 240         OUT_RING(chan, 0);
 241
 242         OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2));
 243         OUT_RING(chan, fui(0.0));
 244         OUT_RING(chan, fui(1.0));
 245
 246         OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1));
 247         OUT_RING(chan, 0xffff0000);
 248
 249         /* enables use of vp rather than fixed-function somehow */
 250         OUT_RING(chan, RING_3D(0x1e94, 1));
 251         OUT_RING(chan, 0x13);
 252 }
 253
 254 static void nv40_screen_init(struct nvfx_screen *screen)
 255 {
 256         struct nouveau_channel *chan = screen->base.channel;
 257
 258         OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2));
 259         OUT_RING(chan, screen->base.channel->vram->handle);
 260         OUT_RING(chan, screen->base.channel->vram->handle);
 261
 262         OUT_RING(chan, RING_3D(0x1ea4, 3));
 263         OUT_RING(chan, 0x00000010);
 264         OUT_RING(chan, 0x01000100);
 265         OUT_RING(chan, 0xff800006);
 266
 267         /* vtxprog output routing */
 268         OUT_RING(chan, RING_3D(0x1fc4, 1));
 269         OUT_RING(chan, 0x06144321);
 270         OUT_RING(chan, RING_3D(0x1fc8, 2));
 271         OUT_RING(chan, 0xedcba987);
 272         OUT_RING(chan, 0x00000021);
 273         OUT_RING(chan, RING_3D(0x1fd0, 1));
 274         OUT_RING(chan, 0x00171615);
 275         OUT_RING(chan, RING_3D(0x1fd4, 1));
 276         OUT_RING(chan, 0x001b1a19);
 277
 278         OUT_RING(chan, RING_3D(0x1ef8, 1));
 279         OUT_RING(chan, 0x0020ffff);
 280         OUT_RING(chan, RING_3D(0x1d64, 1));
 281         OUT_RING(chan, 0x00d30000);
 282         OUT_RING(chan, RING_3D(0x1e94, 1));
 283         OUT_RING(chan, 0x00000001);
 284 }
 285
 286 static unsigned
 287 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 288 {
 289         int vram_hack_default = 0;
 290         int vram_hack;
 291         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 292         // It may also depend on the specific card or the AGP/PCIe chipset.
 293         if(screen->base.device->chipset == 0x47 /* G70 */
 294                 || screen->base.device->chipset == 0x49 /* G71 */
 295                 || screen->base.device->chipset == 0x46 /* G72 */
 296                 )
 297                 vram_hack_default = 1;
 298         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 299
 300 #ifdef DEBUG
 301         if(!vram_hack)
 302         {
 303                 fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
 304                         "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
 305         }
 306         else
 307         {
 308                 fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n"
 309                         "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
 310         }
 311 #endif
 312
 313         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 314 }
 315
 316 struct pipe_screen *
 317 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 318 {
 319         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 320         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 321         struct nouveau_channel *chan;
 322         struct pipe_screen *pscreen;
 323         unsigned eng3d_class = 0;
 324         int ret, i;
 325
 326         if (!screen)
 327                 return NULL;
 328
 329         pscreen = &screen->base.base;
 330
 331         ret = nouveau_screen_init(&screen->base, dev);
 332         if (ret) {
 333                 nvfx_screen_destroy(pscreen);
 334                 return NULL;
 335         }
 336         chan = screen->base.channel;
 337
 338         pscreen->winsys = ws;
 339         pscreen->destroy = nvfx_screen_destroy;
 340         pscreen->get_param = nvfx_screen_get_param;
 341         pscreen->get_paramf = nvfx_screen_get_paramf;
 342         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 343         pscreen->context_create = nvfx_create;
 344
 345         switch (dev->chipset & 0xf0) {
 346         case 0x30:
 347                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 348                         eng3d_class = 0x0397;
 349                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 350                         eng3d_class = 0x0697;
 351                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 352                         eng3d_class = 0x0497;
 353                 break;
 354         case 0x40:
 355                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 356                         eng3d_class = NV40TCL;
 357                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 358                         eng3d_class = NV44TCL;
 359                 screen->is_nv4x = ~0;
 360                 break;
 361         case 0x60:
 362                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 363                         eng3d_class = NV44TCL;
 364                 screen->is_nv4x = ~0;
 365                 break;
 366         }
 367
 368         if (!eng3d_class) {
 369                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 370                 return NULL;
 371         }
 372
 373         screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE);
 374
 375         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 376
 377         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 378         if(eng3d_class == NV40TCL)
 379                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 380
 381         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 382                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 383
 384         nvfx_screen_init_resource_functions(pscreen);
 385
 386         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 387         if (ret) {
 388                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 389                 return FALSE;
 390         }
 391
 392         /* 2D engine setup */
 393         screen->eng2d = nv04_surface_2d_init(&screen->base);
 394         screen->eng2d->buf = nvfx_surface_buffer;
 395
 396         /* Notifier for sync purposes */
 397         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 398         if (ret) {
 399                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 400                 nvfx_screen_destroy(pscreen);
 401                 return NULL;
 402         }
 403
 404         /* Query objects */
 405         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 406         {
 407                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 408                 if(!ret)
 409                         break;
 410         }
 411
 412         if (ret) {
 413                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 414                 nvfx_screen_destroy(pscreen);
 415                 return NULL;
 416         }
 417
 418         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 419         if (ret) {
 420                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 421                 nvfx_screen_destroy(pscreen);
 422                 return NULL;
 423         }
 424
 425         LIST_INITHEAD(&screen->query_list);
 426
 427         /* Vtxprog resources */
 428         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 429             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 430                 nvfx_screen_destroy(pscreen);
 431                 return NULL;
 432         }
 433
 434         BIND_RING(chan, screen->eng3d, 7);
 435
 436         /* Static eng3d initialisation */
 437         /* note that we just started using the channel, so we must have space in the pushbuffer */
 438         OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1));
 439         OUT_RING(chan, screen->sync->handle);
 440         OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2));
 441         OUT_RING(chan, chan->vram->handle);
 442         OUT_RING(chan, chan->gart->handle);
 443         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
 444         OUT_RING(chan, chan->vram->handle);
 445         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2));
 446         OUT_RING(chan, chan->vram->handle);
 447         OUT_RING(chan, chan->vram->handle);
 448         OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2));
 449         OUT_RING(chan, chan->vram->handle);
 450         OUT_RING(chan, chan->gart->handle);
 451
 452         OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2));
 453         OUT_RING(chan, 0);
 454         OUT_RING(chan, screen->query->handle);
 455
 456         OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2));
 457         OUT_RING(chan, chan->vram->handle);
 458         OUT_RING(chan, chan->vram->handle);
 459
 460         if(!screen->is_nv4x)
 461                 nv30_screen_init(screen);
 462         else
 463                 nv40_screen_init(screen);
 464
 465         return pscreen;
 466 }