src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_simple_screen.h"
   4
   5 #include "nouveau/nouveau_screen.h"
   6
   7 #include "nvfx_context.h"
   8 #include "nvfx_video_context.h"
   9 #include "nvfx_screen.h"
  10 #include "nvfx_resource.h"
  11
  12 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  13 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  14 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  15
  16 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  17 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  18 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  19 * with same number of bits everywhere.
  20 */
  21 struct nouveau_winsys {
  22         struct pipe_winsys base;
  23
  24         struct pipe_screen *pscreen;
  25
  26         struct pipe_surface *front;
  27 };
  28 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  29 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  30 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  31
  32 static int
  33 nvfx_screen_get_param(struct pipe_screen *pscreen, int param)
  34 {
  35         struct nvfx_screen *screen = nvfx_screen(pscreen);
  36
  37         switch (param) {
  38         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  39                 /* TODO: check this */
  40                 return screen->is_nv4x ? 16 : 8;
  41         case PIPE_CAP_NPOT_TEXTURES:
  42                 return !!screen->is_nv4x;
  43         case PIPE_CAP_TWO_SIDED_STENCIL:
  44                 return 1;
  45         case PIPE_CAP_GLSL:
  46                 return 0;
  47         case PIPE_CAP_ANISOTROPIC_FILTER:
  48                 return 1;
  49         case PIPE_CAP_POINT_SPRITE:
  50                 return 1;
  51         case PIPE_CAP_MAX_RENDER_TARGETS:
  52                 return screen->is_nv4x ? 4 : 2;
  53         case PIPE_CAP_OCCLUSION_QUERY:
  54                 return 1;
  55         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  56                 return 1;
  57         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58                 return 13;
  59         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60                 return 10;
  61         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62                 return 13;
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  64                 return !!screen->is_nv4x;
  65         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  66                 return 1;
  67         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  68                 return 0; /* We have 4 on nv40 - but unsupported currently */
  69         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  70                 return 0;
  71         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  72                 return !!screen->is_nv4x;
  73         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  74                 return 16;
  75         case PIPE_CAP_INDEP_BLEND_ENABLE:
  76                 /* TODO: on nv40 we have separate color masks */
  77                 /* TODO: nv40 mrt blending is probably broken */
  78                 return 0;
  79         case PIPE_CAP_INDEP_BLEND_FUNC:
  80                 return 0;
  81         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  82         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  83                 return 1;
  84         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  85         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  86                 return 0;
  87         default:
  88                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  89                 return 0;
  90         }
  91 }
  92
  93 static float
  94 nvfx_screen_get_paramf(struct pipe_screen *pscreen, int param)
  95 {
  96         struct nvfx_screen *screen = nvfx_screen(pscreen);
  97
  98         switch (param) {
  99         case PIPE_CAP_MAX_LINE_WIDTH:
 100         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 101                 return 10.0;
 102         case PIPE_CAP_MAX_POINT_WIDTH:
 103         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 104                 return 64.0;
 105         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 106                 return screen->is_nv4x ? 16.0 : 8.0;
 107         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 108                 return screen->is_nv4x ? 16.0 : 4.0;
 109         default:
 110                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 111                 return 0.0;
 112         }
 113 }
 114
 115 static boolean
 116 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 117                                      enum pipe_format format,
 118                                      enum pipe_texture_target target,
 119                                      unsigned tex_usage, unsigned geom_flags)
 120 {
 121         struct nvfx_screen *screen = nvfx_screen(pscreen);
 122         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 123
 124         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
 125                 switch (format) {
 126                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 127                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 128                 case PIPE_FORMAT_B5G6R5_UNORM:
 129                         return TRUE;
 130                 default:
 131                         break;
 132                 }
 133         } else
 134         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 135                 switch (format) {
 136                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 137                 case PIPE_FORMAT_X8Z24_UNORM:
 138                         return TRUE;
 139                 case PIPE_FORMAT_Z16_UNORM:
 140                         /* TODO: this nv30 limitation probably does not exist */
 141                         if (!screen->is_nv4x && front)
 142                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 143                         return TRUE;
 144                 default:
 145                         break;
 146                 }
 147         } else {
 148                 switch (format) {
 149                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 150                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 151                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 152                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 153                 case PIPE_FORMAT_B5G6R5_UNORM:
 154                 case PIPE_FORMAT_L8_UNORM:
 155                 case PIPE_FORMAT_A8_UNORM:
 156                 case PIPE_FORMAT_I8_UNORM:
 157                 case PIPE_FORMAT_L8A8_UNORM:
 158                 case PIPE_FORMAT_Z16_UNORM:
 159                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 160                 case PIPE_FORMAT_DXT1_RGB:
 161                 case PIPE_FORMAT_DXT1_RGBA:
 162                 case PIPE_FORMAT_DXT3_RGBA:
 163                 case PIPE_FORMAT_DXT5_RGBA:
 164                         return TRUE;
 165                 /* TODO: does nv30 support this? */
 166                 case PIPE_FORMAT_R16_SNORM:
 167                         return !!screen->is_nv4x;
 168                 default:
 169                         break;
 170                 }
 171         }
 172
 173         return FALSE;
 174 }
 175
 176
 177 static void
 178 nvfx_screen_destroy(struct pipe_screen *pscreen)
 179 {
 180         struct nvfx_screen *screen = nvfx_screen(pscreen);
 181
 182         nouveau_resource_destroy(&screen->vp_exec_heap);
 183         nouveau_resource_destroy(&screen->vp_data_heap);
 184         nouveau_resource_destroy(&screen->query_heap);
 185         nouveau_notifier_free(&screen->query);
 186         nouveau_notifier_free(&screen->sync);
 187         nouveau_grobj_free(&screen->eng3d);
 188         nv04_surface_2d_takedown(&screen->eng2d);
 189
 190         nouveau_screen_fini(&screen->base);
 191
 192         FREE(pscreen);
 193 }
 194
 195 static void nv30_screen_init(struct nvfx_screen *screen)
 196 {
 197         struct nouveau_channel *chan = screen->base.channel;
 198         int i;
 199
 200         /* TODO: perhaps we should do some of this on nv40 too? */
 201         for (i=1; i<8; i++) {
 202                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1));
 203                 OUT_RING(chan, 0);
 204                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1));
 205                 OUT_RING(chan, 0);
 206         }
 207
 208         OUT_RING(chan, RING_3D(0x220, 1));
 209         OUT_RING(chan, 1);
 210
 211         OUT_RING(chan, RING_3D(0x03b0, 1));
 212         OUT_RING(chan, 0x00100000);
 213         OUT_RING(chan, RING_3D(0x1454, 1));
 214         OUT_RING(chan, 0);
 215         OUT_RING(chan, RING_3D(0x1d80, 1));
 216         OUT_RING(chan, 3);
 217         OUT_RING(chan, RING_3D(0x1450, 1));
 218         OUT_RING(chan, 0x00030004);
 219
 220         /* NEW */
 221         OUT_RING(chan, RING_3D(0x1e98, 1));
 222         OUT_RING(chan, 0);
 223         OUT_RING(chan, RING_3D(0x17e0, 3));
 224         OUT_RING(chan, fui(0.0));
 225         OUT_RING(chan, fui(0.0));
 226         OUT_RING(chan, fui(1.0));
 227         OUT_RING(chan, RING_3D(0x1f80, 16));
 228         for (i=0; i<16; i++) {
 229                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 230         }
 231
 232         OUT_RING(chan, RING_3D(0x120, 3));
 233         OUT_RING(chan, 0);
 234         OUT_RING(chan, 1);
 235         OUT_RING(chan, 2);
 236
 237         OUT_RING(chan, RING_3D(0x1d88, 1));
 238         OUT_RING(chan, 0x00001200);
 239
 240         OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1));
 241         OUT_RING(chan, 0);
 242
 243         OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2));
 244         OUT_RING(chan, fui(0.0));
 245         OUT_RING(chan, fui(1.0));
 246
 247         OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1));
 248         OUT_RING(chan, 0xffff0000);
 249
 250         /* enables use of vp rather than fixed-function somehow */
 251         OUT_RING(chan, RING_3D(0x1e94, 1));
 252         OUT_RING(chan, 0x13);
 253 }
 254
 255 static void nv40_screen_init(struct nvfx_screen *screen)
 256 {
 257         struct nouveau_channel *chan = screen->base.channel;
 258
 259         OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2));
 260         OUT_RING(chan, screen->base.channel->vram->handle);
 261         OUT_RING(chan, screen->base.channel->vram->handle);
 262
 263         OUT_RING(chan, RING_3D(0x1ea4, 3));
 264         OUT_RING(chan, 0x00000010);
 265         OUT_RING(chan, 0x01000100);
 266         OUT_RING(chan, 0xff800006);
 267
 268         /* vtxprog output routing */
 269         OUT_RING(chan, RING_3D(0x1fc4, 1));
 270         OUT_RING(chan, 0x06144321);
 271         OUT_RING(chan, RING_3D(0x1fc8, 2));
 272         OUT_RING(chan, 0xedcba987);
 273         OUT_RING(chan, 0x00000021);
 274         OUT_RING(chan, RING_3D(0x1fd0, 1));
 275         OUT_RING(chan, 0x00171615);
 276         OUT_RING(chan, RING_3D(0x1fd4, 1));
 277         OUT_RING(chan, 0x001b1a19);
 278
 279         OUT_RING(chan, RING_3D(0x1ef8, 1));
 280         OUT_RING(chan, 0x0020ffff);
 281         OUT_RING(chan, RING_3D(0x1d64, 1));
 282         OUT_RING(chan, 0x00d30000);
 283         OUT_RING(chan, RING_3D(0x1e94, 1));
 284         OUT_RING(chan, 0x00000001);
 285 }
 286
 287 static unsigned
 288 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 289 {
 290         int vram_hack_default = 0;
 291         int vram_hack;
 292         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 293         // It may also depend on the specific card or the AGP/PCIe chipset.
 294         if(screen->base.device->chipset == 0x47 /* G70 */
 295                 || screen->base.device->chipset == 0x49 /* G71 */
 296                 || screen->base.device->chipset == 0x46 /* G72 */
 297                 )
 298                 vram_hack_default = 1;
 299         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 300
 301 #ifdef DEBUG
 302         if(!vram_hack)
 303         {
 304                 fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
 305                         "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
 306         }
 307         else
 308         {
 309                 fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n"
 310                         "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
 311         }
 312 #endif
 313
 314         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 315 }
 316
 317 struct pipe_screen *
 318 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 319 {
 320         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 321         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 322         struct nouveau_channel *chan;
 323         struct pipe_screen *pscreen;
 324         unsigned eng3d_class = 0;
 325         int ret, i;
 326
 327         if (!screen)
 328                 return NULL;
 329
 330         pscreen = &screen->base.base;
 331
 332         ret = nouveau_screen_init(&screen->base, dev);
 333         if (ret) {
 334                 nvfx_screen_destroy(pscreen);
 335                 return NULL;
 336         }
 337         chan = screen->base.channel;
 338
 339         pscreen->winsys = ws;
 340         pscreen->destroy = nvfx_screen_destroy;
 341         pscreen->get_param = nvfx_screen_get_param;
 342         pscreen->get_paramf = nvfx_screen_get_paramf;
 343         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 344         pscreen->context_create = nvfx_create;
 345         pscreen->video_context_create = nvfx_video_create;
 346
 347         switch (dev->chipset & 0xf0) {
 348         case 0x30:
 349                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 350                         eng3d_class = 0x0397;
 351                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 352                         eng3d_class = 0x0697;
 353                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 354                         eng3d_class = 0x0497;
 355                 break;
 356         case 0x40:
 357                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 358                         eng3d_class = NV40TCL;
 359                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 360                         eng3d_class = NV44TCL;
 361                 screen->is_nv4x = ~0;
 362                 break;
 363         case 0x60:
 364                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 365                         eng3d_class = NV44TCL;
 366                 screen->is_nv4x = ~0;
 367                 break;
 368         }
 369
 370         if (!eng3d_class) {
 371                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 372                 return NULL;
 373         }
 374
 375         screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE);
 376
 377         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 378
 379         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 380         if(eng3d_class == NV40TCL)
 381                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 382
 383         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 384                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 385
 386         nvfx_screen_init_resource_functions(pscreen);
 387
 388         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 389         if (ret) {
 390                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 391                 return FALSE;
 392         }
 393
 394         /* 2D engine setup */
 395         screen->eng2d = nv04_surface_2d_init(&screen->base);
 396         screen->eng2d->buf = nvfx_surface_buffer;
 397
 398         /* Notifier for sync purposes */
 399         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 400         if (ret) {
 401                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 402                 nvfx_screen_destroy(pscreen);
 403                 return NULL;
 404         }
 405
 406         /* Query objects */
 407         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 408         {
 409                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 410                 if(!ret)
 411                         break;
 412         }
 413
 414         if (ret) {
 415                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 416                 nvfx_screen_destroy(pscreen);
 417                 return NULL;
 418         }
 419
 420         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 421         if (ret) {
 422                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 423                 nvfx_screen_destroy(pscreen);
 424                 return NULL;
 425         }
 426
 427         LIST_INITHEAD(&screen->query_list);
 428
 429         /* Vtxprog resources */
 430         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 431             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 432                 nvfx_screen_destroy(pscreen);
 433                 return NULL;
 434         }
 435
 436         BIND_RING(chan, screen->eng3d, 7);
 437
 438         /* Static eng3d initialisation */
 439         /* note that we just started using the channel, so we must have space in the pushbuffer */
 440         OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1));
 441         OUT_RING(chan, screen->sync->handle);
 442         OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2));
 443         OUT_RING(chan, chan->vram->handle);
 444         OUT_RING(chan, chan->gart->handle);
 445         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
 446         OUT_RING(chan, chan->vram->handle);
 447         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2));
 448         OUT_RING(chan, chan->vram->handle);
 449         OUT_RING(chan, chan->vram->handle);
 450         OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2));
 451         OUT_RING(chan, chan->vram->handle);
 452         OUT_RING(chan, chan->gart->handle);
 453
 454         OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2));
 455         OUT_RING(chan, 0);
 456         OUT_RING(chan, screen->query->handle);
 457
 458         OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2));
 459         OUT_RING(chan, chan->vram->handle);
 460         OUT_RING(chan, chan->vram->handle);
 461
 462         if(!screen->is_nv4x)
 463                 nv30_screen_init(screen);
 464         else
 465                 nv40_screen_init(screen);
 466
 467         return pscreen;
 468 }