src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7 #include "nouveau/nv_object.xml.h"
   8 #include "nvfx_context.h"
   9 #include "nvfx_video_context.h"
  10 #include "nvfx_screen.h"
  11 #include "nvfx_resource.h"
  12 #include "nvfx_tex.h"
  13
  14 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  15 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  16 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  17
  18 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  19 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  20 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  21
  22 static int
  23 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  24 {
  25         struct nvfx_screen *screen = nvfx_screen(pscreen);
  26
  27         switch (param) {
  28         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  29                 return 16;
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_GLSL:
  35                 return 1;
  36         case PIPE_CAP_ANISOTROPIC_FILTER:
  37                 return 1;
  38         case PIPE_CAP_POINT_SPRITE:
  39                 return 1;
  40         case PIPE_CAP_MAX_RENDER_TARGETS:
  41                 return screen->use_nv4x ? 4 : 2;
  42         case PIPE_CAP_OCCLUSION_QUERY:
  43                 return 1;
  44         case PIPE_CAP_TIMER_QUERY:
  45                 return 0;
  46         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  47                 return 1;
  48         case PIPE_CAP_TEXTURE_SWIZZLE:
  49                 return 1;
  50         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  51                 return 13;
  52         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  53                 return 10;
  54         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  57                 return !!screen->use_nv4x;
  58         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  59                 return 1;
  60         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  61                 return 0; /* We have 4 on nv40 - but unsupported currently */
  62         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  63                 return screen->advertise_blend_equation_separate;
  64         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  65                 return 16;
  66         case PIPE_CAP_INDEP_BLEND_ENABLE:
  67                 /* TODO: on nv40 we have separate color masks */
  68                 /* TODO: nv40 mrt blending is probably broken */
  69                 return 0;
  70         case PIPE_CAP_INDEP_BLEND_FUNC:
  71                 return 0;
  72         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  73                 return 0;
  74         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  75         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  76         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  77         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  78                 return 1;
  79         case PIPE_CAP_DEPTH_CLAMP:
  80                 return 0; // TODO: implement depth clamp
  81         case PIPE_CAP_PRIMITIVE_RESTART:
  82                 return 0; // TODO: implement primitive restart
  83         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  84                 return 0;
  85         default:
  86                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  87                 return 0;
  88         }
  89 }
  90
  91 static int
  92 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
  93 {
  94         struct nvfx_screen *screen = nvfx_screen(pscreen);
  95
  96         switch(shader) {
  97         case PIPE_SHADER_FRAGMENT:
  98                 switch(param) {
  99                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 100                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 101                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 102                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 103                         return 4096;
 104                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 105                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 106                          value (nv30:0/nv40:4) ? */
 107                         return screen->use_nv4x ? 4 : 0;
 108                 case PIPE_SHADER_CAP_MAX_INPUTS:
 109                         return screen->use_nv4x ? 12 : 10;
 110                 case PIPE_SHADER_CAP_MAX_CONSTS:
 111                         return screen->use_nv4x ? 224 : 32;
 112                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 113                     return 1;
 114                 case PIPE_SHADER_CAP_MAX_TEMPS:
 115                         return 32;
 116                 case PIPE_SHADER_CAP_MAX_ADDRS:
 117                         return screen->use_nv4x ? 1 : 0;
 118                 case PIPE_SHADER_CAP_MAX_PREDS:
 119                         return 0; /* we could expose these, but nothing uses them */
 120                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 121                     return 0;
 122                 default:
 123                         break;
 124                 }
 125                 break;
 126         case PIPE_SHADER_VERTEX:
 127                 switch(param) {
 128                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 129                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 130                         return screen->use_nv4x ? 512 : 256;
 131                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 132                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 133                         return screen->use_nv4x ? 512 : 0;
 134                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 135                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 136                          value (nv30:1/nv40:4) ? */
 137                         return screen->use_nv4x ? 4 : 1;
 138                 case PIPE_SHADER_CAP_MAX_INPUTS:
 139                         return 16;
 140                 case PIPE_SHADER_CAP_MAX_CONSTS:
 141                         /* - 6 is for clip planes; Gallium should be fixed to put
 142                          * them in the vertex shader itself, so we don't need to reserve these */
 143                         return (screen->use_nv4x ? 468 : 256) - 6;
 144                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 145                             return 1;
 146                 case PIPE_SHADER_CAP_MAX_TEMPS:
 147                         return screen->use_nv4x ? 32 : 13;
 148                 case PIPE_SHADER_CAP_MAX_ADDRS:
 149                         return 2;
 150                 case PIPE_SHADER_CAP_MAX_PREDS:
 151                         return 0; /* we could expose these, but nothing uses them */
 152                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 153                         return 1;
 154                 default:
 155                         break;
 156                 }
 157                 break;
 158         default:
 159                 break;
 160         }
 161         return 0;
 162 }
 163
 164 static float
 165 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 166 {
 167         struct nvfx_screen *screen = nvfx_screen(pscreen);
 168
 169         switch (param) {
 170         case PIPE_CAP_MAX_LINE_WIDTH:
 171         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 172                 return 10.0;
 173         case PIPE_CAP_MAX_POINT_WIDTH:
 174         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 175                 return 64.0;
 176         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 177                 return screen->use_nv4x ? 16.0 : 8.0;
 178         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 179                 return 15.0;
 180         default:
 181                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 182                 return 0.0;
 183         }
 184 }
 185
 186 static boolean
 187 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 188                                      enum pipe_format format,
 189                                      enum pipe_texture_target target,
 190                                      unsigned sample_count,
 191                                      unsigned bind, unsigned geom_flags)
 192 {
 193         struct nvfx_screen *screen = nvfx_screen(pscreen);
 194
 195          if (sample_count > 1)
 196                 return FALSE;
 197
 198         if (bind & PIPE_BIND_RENDER_TARGET) {
 199                 switch (format) {
 200                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 201                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 202                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 203                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 204                 case PIPE_FORMAT_B5G6R5_UNORM:
 205                         break;
 206                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 207                         if(!screen->advertise_fp16)
 208                                 return FALSE;
 209                         break;
 210                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 211                         if(!screen->advertise_fp32)
 212                                 return FALSE;
 213                         break;
 214                 default:
 215                         return FALSE;
 216                 }
 217         }
 218
 219         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 220                 switch (format) {
 221                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 222                 case PIPE_FORMAT_X8Z24_UNORM:
 223                 case PIPE_FORMAT_Z16_UNORM:
 224                         break;
 225                 default:
 226                         return FALSE;
 227                 }
 228         }
 229
 230         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 231                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 232                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 233                         return FALSE;
 234                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 235                         return FALSE;
 236                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 237                         return FALSE;
 238                 if(screen->use_nv4x)
 239                 {
 240                         if(tf->fmt[4] < 0)
 241                                 return FALSE;
 242                 }
 243                 else
 244                 {
 245                         if(tf->fmt[0] < 0)
 246                                 return FALSE;
 247                 }
 248         }
 249
 250         // note that we do actually support everything through translate
 251         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 252                 unsigned type = nvfx_vertex_formats[format];
 253                 if(!type)
 254                         return FALSE;
 255         }
 256
 257         if (bind & PIPE_BIND_INDEX_BUFFER) {
 258                 // 8-bit indices supported, but not in hardware index buffer
 259                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 260                         return FALSE;
 261         }
 262
 263         if(bind & PIPE_BIND_STREAM_OUTPUT)
 264                 return FALSE;
 265
 266         return TRUE;
 267 }
 268
 269 static void
 270 nvfx_screen_destroy(struct pipe_screen *pscreen)
 271 {
 272         struct nvfx_screen *screen = nvfx_screen(pscreen);
 273
 274         nouveau_resource_destroy(&screen->vp_exec_heap);
 275         nouveau_resource_destroy(&screen->vp_data_heap);
 276         nouveau_resource_destroy(&screen->query_heap);
 277         nouveau_notifier_free(&screen->query);
 278         nouveau_notifier_free(&screen->sync);
 279         nouveau_grobj_free(&screen->eng3d);
 280         nvfx_screen_surface_takedown(pscreen);
 281
 282         nouveau_screen_fini(&screen->base);
 283
 284         FREE(pscreen);
 285 }
 286
 287 static void nv30_screen_init(struct nvfx_screen *screen)
 288 {
 289         struct nouveau_channel *chan = screen->base.channel;
 290         int i;
 291
 292         /* TODO: perhaps we should do some of this on nv40 too? */
 293         for (i=1; i<8; i++) {
 294                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1));
 295                 OUT_RING(chan, 0);
 296                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1));
 297                 OUT_RING(chan, 0);
 298         }
 299
 300         OUT_RING(chan, RING_3D(0x220, 1));
 301         OUT_RING(chan, 1);
 302
 303         OUT_RING(chan, RING_3D(0x03b0, 1));
 304         OUT_RING(chan, 0x00100000);
 305         OUT_RING(chan, RING_3D(0x1454, 1));
 306         OUT_RING(chan, 0);
 307         OUT_RING(chan, RING_3D(0x1d80, 1));
 308         OUT_RING(chan, 3);
 309         OUT_RING(chan, RING_3D(0x1450, 1));
 310         OUT_RING(chan, 0x00030004);
 311
 312         /* NEW */
 313         OUT_RING(chan, RING_3D(0x1e98, 1));
 314         OUT_RING(chan, 0);
 315         OUT_RING(chan, RING_3D(0x17e0, 3));
 316         OUT_RING(chan, fui(0.0));
 317         OUT_RING(chan, fui(0.0));
 318         OUT_RING(chan, fui(1.0));
 319         OUT_RING(chan, RING_3D(0x1f80, 16));
 320         for (i=0; i<16; i++) {
 321                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 322         }
 323
 324         OUT_RING(chan, RING_3D(0x120, 3));
 325         OUT_RING(chan, 0);
 326         OUT_RING(chan, 1);
 327         OUT_RING(chan, 2);
 328
 329         OUT_RING(chan, RING_3D(0x1d88, 1));
 330         OUT_RING(chan, 0x00001200);
 331
 332         OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1));
 333         OUT_RING(chan, 0);
 334
 335         OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2));
 336         OUT_RING(chan, fui(0.0));
 337         OUT_RING(chan, fui(1.0));
 338
 339         OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1));
 340         OUT_RING(chan, 0xffff0000);
 341
 342         /* enables use of vp rather than fixed-function somehow */
 343         OUT_RING(chan, RING_3D(0x1e94, 1));
 344         OUT_RING(chan, 0x13);
 345 }
 346
 347 static void nv40_screen_init(struct nvfx_screen *screen)
 348 {
 349         struct nouveau_channel *chan = screen->base.channel;
 350
 351         OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2));
 352         OUT_RING(chan, screen->base.channel->vram->handle);
 353         OUT_RING(chan, screen->base.channel->vram->handle);
 354
 355         OUT_RING(chan, RING_3D(0x1450, 1));
 356         OUT_RING(chan, 0x00000004);
 357
 358         OUT_RING(chan, RING_3D(0x1ea4, 3));
 359         OUT_RING(chan, 0x00000010);
 360         OUT_RING(chan, 0x01000100);
 361         OUT_RING(chan, 0xff800006);
 362
 363         /* vtxprog output routing */
 364         OUT_RING(chan, RING_3D(0x1fc4, 1));
 365         OUT_RING(chan, 0x06144321);
 366         OUT_RING(chan, RING_3D(0x1fc8, 2));
 367         OUT_RING(chan, 0xedcba987);
 368         OUT_RING(chan, 0x0000006f);
 369         OUT_RING(chan, RING_3D(0x1fd0, 1));
 370         OUT_RING(chan, 0x00171615);
 371         OUT_RING(chan, RING_3D(0x1fd4, 1));
 372         OUT_RING(chan, 0x001b1a19);
 373
 374         OUT_RING(chan, RING_3D(0x1ef8, 1));
 375         OUT_RING(chan, 0x0020ffff);
 376         OUT_RING(chan, RING_3D(0x1d64, 1));
 377         OUT_RING(chan, 0x01d300d4);
 378         OUT_RING(chan, RING_3D(0x1e94, 1));
 379         OUT_RING(chan, 0x00000001);
 380
 381         OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1));
 382         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 383 }
 384
 385 static unsigned
 386 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 387 {
 388         int vram_hack_default = 0;
 389         int vram_hack;
 390         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 391         // It may also depend on the specific card or the AGP/PCIe chipset.
 392         if(screen->base.device->chipset == 0x47 /* G70 */
 393                 || screen->base.device->chipset == 0x49 /* G71 */
 394                 || screen->base.device->chipset == 0x46 /* G72 */
 395                 )
 396                 vram_hack_default = 1;
 397         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 398
 399         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 400 }
 401
 402 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 403 {
 404         struct nvfx_screen* screen = chan->user_private;
 405         struct nvfx_context* nvfx = screen->cur_ctx;
 406         if(nvfx)
 407                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 408 }
 409
 410 struct pipe_screen *
 411 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 412 {
 413         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 414         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 415         struct nouveau_channel *chan;
 416         struct pipe_screen *pscreen;
 417         unsigned eng3d_class = 0;
 418         int ret, i;
 419
 420         if (!screen)
 421                 return NULL;
 422
 423         pscreen = &screen->base.base;
 424
 425         ret = nouveau_screen_init(&screen->base, dev);
 426         if (ret) {
 427                 nvfx_screen_destroy(pscreen);
 428                 return NULL;
 429         }
 430         chan = screen->base.channel;
 431         screen->cur_ctx = NULL;
 432         chan->user_private = screen;
 433         chan->flush_notify = nvfx_channel_flush_notify;
 434
 435         pscreen->winsys = ws;
 436         pscreen->destroy = nvfx_screen_destroy;
 437         pscreen->get_param = nvfx_screen_get_param;
 438         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 439         pscreen->get_paramf = nvfx_screen_get_paramf;
 440         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 441         pscreen->context_create = nvfx_create;
 442         pscreen->video_context_create = nvfx_video_create;
 443
 444         switch (dev->chipset & 0xf0) {
 445         case 0x30:
 446                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 447                         eng3d_class = NV30_3D;
 448                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 449                         eng3d_class = NV34_3D;
 450                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 451                         eng3d_class = NV35_3D;
 452                 break;
 453         case 0x40:
 454                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 455                         eng3d_class = NV40_3D;
 456                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 457                         eng3d_class = NV44_3D;
 458                 screen->is_nv4x = ~0;
 459                 break;
 460         case 0x60:
 461                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 462                         eng3d_class = NV44_3D;
 463                 screen->is_nv4x = ~0;
 464                 break;
 465         }
 466
 467         if (!eng3d_class) {
 468                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 469                 return NULL;
 470         }
 471
 472         screen->advertise_npot = !!screen->is_nv4x;
 473         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 474         screen->use_nv4x = screen->is_nv4x;
 475
 476         if(screen->is_nv4x) {
 477                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 478                         screen->use_nv4x = 0;
 479                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 480                         screen->advertise_npot = 0;
 481                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 482                         screen->advertise_blend_equation_separate = 0;
 483         }
 484
 485         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 486         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 487
 488         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 489         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 490         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 491
 492         /* We don't advertise these by default because filtering and blending doesn't work as
 493          * it should, due to several restrictions.
 494          * The only exception is fp16 on nv40.
 495          */
 496         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 497         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 498
 499         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 500
 501         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 502         if(eng3d_class == NV40_3D)
 503                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 504
 505         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 506                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 507
 508         nvfx_screen_init_resource_functions(pscreen);
 509
 510         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 511         if (ret) {
 512                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 513                 return FALSE;
 514         }
 515
 516         /* 2D engine setup */
 517         nvfx_screen_surface_init(pscreen);
 518
 519         /* Notifier for sync purposes */
 520         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 521         if (ret) {
 522                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 523                 nvfx_screen_destroy(pscreen);
 524                 return NULL;
 525         }
 526
 527         /* Query objects */
 528         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 529         {
 530                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 531                 if(!ret)
 532                         break;
 533         }
 534
 535         if (ret) {
 536                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 537                 nvfx_screen_destroy(pscreen);
 538                 return NULL;
 539         }
 540
 541         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 542         if (ret) {
 543                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 544                 nvfx_screen_destroy(pscreen);
 545                 return NULL;
 546         }
 547
 548         LIST_INITHEAD(&screen->query_list);
 549
 550         /* Vtxprog resources */
 551         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 552             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 553                 nvfx_screen_destroy(pscreen);
 554                 return NULL;
 555         }
 556
 557         BIND_RING(chan, screen->eng3d, 7);
 558
 559         /* Static eng3d initialisation */
 560         /* note that we just started using the channel, so we must have space in the pushbuffer */
 561         OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1));
 562         OUT_RING(chan, screen->sync->handle);
 563         OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2));
 564         OUT_RING(chan, chan->vram->handle);
 565         OUT_RING(chan, chan->gart->handle);
 566         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1));
 567         OUT_RING(chan, chan->vram->handle);
 568         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2));
 569         OUT_RING(chan, chan->vram->handle);
 570         OUT_RING(chan, chan->vram->handle);
 571         OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2));
 572         OUT_RING(chan, chan->vram->handle);
 573         OUT_RING(chan, chan->gart->handle);
 574
 575         OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2));
 576         OUT_RING(chan, 0);
 577         OUT_RING(chan, screen->query->handle);
 578
 579         OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2));
 580         OUT_RING(chan, chan->vram->handle);
 581         OUT_RING(chan, chan->vram->handle);
 582
 583         if(!screen->is_nv4x)
 584                 nv30_screen_init(screen);
 585         else
 586                 nv40_screen_init(screen);
 587
 588         return pscreen;
 589 }