panfrost: do not report alpha-test as supported
[mesa.git] / src / gallium / drivers / panfrost / pan_assemble.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 */
24
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include "pan_bo.h"
29 #include "pan_context.h"
30
31 #include "compiler/nir/nir.h"
32 #include "nir/tgsi_to_nir.h"
33 #include "midgard/midgard_compile.h"
34 #include "util/u_dynarray.h"
35
36 #include "tgsi/tgsi_dump.h"
37
38 void
39 panfrost_shader_compile(
40 struct panfrost_context *ctx,
41 struct mali_shader_meta *meta,
42 enum pipe_shader_ir ir_type,
43 const void *ir,
44 gl_shader_stage stage,
45 struct panfrost_shader_state *state,
46 uint64_t *outputs_written)
47 {
48 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
49 uint8_t *dst;
50
51 nir_shader *s;
52
53 if (ir_type == PIPE_SHADER_IR_NIR) {
54 s = nir_shader_clone(NULL, ir);
55 } else {
56 assert (ir_type == PIPE_SHADER_IR_TGSI);
57 s = tgsi_to_nir(ir, ctx->base.screen);
58 }
59
60 s->info.stage = stage;
61
62 /* Call out to Midgard compiler given the above NIR */
63
64 midgard_program program = {
65 .alpha_ref = state->alpha_state.ref_value
66 };
67
68 midgard_compile_shader_nir(&ctx->compiler, s, &program, false);
69
70 /* Prepare the compiled binary for upload */
71 int size = program.compiled.size;
72 dst = program.compiled.data;
73
74 /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
75 * I bet someone just thought that would be a cute pun. At least,
76 * that's how I'd do it. */
77
78 state->bo = panfrost_bo_create(screen, size, PAN_BO_EXECUTE);
79 memcpy(state->bo->cpu, dst, size);
80 meta->shader = state->bo->gpu | program.first_tag;
81
82 util_dynarray_fini(&program.compiled);
83
84 /* Sysvals are prepended */
85 program.uniform_count += program.sysval_count;
86 state->sysval_count = program.sysval_count;
87 memcpy(state->sysval, program.sysvals, sizeof(state->sysval[0]) * state->sysval_count);
88
89 meta->midgard1.uniform_count = MIN2(program.uniform_count, program.uniform_cutoff);
90 meta->midgard1.work_count = program.work_register_count;
91
92 switch (stage) {
93 case MESA_SHADER_VERTEX:
94 meta->attribute_count = util_bitcount64(s->info.inputs_read);
95 meta->varying_count = util_bitcount64(s->info.outputs_written);
96 break;
97 case MESA_SHADER_FRAGMENT:
98 meta->attribute_count = 0;
99 meta->varying_count = util_bitcount64(s->info.inputs_read);
100 break;
101 case MESA_SHADER_COMPUTE:
102 /* TODO: images */
103 meta->attribute_count = 0;
104 meta->varying_count = 0;
105 break;
106 default:
107 unreachable("Unknown shader state");
108 }
109
110 state->can_discard = s->info.fs.uses_discard;
111 state->writes_point_size = program.writes_point_size;
112 state->reads_point_coord = false;
113 state->helper_invocations = s->info.fs.needs_helper_invocations;
114
115 if (outputs_written)
116 *outputs_written = s->info.outputs_written;
117
118 /* Separate as primary uniform count is truncated */
119 state->uniform_count = program.uniform_count;
120
121 meta->midgard1.unknown2 = 8; /* XXX */
122
123 unsigned default_vec1_swizzle = panfrost_get_default_swizzle(1);
124 unsigned default_vec2_swizzle = panfrost_get_default_swizzle(2);
125 unsigned default_vec4_swizzle = panfrost_get_default_swizzle(4);
126
127 /* Iterate the varyings and emit the corresponding descriptor */
128 for (unsigned i = 0; i < meta->varying_count; ++i) {
129 unsigned location = program.varyings[i];
130
131 /* Default to a vec4 varying */
132 struct mali_attr_meta v = {
133 .format = MALI_RGBA32F,
134 .swizzle = default_vec4_swizzle,
135 .unknown1 = 0x2,
136 };
137
138 /* Check for special cases, otherwise assume general varying */
139
140 if (location == VARYING_SLOT_POS) {
141 if (stage == MESA_SHADER_FRAGMENT)
142 state->reads_frag_coord = true;
143 else
144 v.format = MALI_VARYING_POS;
145 } else if (location == VARYING_SLOT_PSIZ) {
146 v.format = MALI_R16F;
147 v.swizzle = default_vec1_swizzle;
148
149 state->writes_point_size = true;
150 } else if (location == VARYING_SLOT_PNTC) {
151 v.format = MALI_RG16F;
152 v.swizzle = default_vec2_swizzle;
153
154 state->reads_point_coord = true;
155 } else if (location == VARYING_SLOT_FACE) {
156 v.format = MALI_R32I;
157 v.swizzle = default_vec1_swizzle;
158
159 state->reads_face = true;
160 }
161
162 state->varyings[i] = v;
163 state->varyings_loc[i] = location;
164 }
165 }