afd16abb2d21d23789f7bc3afee61a753b25db74
2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 #include "pan_context.h"
31 #include "compiler/nir/nir.h"
32 #include "nir/tgsi_to_nir.h"
33 #include "midgard/midgard_compile.h"
34 #include "util/u_dynarray.h"
36 #include "tgsi/tgsi_dump.h"
39 panfrost_shader_compile(
40 struct panfrost_context
*ctx
,
41 struct mali_shader_meta
*meta
,
42 enum pipe_shader_ir ir_type
,
44 gl_shader_stage stage
,
45 struct panfrost_shader_state
*state
,
46 uint64_t *outputs_written
)
48 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
53 if (ir_type
== PIPE_SHADER_IR_NIR
) {
54 s
= nir_shader_clone(NULL
, ir
);
56 assert (ir_type
== PIPE_SHADER_IR_TGSI
);
57 s
= tgsi_to_nir(ir
, ctx
->base
.screen
);
60 s
->info
.stage
= stage
;
62 if (stage
== MESA_SHADER_FRAGMENT
) {
63 /* Inject the alpha test now if we need to */
65 if (state
->alpha_state
.enabled
) {
66 NIR_PASS_V(s
, nir_lower_alpha_test
, state
->alpha_state
.func
, false);
70 /* Call out to Midgard compiler given the above NIR */
72 midgard_program program
= {
73 .alpha_ref
= state
->alpha_state
.ref_value
76 midgard_compile_shader_nir(&ctx
->compiler
, s
, &program
, false);
78 /* Prepare the compiled binary for upload */
79 int size
= program
.compiled
.size
;
80 dst
= program
.compiled
.data
;
82 /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
83 * I bet someone just thought that would be a cute pun. At least,
84 * that's how I'd do it. */
86 state
->bo
= panfrost_bo_create(screen
, size
, PAN_BO_EXECUTE
);
87 memcpy(state
->bo
->cpu
, dst
, size
);
88 meta
->shader
= state
->bo
->gpu
| program
.first_tag
;
90 util_dynarray_fini(&program
.compiled
);
92 /* Sysvals are prepended */
93 program
.uniform_count
+= program
.sysval_count
;
94 state
->sysval_count
= program
.sysval_count
;
95 memcpy(state
->sysval
, program
.sysvals
, sizeof(state
->sysval
[0]) * state
->sysval_count
);
97 meta
->midgard1
.uniform_count
= MIN2(program
.uniform_count
, program
.uniform_cutoff
);
98 meta
->midgard1
.work_count
= program
.work_register_count
;
101 case MESA_SHADER_VERTEX
:
102 meta
->attribute_count
= util_bitcount64(s
->info
.inputs_read
);
103 meta
->varying_count
= util_bitcount64(s
->info
.outputs_written
);
105 case MESA_SHADER_FRAGMENT
:
106 meta
->attribute_count
= 0;
107 meta
->varying_count
= util_bitcount64(s
->info
.inputs_read
);
109 case MESA_SHADER_COMPUTE
:
111 meta
->attribute_count
= 0;
112 meta
->varying_count
= 0;
115 unreachable("Unknown shader state");
118 state
->can_discard
= s
->info
.fs
.uses_discard
;
119 state
->writes_point_size
= program
.writes_point_size
;
120 state
->reads_point_coord
= false;
121 state
->helper_invocations
= s
->info
.fs
.needs_helper_invocations
;
124 *outputs_written
= s
->info
.outputs_written
;
126 /* Separate as primary uniform count is truncated */
127 state
->uniform_count
= program
.uniform_count
;
129 meta
->midgard1
.unknown2
= 8; /* XXX */
131 unsigned default_vec1_swizzle
= panfrost_get_default_swizzle(1);
132 unsigned default_vec2_swizzle
= panfrost_get_default_swizzle(2);
133 unsigned default_vec4_swizzle
= panfrost_get_default_swizzle(4);
135 /* Iterate the varyings and emit the corresponding descriptor */
136 for (unsigned i
= 0; i
< meta
->varying_count
; ++i
) {
137 unsigned location
= program
.varyings
[i
];
139 /* Default to a vec4 varying */
140 struct mali_attr_meta v
= {
141 .format
= MALI_RGBA32F
,
142 .swizzle
= default_vec4_swizzle
,
146 /* Check for special cases, otherwise assume general varying */
148 if (location
== VARYING_SLOT_POS
) {
149 if (stage
== MESA_SHADER_FRAGMENT
)
150 state
->reads_frag_coord
= true;
152 v
.format
= MALI_VARYING_POS
;
153 } else if (location
== VARYING_SLOT_PSIZ
) {
154 v
.format
= MALI_R16F
;
155 v
.swizzle
= default_vec1_swizzle
;
157 state
->writes_point_size
= true;
158 } else if (location
== VARYING_SLOT_PNTC
) {
159 v
.format
= MALI_RG16F
;
160 v
.swizzle
= default_vec2_swizzle
;
162 state
->reads_point_coord
= true;
163 } else if (location
== VARYING_SLOT_FACE
) {
164 v
.format
= MALI_R32I
;
165 v
.swizzle
= default_vec1_swizzle
;
167 state
->reads_face
= true;
170 state
->varyings
[i
] = v
;
171 state
->varyings_loc
[i
] = location
;