src/gallium/drivers/panfrost/pan_assemble.c

   1 /*
   2  * © Copyright 2018 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include "pan_bo.h"
  29 #include "pan_context.h"
  30 #include "pan_util.h"
  31
  32 #include "compiler/nir/nir.h"
  33 #include "nir/tgsi_to_nir.h"
  34 #include "midgard/midgard_compile.h"
  35 #include "util/u_dynarray.h"
  36
  37 #include "tgsi/tgsi_dump.h"
  38
  39 void
  40 panfrost_shader_compile(struct panfrost_context *ctx,
  41                         enum pipe_shader_ir ir_type,
  42                         const void *ir,
  43                         gl_shader_stage stage,
  44                         struct panfrost_shader_state *state,
  45                         uint64_t *outputs_written)
  46 {
  47         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
  48         uint8_t *dst;
  49
  50         nir_shader *s;
  51
  52         if (ir_type == PIPE_SHADER_IR_NIR) {
  53                 s = nir_shader_clone(NULL, ir);
  54         } else {
  55                 assert (ir_type == PIPE_SHADER_IR_TGSI);
  56                 s = tgsi_to_nir(ir, ctx->base.screen);
  57         }
  58
  59         s->info.stage = stage;
  60
  61         /* Call out to Midgard compiler given the above NIR */
  62
  63         panfrost_program program = {
  64                 .alpha_ref = state->alpha_state.ref_value
  65         };
  66
  67         midgard_compile_shader_nir(s, &program, false, 0, screen->gpu_id,
  68                         pan_debug & PAN_DBG_PRECOMPILE);
  69
  70         /* Prepare the compiled binary for upload */
  71         int size = program.compiled.size;
  72         dst = program.compiled.data;
  73
  74         /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
  75          * I bet someone just thought that would be a cute pun. At least,
  76          * that's how I'd do it. */
  77
  78         if (size) {
  79                 state->bo = panfrost_bo_create(screen, size, PAN_BO_EXECUTE);
  80                 memcpy(state->bo->cpu, dst, size);
  81                 state->first_tag = program.first_tag;
  82         } else {
  83                 /* No shader. Use dummy tag to avoid INSTR_INVALID_ENC */
  84                 state->first_tag = 1;
  85         }
  86
  87         util_dynarray_fini(&program.compiled);
  88
  89         /* Sysvals are prepended */
  90         program.uniform_count += program.sysval_count;
  91         state->sysval_count = program.sysval_count;
  92         memcpy(state->sysval, program.sysvals, sizeof(state->sysval[0]) * state->sysval_count);
  93
  94         bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID);
  95         bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID);
  96
  97         switch (stage) {
  98         case MESA_SHADER_VERTEX:
  99                 state->attribute_count = util_bitcount64(s->info.inputs_read);
 100                 state->varying_count = util_bitcount64(s->info.outputs_written);
 101
 102                 if (vertex_id)
 103                         state->attribute_count = MAX2(state->attribute_count, PAN_VERTEX_ID + 1);
 104
 105                 if (instance_id)
 106                         state->attribute_count = MAX2(state->attribute_count, PAN_INSTANCE_ID + 1);
 107
 108                 break;
 109         case MESA_SHADER_FRAGMENT:
 110                 state->attribute_count = 0;
 111                 state->varying_count = util_bitcount64(s->info.inputs_read);
 112                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 113                         state->writes_depth = true;
 114                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
 115                         state->writes_stencil = true;
 116                 break;
 117         case MESA_SHADER_COMPUTE:
 118                 /* TODO: images */
 119                 state->attribute_count = 0;
 120                 state->varying_count = 0;
 121                 state->shared_size = s->info.cs.shared_size;
 122                 break;
 123         default:
 124                 unreachable("Unknown shader state");
 125         }
 126
 127         state->can_discard = s->info.fs.uses_discard;
 128         state->writes_point_size = program.writes_point_size;
 129         state->reads_point_coord = false;
 130         state->helper_invocations = s->info.fs.needs_helper_invocations;
 131         state->stack_size = program.tls_size;
 132
 133         if (outputs_written)
 134                 *outputs_written = s->info.outputs_written;
 135
 136         /* Separate as primary uniform count is truncated */
 137         state->uniform_count = program.uniform_count;
 138         state->uniform_cutoff = program.uniform_cutoff;
 139         state->work_reg_count = program.work_register_count;
 140
 141         unsigned default_vec1_swizzle = panfrost_get_default_swizzle(1);
 142         unsigned default_vec2_swizzle = panfrost_get_default_swizzle(2);
 143         unsigned default_vec4_swizzle = panfrost_get_default_swizzle(4);
 144
 145         /* Iterate the varyings and emit the corresponding descriptor */
 146         for (unsigned i = 0; i < state->varying_count; ++i) {
 147                 unsigned location = program.varyings[i];
 148
 149                 /* Default to a vec4 varying */
 150                 struct mali_attr_meta v = {
 151                         .format = program.varying_type[i],
 152                         .swizzle = default_vec4_swizzle,
 153                         .unknown1 = 0x2,
 154                 };
 155
 156                 /* Check for special cases, otherwise assume general varying */
 157
 158                 if (location == VARYING_SLOT_POS) {
 159                         if (stage == MESA_SHADER_FRAGMENT)
 160                                 state->reads_frag_coord = true;
 161                         else
 162                                 v.format = MALI_VARYING_POS;
 163                 } else if (location == VARYING_SLOT_PSIZ) {
 164                         v.format = MALI_R16F;
 165                         v.swizzle = default_vec1_swizzle;
 166
 167                         state->writes_point_size = true;
 168                 } else if (location == VARYING_SLOT_PNTC) {
 169                         v.format = MALI_RG16F;
 170                         v.swizzle = default_vec2_swizzle;
 171
 172                         state->reads_point_coord = true;
 173                 } else if (location == VARYING_SLOT_FACE) {
 174                         v.format = MALI_R32I;
 175                         v.swizzle = default_vec1_swizzle;
 176
 177                         state->reads_face = true;
 178                 }
 179
 180                 state->varyings[i] = v;
 181                 state->varyings_loc[i] = location;
 182         }
 183 }