2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 #include "pan_context.h"
32 #include "compiler/nir/nir.h"
33 #include "nir/tgsi_to_nir.h"
34 #include "midgard/midgard_compile.h"
35 #include "util/u_dynarray.h"
37 #include "tgsi/tgsi_dump.h"
40 panfrost_shader_compile(
41 struct panfrost_context
*ctx
,
42 struct mali_shader_meta
*meta
,
43 enum pipe_shader_ir ir_type
,
45 gl_shader_stage stage
,
46 struct panfrost_shader_state
*state
,
47 uint64_t *outputs_written
)
49 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
54 if (ir_type
== PIPE_SHADER_IR_NIR
) {
55 s
= nir_shader_clone(NULL
, ir
);
57 assert (ir_type
== PIPE_SHADER_IR_TGSI
);
58 s
= tgsi_to_nir(ir
, ctx
->base
.screen
);
61 s
->info
.stage
= stage
;
63 /* Call out to Midgard compiler given the above NIR */
65 midgard_program program
= {
66 .alpha_ref
= state
->alpha_state
.ref_value
69 midgard_compile_shader_nir(s
, &program
, false, 0, screen
->gpu_id
,
70 pan_debug
& PAN_DBG_PRECOMPILE
);
72 /* Prepare the compiled binary for upload */
73 int size
= program
.compiled
.size
;
74 dst
= program
.compiled
.data
;
76 /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
77 * I bet someone just thought that would be a cute pun. At least,
78 * that's how I'd do it. */
81 state
->bo
= panfrost_bo_create(screen
, size
, PAN_BO_EXECUTE
);
82 memcpy(state
->bo
->cpu
, dst
, size
);
83 meta
->shader
= state
->bo
->gpu
| program
.first_tag
;
84 state
->first_tag
= program
.first_tag
;
86 /* No shader. Use dummy tag to avoid INSTR_INVALID_ENC */
87 meta
->shader
= 0x0 | 1;
91 util_dynarray_fini(&program
.compiled
);
93 /* Sysvals are prepended */
94 program
.uniform_count
+= program
.sysval_count
;
95 state
->sysval_count
= program
.sysval_count
;
96 memcpy(state
->sysval
, program
.sysvals
, sizeof(state
->sysval
[0]) * state
->sysval_count
);
98 meta
->midgard1
.uniform_count
= MIN2(program
.uniform_count
, program
.uniform_cutoff
);
99 meta
->midgard1
.work_count
= program
.work_register_count
;
101 bool vertex_id
= s
->info
.system_values_read
& (1 << SYSTEM_VALUE_VERTEX_ID
);
102 bool instance_id
= s
->info
.system_values_read
& (1 << SYSTEM_VALUE_INSTANCE_ID
);
105 case MESA_SHADER_VERTEX
:
106 state
->attribute_count
= util_bitcount64(s
->info
.inputs_read
);
107 state
->varying_count
= util_bitcount64(s
->info
.outputs_written
);
110 state
->attribute_count
= MAX2(state
->attribute_count
, PAN_VERTEX_ID
+ 1);
113 state
->attribute_count
= MAX2(state
->attribute_count
, PAN_INSTANCE_ID
+ 1);
116 case MESA_SHADER_FRAGMENT
:
117 state
->attribute_count
= 0;
118 state
->varying_count
= util_bitcount64(s
->info
.inputs_read
);
119 if (s
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
120 state
->writes_depth
= true;
121 if (s
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
122 state
->writes_stencil
= true;
124 case MESA_SHADER_COMPUTE
:
126 state
->attribute_count
= 0;
127 state
->varying_count
= 0;
128 state
->shared_size
= s
->info
.cs
.shared_size
;
131 unreachable("Unknown shader state");
134 state
->can_discard
= s
->info
.fs
.uses_discard
;
135 state
->writes_point_size
= program
.writes_point_size
;
136 state
->reads_point_coord
= false;
137 state
->helper_invocations
= s
->info
.fs
.needs_helper_invocations
;
138 state
->stack_size
= program
.tls_size
;
141 *outputs_written
= s
->info
.outputs_written
;
143 /* Separate as primary uniform count is truncated */
144 state
->uniform_count
= program
.uniform_count
;
145 state
->uniform_cutoff
= program
.uniform_cutoff
;
146 state
->work_reg_count
= program
.work_register_count
;
148 meta
->attribute_count
= state
->attribute_count
;
149 meta
->varying_count
= state
->varying_count
;
150 meta
->midgard1
.flags_hi
= 8; /* XXX */
152 unsigned default_vec1_swizzle
= panfrost_get_default_swizzle(1);
153 unsigned default_vec2_swizzle
= panfrost_get_default_swizzle(2);
154 unsigned default_vec4_swizzle
= panfrost_get_default_swizzle(4);
156 /* Iterate the varyings and emit the corresponding descriptor */
157 for (unsigned i
= 0; i
< state
->varying_count
; ++i
) {
158 unsigned location
= program
.varyings
[i
];
160 /* Default to a vec4 varying */
161 struct mali_attr_meta v
= {
162 .format
= program
.varying_type
[i
],
163 .swizzle
= default_vec4_swizzle
,
167 /* Check for special cases, otherwise assume general varying */
169 if (location
== VARYING_SLOT_POS
) {
170 if (stage
== MESA_SHADER_FRAGMENT
)
171 state
->reads_frag_coord
= true;
173 v
.format
= MALI_VARYING_POS
;
174 } else if (location
== VARYING_SLOT_PSIZ
) {
175 v
.format
= MALI_R16F
;
176 v
.swizzle
= default_vec1_swizzle
;
178 state
->writes_point_size
= true;
179 } else if (location
== VARYING_SLOT_PNTC
) {
180 v
.format
= MALI_RG16F
;
181 v
.swizzle
= default_vec2_swizzle
;
183 state
->reads_point_coord
= true;
184 } else if (location
== VARYING_SLOT_FACE
) {
185 v
.format
= MALI_R32I
;
186 v
.swizzle
= default_vec1_swizzle
;
188 state
->reads_face
= true;
191 state
->varyings
[i
] = v
;
192 state
->varyings_loc
[i
] = location
;