2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
30 #include "compiler/nir/nir.h"
31 #include "nir/tgsi_to_nir.h"
32 #include "midgard/midgard_compile.h"
33 #include "util/u_dynarray.h"
35 #include "tgsi/tgsi_dump.h"
38 panfrost_shader_compile(
39 struct panfrost_context
*ctx
,
40 struct mali_shader_meta
*meta
,
41 enum pipe_shader_ir ir_type
,
43 gl_shader_stage stage
,
44 struct panfrost_shader_state
*state
)
46 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
51 if (ir_type
== PIPE_SHADER_IR_NIR
) {
52 s
= nir_shader_clone(NULL
, ir
);
54 assert (ir_type
== PIPE_SHADER_IR_TGSI
);
55 s
= tgsi_to_nir(ir
, ctx
->base
.screen
);
58 s
->info
.stage
= stage
;
60 if (stage
== MESA_SHADER_FRAGMENT
) {
61 /* Inject the alpha test now if we need to */
63 if (state
->alpha_state
.enabled
) {
64 NIR_PASS_V(s
, nir_lower_alpha_test
, state
->alpha_state
.func
, false);
68 /* Call out to Midgard compiler given the above NIR */
70 midgard_program program
= {
71 .alpha_ref
= state
->alpha_state
.ref_value
74 midgard_compile_shader_nir(&ctx
->compiler
, s
, &program
, false);
76 /* Prepare the compiled binary for upload */
77 int size
= program
.compiled
.size
;
78 dst
= program
.compiled
.data
;
80 /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
81 * I bet someone just thought that would be a cute pun. At least,
82 * that's how I'd do it. */
84 state
->bo
= panfrost_drm_create_bo(screen
, size
, PAN_ALLOCATE_EXECUTE
);
85 memcpy(state
->bo
->cpu
, dst
, size
);
86 meta
->shader
= state
->bo
->gpu
| program
.first_tag
;
88 util_dynarray_fini(&program
.compiled
);
90 /* Sysvals are prepended */
91 program
.uniform_count
+= program
.sysval_count
;
92 state
->sysval_count
= program
.sysval_count
;
93 memcpy(state
->sysval
, program
.sysvals
, sizeof(state
->sysval
[0]) * state
->sysval_count
);
95 meta
->midgard1
.uniform_count
= MIN2(program
.uniform_count
, program
.uniform_cutoff
);
96 meta
->midgard1
.work_count
= program
.work_register_count
;
99 case MESA_SHADER_VERTEX
:
100 meta
->attribute_count
= util_bitcount64(s
->info
.inputs_read
);
101 meta
->varying_count
= util_bitcount64(s
->info
.outputs_written
);
103 case MESA_SHADER_FRAGMENT
:
104 meta
->attribute_count
= 0;
105 meta
->varying_count
= util_bitcount64(s
->info
.inputs_read
);
107 case MESA_SHADER_COMPUTE
:
109 meta
->attribute_count
= 0;
110 meta
->varying_count
= 0;
113 unreachable("Unknown shader state");
116 state
->can_discard
= s
->info
.fs
.uses_discard
;
117 state
->writes_point_size
= program
.writes_point_size
;
118 state
->reads_point_coord
= false;
119 state
->helper_invocations
= s
->info
.fs
.needs_helper_invocations
;
121 /* Separate as primary uniform count is truncated */
122 state
->uniform_count
= program
.uniform_count
;
124 meta
->midgard1
.unknown2
= 8; /* XXX */
126 unsigned default_vec1_swizzle
= panfrost_get_default_swizzle(1);
127 unsigned default_vec2_swizzle
= panfrost_get_default_swizzle(2);
128 unsigned default_vec4_swizzle
= panfrost_get_default_swizzle(4);
130 /* Iterate the varyings and emit the corresponding descriptor */
131 for (unsigned i
= 0; i
< meta
->varying_count
; ++i
) {
132 unsigned location
= program
.varyings
[i
];
134 /* Default to a vec4 varying */
135 struct mali_attr_meta v
= {
136 .format
= MALI_RGBA32F
,
137 .swizzle
= default_vec4_swizzle
,
141 /* Check for special cases, otherwise assume general varying */
143 if (location
== VARYING_SLOT_POS
) {
145 v
.format
= MALI_VARYING_POS
;
146 } else if (location
== VARYING_SLOT_PSIZ
) {
148 v
.format
= MALI_R16F
;
149 v
.swizzle
= default_vec1_swizzle
;
151 state
->writes_point_size
= true;
152 } else if (location
== VARYING_SLOT_PNTC
) {
154 v
.format
= MALI_RG16F
;
155 v
.swizzle
= default_vec2_swizzle
;
157 state
->reads_point_coord
= true;
158 } else if (location
== VARYING_SLOT_FACE
) {
160 v
.format
= MALI_R32I
;
161 v
.swizzle
= default_vec1_swizzle
;
163 state
->reads_face
= true;
168 state
->varyings
[i
] = v
;
169 state
->varyings_loc
[i
] = location
;