src/gallium/drivers/panfrost/pan_assemble.c

   1 /*
   2  * © Copyright 2018 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include "pan_context.h"
  29
  30 #include "compiler/nir/nir.h"
  31 #include "nir/tgsi_to_nir.h"
  32 #include "midgard/midgard_compile.h"
  33 #include "util/u_dynarray.h"
  34
  35 #include "tgsi/tgsi_dump.h"
  36
  37 void
  38 panfrost_shader_compile(struct panfrost_context *ctx, struct mali_shader_meta *meta, const char *src, int type, struct panfrost_shader_state *state)
  39 {
  40         uint8_t *dst;
  41
  42         nir_shader *s;
  43
  44         struct pipe_shader_state *cso = state->base;
  45
  46         if (cso->type == PIPE_SHADER_IR_NIR) {
  47                 s = nir_shader_clone(NULL, cso->ir.nir);
  48         } else {
  49                 assert (cso->type == PIPE_SHADER_IR_TGSI);
  50                 //tgsi_dump(cso->tokens, 0);
  51                 s = tgsi_to_nir(cso->tokens, ctx->base.screen);
  52         }
  53
  54         s->info.stage = type == JOB_TYPE_VERTEX ? MESA_SHADER_VERTEX : MESA_SHADER_FRAGMENT;
  55
  56         if (s->info.stage == MESA_SHADER_FRAGMENT) {
  57                 /* Inject the alpha test now if we need to */
  58
  59                 if (state->alpha_state.enabled) {
  60                         NIR_PASS_V(s, nir_lower_alpha_test, state->alpha_state.func, false);
  61                 }
  62         }
  63
  64         /* Call out to Midgard compiler given the above NIR */
  65
  66         midgard_program program = {
  67                 .alpha_ref = state->alpha_state.ref_value
  68         };
  69
  70         midgard_compile_shader_nir(s, &program, false);
  71
  72         /* Prepare the compiled binary for upload */
  73         int size = program.compiled.size;
  74         dst = program.compiled.data;
  75
  76         /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
  77          * I bet someone just thought that would be a cute pun. At least,
  78          * that's how I'd do it. */
  79
  80         meta->shader = panfrost_upload(&ctx->shaders, dst, size, true) | program.first_tag;
  81
  82         util_dynarray_fini(&program.compiled);
  83
  84         meta->midgard1.uniform_count = MIN2(program.uniform_count, program.uniform_cutoff);
  85         meta->attribute_count = program.attribute_count;
  86         meta->varying_count = program.varying_count;
  87         meta->midgard1.work_count = program.work_register_count;
  88
  89         state->can_discard = program.can_discard;
  90         state->writes_point_size = program.writes_point_size;
  91         state->reads_point_coord = false;
  92
  93         /* Separate as primary uniform count is truncated */
  94         state->uniform_count = program.uniform_count;
  95
  96         meta->midgard1.unknown2 = 8; /* XXX */
  97
  98         unsigned default_vec1_swizzle = panfrost_get_default_swizzle(1);
  99         unsigned default_vec2_swizzle = panfrost_get_default_swizzle(2);
 100         unsigned default_vec4_swizzle = panfrost_get_default_swizzle(4);
 101
 102         /* Iterate the varyings and emit the corresponding descriptor */
 103         unsigned general_purpose_count = 0;
 104
 105         for (unsigned i = 0; i < program.varying_count; ++i) {
 106                 unsigned location = program.varyings[i];
 107
 108                 /* Default to a vec4 varying */
 109                 struct mali_attr_meta v = {
 110                         .format = MALI_RGBA16F,
 111                         .swizzle = default_vec4_swizzle,
 112                         .unknown1 = 0x2,
 113                 };
 114
 115                 /* Check for special cases, otherwise assume general varying */
 116
 117                 if (location == VARYING_SLOT_POS) {
 118                         v.index = 1;
 119                         v.format = MALI_VARYING_POS;
 120                 } else if (location == VARYING_SLOT_PSIZ) {
 121                         v.index = 2;
 122                         v.format = MALI_R16F;
 123                         v.swizzle = default_vec1_swizzle;
 124
 125                         state->writes_point_size = true;
 126                 } else if (location == VARYING_SLOT_PNTC) {
 127                         v.index = 3;
 128                         v.format = MALI_RG16F;
 129                         v.swizzle = default_vec2_swizzle;
 130
 131                         state->reads_point_coord = true;
 132                 } else {
 133                         v.index = 0;
 134                         v.src_offset = 8 * (general_purpose_count++);
 135                 }
 136
 137                 state->varyings[i] = v;
 138         }
 139
 140         /* Set the stride for the general purpose fp16 vec4 varyings */
 141         state->general_varying_stride = (2 * 4) * general_purpose_count;
 142 }