src/gallium/drivers/panfrost/pan_assemble.c

   1 /*
   2  * © Copyright 2018 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include "pan_bo.h"
  29 #include "pan_context.h"
  30 #include "pan_util.h"
  31 #include "panfrost-quirks.h"
  32
  33 #include "compiler/nir/nir.h"
  34 #include "nir/tgsi_to_nir.h"
  35 #include "midgard/midgard_compile.h"
  36 #include "bifrost/bifrost_compile.h"
  37 #include "util/u_dynarray.h"
  38
  39 #include "tgsi/tgsi_dump.h"
  40
  41 static unsigned
  42 pan_format_from_nir_base(nir_alu_type base)
  43 {
  44         switch (base) {
  45         case nir_type_int:
  46                 return MALI_FORMAT_SINT;
  47         case nir_type_uint:
  48         case nir_type_bool:
  49                 return MALI_FORMAT_UINT;
  50         case nir_type_float:
  51                 return MALI_CHANNEL_FLOAT;
  52         default:
  53                 unreachable("Invalid base");
  54         }
  55 }
  56
  57 static unsigned
  58 pan_format_from_nir_size(nir_alu_type base, unsigned size)
  59 {
  60         if (base == nir_type_float) {
  61                 switch (size) {
  62                 case 16: return MALI_FORMAT_SINT;
  63                 case 32: return MALI_FORMAT_UNORM;
  64                 default:
  65                         unreachable("Invalid float size for format");
  66                 }
  67         } else {
  68                 switch (size) {
  69                 case 1:
  70                 case 8:  return MALI_CHANNEL_8;
  71                 case 16: return MALI_CHANNEL_16;
  72                 case 32: return MALI_CHANNEL_32;
  73                 default:
  74                          unreachable("Invalid int size for format");
  75                 }
  76         }
  77 }
  78
  79 static enum mali_format
  80 pan_format_from_glsl(const struct glsl_type *type)
  81 {
  82         enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type));
  83         nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
  84
  85         unsigned base = nir_alu_type_get_base_type(t);
  86         unsigned size = nir_alu_type_get_type_size(t);
  87
  88         return pan_format_from_nir_base(base) |
  89                 pan_format_from_nir_size(base, size) |
  90                 MALI_NR_CHANNELS(4);
  91 }
  92
  93 static enum bifrost_shader_type
  94 bifrost_blend_type_from_nir(nir_alu_type nir_type)
  95 {
  96         switch(nir_type) {
  97         case 0: /* Render target not in use */
  98                 return 0;
  99         case nir_type_float16:
 100                 return BIFROST_BLEND_F16;
 101         case nir_type_float32:
 102                 return BIFROST_BLEND_F32;
 103         case nir_type_int32:
 104                 return BIFROST_BLEND_I32;
 105         case nir_type_uint32:
 106                 return BIFROST_BLEND_U32;
 107         case nir_type_int16:
 108                 return BIFROST_BLEND_I16;
 109         case nir_type_uint16:
 110                 return BIFROST_BLEND_U16;
 111         default:
 112                 DBG("Unsupported blend shader type for NIR alu type %d", nir_type);
 113                 assert(0);
 114                 return 0;
 115         }
 116 }
 117
 118 void
 119 panfrost_shader_compile(struct panfrost_context *ctx,
 120                         enum pipe_shader_ir ir_type,
 121                         const void *ir,
 122                         gl_shader_stage stage,
 123                         struct panfrost_shader_state *state,
 124                         uint64_t *outputs_written)
 125 {
 126         struct panfrost_device *dev = pan_device(ctx->base.screen);
 127         uint8_t *dst;
 128
 129         nir_shader *s;
 130
 131         if (ir_type == PIPE_SHADER_IR_NIR) {
 132                 s = nir_shader_clone(NULL, ir);
 133         } else {
 134                 assert (ir_type == PIPE_SHADER_IR_TGSI);
 135                 s = tgsi_to_nir(ir, ctx->base.screen, false);
 136         }
 137
 138         s->info.stage = stage;
 139
 140         /* Call out to Midgard compiler given the above NIR */
 141
 142         panfrost_program program = {
 143                 .alpha_ref = state->alpha_state.ref_value
 144         };
 145
 146         if (dev->quirks & IS_BIFROST) {
 147                 bifrost_compile_shader_nir(s, &program, dev->gpu_id);
 148         } else {
 149                 midgard_compile_shader_nir(s, &program, false, 0, dev->gpu_id,
 150                                 pan_debug & PAN_DBG_PRECOMPILE);
 151         }
 152
 153         /* Prepare the compiled binary for upload */
 154         int size = program.compiled.size;
 155         dst = program.compiled.data;
 156
 157         /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
 158          * I bet someone just thought that would be a cute pun. At least,
 159          * that's how I'd do it. */
 160
 161         if (size) {
 162                 state->bo = pan_bo_create(dev, size, PAN_BO_EXECUTE);
 163                 memcpy(state->bo->cpu, dst, size);
 164         }
 165
 166         if (!(dev->quirks & IS_BIFROST)) {
 167                 /* If size = 0, no shader. Use dummy tag to avoid
 168                  * INSTR_INVALID_ENC */
 169                 state->first_tag = size ? program.first_tag : 1;
 170         }
 171
 172         util_dynarray_fini(&program.compiled);
 173
 174         state->sysval_count = program.sysval_count;
 175         memcpy(state->sysval, program.sysvals, sizeof(state->sysval[0]) * state->sysval_count);
 176
 177         bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID);
 178         bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID);
 179
 180         /* On Bifrost it's a sysval, on Midgard it's a varying */
 181         state->reads_frag_coord = s->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD);
 182
 183         state->writes_global = s->info.writes_memory;
 184
 185         switch (stage) {
 186         case MESA_SHADER_VERTEX:
 187                 state->attribute_count = util_bitcount64(s->info.inputs_read);
 188                 state->varying_count = util_bitcount64(s->info.outputs_written);
 189
 190                 if (vertex_id)
 191                         state->attribute_count = MAX2(state->attribute_count, PAN_VERTEX_ID + 1);
 192
 193                 if (instance_id)
 194                         state->attribute_count = MAX2(state->attribute_count, PAN_INSTANCE_ID + 1);
 195
 196                 break;
 197         case MESA_SHADER_FRAGMENT:
 198                 state->attribute_count = 0;
 199                 state->varying_count = util_bitcount64(s->info.inputs_read);
 200                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 201                         state->writes_depth = true;
 202                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
 203                         state->writes_stencil = true;
 204
 205                 /* List of reasons we need to execute frag shaders when things
 206                  * are masked off */
 207
 208                 state->fs_sidefx =
 209                         s->info.writes_memory ||
 210                         s->info.fs.uses_discard ||
 211                         s->info.fs.uses_demote;
 212                 break;
 213         case MESA_SHADER_COMPUTE:
 214                 /* TODO: images */
 215                 state->attribute_count = 0;
 216                 state->varying_count = 0;
 217                 state->shared_size = s->info.cs.shared_size;
 218                 break;
 219         default:
 220                 unreachable("Unknown shader state");
 221         }
 222
 223         state->can_discard = s->info.fs.uses_discard;
 224         state->writes_point_size = program.writes_point_size;
 225         state->reads_point_coord = false;
 226         state->helper_invocations = s->info.fs.needs_helper_invocations;
 227         state->stack_size = program.tls_size;
 228
 229         if (outputs_written)
 230                 *outputs_written = s->info.outputs_written;
 231
 232         /* Separate as primary uniform count is truncated. Sysvals are prefix
 233          * uniforms */
 234         state->uniform_count = s->num_uniforms + program.sysval_count;
 235         state->uniform_cutoff = program.uniform_cutoff;
 236         state->work_reg_count = program.work_register_count;
 237
 238         if (dev->quirks & IS_BIFROST)
 239                 for (unsigned i = 0; i < BIFROST_MAX_RENDER_TARGET_COUNT; i++)
 240                         state->blend_types[i] = bifrost_blend_type_from_nir(program.blend_types[i]);
 241
 242         unsigned default_vec1_swizzle;
 243         unsigned default_vec2_swizzle;
 244         unsigned default_vec4_swizzle;
 245
 246         if (dev->quirks & HAS_SWIZZLES) {
 247                 default_vec1_swizzle = panfrost_get_default_swizzle(1);
 248                 default_vec2_swizzle = panfrost_get_default_swizzle(2);
 249                 default_vec4_swizzle = panfrost_get_default_swizzle(4);
 250         } else {
 251                 default_vec1_swizzle = panfrost_bifrost_swizzle(1);
 252                 default_vec2_swizzle = panfrost_bifrost_swizzle(2);
 253                 default_vec4_swizzle = panfrost_bifrost_swizzle(4);
 254         }
 255
 256         /* Record the varying mapping for the command stream's bookkeeping */
 257
 258         unsigned p_varyings[32];
 259         enum mali_format p_varying_type[32];
 260
 261         struct exec_list *l_varyings =
 262                         stage == MESA_SHADER_VERTEX ? &s->outputs : &s->inputs;
 263
 264         nir_foreach_variable(var, l_varyings) {
 265                 unsigned loc = var->data.driver_location;
 266                 unsigned sz = glsl_count_attribute_slots(var->type, FALSE);
 267
 268                 for (int c = 0; c < sz; ++c) {
 269                         p_varyings[loc + c] = var->data.location + c;
 270                         p_varying_type[loc + c] = pan_format_from_glsl(var->type);
 271                 }
 272         }
 273
 274         /* Iterate the varyings and emit the corresponding descriptor */
 275         for (unsigned i = 0; i < state->varying_count; ++i) {
 276                 unsigned location = p_varyings[i];
 277
 278                 /* Default to a vec4 varying */
 279                 struct mali_attr_meta v = {
 280                         .format = p_varying_type[i],
 281                         .swizzle = default_vec4_swizzle,
 282                         .unknown1 = dev->quirks & IS_BIFROST ? 0x0 : 0x2,
 283                 };
 284
 285                 /* Check for special cases, otherwise assume general varying */
 286
 287                 if (location == VARYING_SLOT_POS) {
 288                         if (stage == MESA_SHADER_FRAGMENT)
 289                                 state->reads_frag_coord = true;
 290                         else
 291                                 v.format = MALI_VARYING_POS;
 292                 } else if (location == VARYING_SLOT_PSIZ) {
 293                         v.format = MALI_R16F;
 294                         v.swizzle = default_vec1_swizzle;
 295
 296                         state->writes_point_size = true;
 297                 } else if (location == VARYING_SLOT_PNTC) {
 298                         v.format = MALI_RG16F;
 299                         v.swizzle = default_vec2_swizzle;
 300
 301                         state->reads_point_coord = true;
 302                 } else if (location == VARYING_SLOT_FACE) {
 303                         v.format = MALI_R32I;
 304                         v.swizzle = default_vec1_swizzle;
 305
 306                         state->reads_face = true;
 307                 }
 308
 309                 state->varyings[i] = v;
 310                 state->varyings_loc[i] = location;
 311         }
 312 }