src/gallium/drivers/panfrost/pan_assemble.c

   1 /*
   2  * © Copyright 2018 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include "pan_bo.h"
  29 #include "pan_context.h"
  30 #include "pan_util.h"
  31 #include "panfrost-quirks.h"
  32
  33 #include "compiler/nir/nir.h"
  34 #include "nir/tgsi_to_nir.h"
  35 #include "midgard/midgard_compile.h"
  36 #include "bifrost/bifrost_compile.h"
  37 #include "util/u_dynarray.h"
  38
  39 #include "tgsi/tgsi_dump.h"
  40
  41 static unsigned
  42 pan_format_from_nir_base(nir_alu_type base)
  43 {
  44         switch (base) {
  45         case nir_type_int:
  46                 return MALI_FORMAT_SINT;
  47         case nir_type_uint:
  48         case nir_type_bool:
  49                 return MALI_FORMAT_UINT;
  50         case nir_type_float:
  51                 return MALI_CHANNEL_FLOAT;
  52         default:
  53                 unreachable("Invalid base");
  54         }
  55 }
  56
  57 static unsigned
  58 pan_format_from_nir_size(nir_alu_type base, unsigned size)
  59 {
  60         if (base == nir_type_float) {
  61                 switch (size) {
  62                 case 16: return MALI_FORMAT_SINT;
  63                 case 32: return MALI_FORMAT_UNORM;
  64                 default:
  65                         unreachable("Invalid float size for format");
  66                 }
  67         } else {
  68                 switch (size) {
  69                 case 1:
  70                 case 8:  return MALI_CHANNEL_8;
  71                 case 16: return MALI_CHANNEL_16;
  72                 case 32: return MALI_CHANNEL_32;
  73                 default:
  74                          unreachable("Invalid int size for format");
  75                 }
  76         }
  77 }
  78
  79 static enum mali_format
  80 pan_format_from_glsl(const struct glsl_type *type, unsigned frac)
  81 {
  82         const struct glsl_type *column = glsl_without_array_or_matrix(type);
  83         enum glsl_base_type glsl_base = glsl_get_base_type(column);
  84         nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
  85         unsigned chan = glsl_get_components(column);
  86
  87         /* If we have a fractional location added, we need to increase the size
  88          * so it will fit, i.e. a vec3 in YZW requires us to allocate a vec4.
  89          * We could do better but this is an edge case as it is, normally
  90          * packed varyings will be aligned. */
  91         chan += frac;
  92
  93         assert(chan >= 1 && chan <= 4);
  94
  95         unsigned base = nir_alu_type_get_base_type(t);
  96         unsigned size = nir_alu_type_get_type_size(t);
  97
  98         return pan_format_from_nir_base(base) |
  99                 pan_format_from_nir_size(base, size) |
 100                 MALI_NR_CHANNELS(chan);
 101 }
 102
 103 static enum bifrost_shader_type
 104 bifrost_blend_type_from_nir(nir_alu_type nir_type)
 105 {
 106         switch(nir_type) {
 107         case 0: /* Render target not in use */
 108                 return 0;
 109         case nir_type_float16:
 110                 return BIFROST_BLEND_F16;
 111         case nir_type_float32:
 112                 return BIFROST_BLEND_F32;
 113         case nir_type_int32:
 114                 return BIFROST_BLEND_I32;
 115         case nir_type_uint32:
 116                 return BIFROST_BLEND_U32;
 117         case nir_type_int16:
 118                 return BIFROST_BLEND_I16;
 119         case nir_type_uint16:
 120                 return BIFROST_BLEND_U16;
 121         default:
 122                 DBG("Unsupported blend shader type for NIR alu type %d", nir_type);
 123                 assert(0);
 124                 return 0;
 125         }
 126 }
 127
 128 void
 129 panfrost_shader_compile(struct panfrost_context *ctx,
 130                         enum pipe_shader_ir ir_type,
 131                         const void *ir,
 132                         gl_shader_stage stage,
 133                         struct panfrost_shader_state *state,
 134                         uint64_t *outputs_written)
 135 {
 136         struct panfrost_device *dev = pan_device(ctx->base.screen);
 137         uint8_t *dst;
 138
 139         nir_shader *s;
 140
 141         if (ir_type == PIPE_SHADER_IR_NIR) {
 142                 s = nir_shader_clone(NULL, ir);
 143         } else {
 144                 assert (ir_type == PIPE_SHADER_IR_TGSI);
 145                 s = tgsi_to_nir(ir, ctx->base.screen, false);
 146         }
 147
 148         s->info.stage = stage;
 149
 150         /* Call out to Midgard compiler given the above NIR */
 151
 152         panfrost_program program = {
 153                 .alpha_ref = state->alpha_state.ref_value
 154         };
 155
 156         if (dev->quirks & IS_BIFROST) {
 157                 bifrost_compile_shader_nir(s, &program, dev->gpu_id);
 158         } else {
 159                 midgard_compile_shader_nir(s, &program, false, 0, dev->gpu_id,
 160                                 pan_debug & PAN_DBG_PRECOMPILE);
 161         }
 162
 163         /* Prepare the compiled binary for upload */
 164         int size = program.compiled.size;
 165         dst = program.compiled.data;
 166
 167         /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
 168          * I bet someone just thought that would be a cute pun. At least,
 169          * that's how I'd do it. */
 170
 171         if (size) {
 172                 state->bo = pan_bo_create(dev, size, PAN_BO_EXECUTE);
 173                 memcpy(state->bo->cpu, dst, size);
 174         }
 175
 176         if (!(dev->quirks & IS_BIFROST)) {
 177                 /* If size = 0, no shader. Use dummy tag to avoid
 178                  * INSTR_INVALID_ENC */
 179                 state->first_tag = size ? program.first_tag : 1;
 180         }
 181
 182         util_dynarray_fini(&program.compiled);
 183
 184         state->sysval_count = program.sysval_count;
 185         memcpy(state->sysval, program.sysvals, sizeof(state->sysval[0]) * state->sysval_count);
 186
 187         bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID);
 188         bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID);
 189
 190         /* On Bifrost it's a sysval, on Midgard it's a varying */
 191         state->reads_frag_coord = s->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD);
 192
 193         state->writes_global = s->info.writes_memory;
 194
 195         switch (stage) {
 196         case MESA_SHADER_VERTEX:
 197                 state->attribute_count = util_bitcount64(s->info.inputs_read);
 198                 state->varying_count = util_bitcount64(s->info.outputs_written);
 199
 200                 if (vertex_id)
 201                         state->attribute_count = MAX2(state->attribute_count, PAN_VERTEX_ID + 1);
 202
 203                 if (instance_id)
 204                         state->attribute_count = MAX2(state->attribute_count, PAN_INSTANCE_ID + 1);
 205
 206                 break;
 207         case MESA_SHADER_FRAGMENT:
 208                 state->attribute_count = 0;
 209                 state->varying_count = util_bitcount64(s->info.inputs_read);
 210                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 211                         state->writes_depth = true;
 212                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
 213                         state->writes_stencil = true;
 214
 215                 /* List of reasons we need to execute frag shaders when things
 216                  * are masked off */
 217
 218                 state->fs_sidefx =
 219                         s->info.writes_memory ||
 220                         s->info.fs.uses_discard ||
 221                         s->info.fs.uses_demote;
 222                 break;
 223         case MESA_SHADER_COMPUTE:
 224                 /* TODO: images */
 225                 state->attribute_count = 0;
 226                 state->varying_count = 0;
 227                 state->shared_size = s->info.cs.shared_size;
 228                 break;
 229         default:
 230                 unreachable("Unknown shader state");
 231         }
 232
 233         state->can_discard = s->info.fs.uses_discard;
 234         state->helper_invocations = s->info.fs.needs_helper_invocations;
 235         state->stack_size = program.tls_size;
 236
 237         state->reads_frag_coord = s->info.inputs_read & (1 << VARYING_SLOT_POS);
 238         state->reads_point_coord = s->info.inputs_read & (1 << VARYING_SLOT_PNTC);
 239         state->reads_face = s->info.inputs_read & (1 << VARYING_SLOT_FACE);
 240         state->writes_point_size = s->info.outputs_written & (1 << VARYING_SLOT_PSIZ);
 241
 242         if (outputs_written)
 243                 *outputs_written = s->info.outputs_written;
 244
 245         /* Separate as primary uniform count is truncated. Sysvals are prefix
 246          * uniforms */
 247         state->uniform_count = s->num_uniforms + program.sysval_count;
 248         state->uniform_cutoff = program.uniform_cutoff;
 249         state->work_reg_count = program.work_register_count;
 250
 251         if (dev->quirks & IS_BIFROST)
 252                 for (unsigned i = 0; i < BIFROST_MAX_RENDER_TARGET_COUNT; i++)
 253                         state->blend_types[i] = bifrost_blend_type_from_nir(program.blend_types[i]);
 254
 255         /* Record the varying mapping for the command stream's bookkeeping */
 256
 257         struct exec_list *l_varyings =
 258                         stage == MESA_SHADER_VERTEX ? &s->outputs : &s->inputs;
 259
 260         nir_foreach_variable(var, l_varyings) {
 261                 unsigned loc = var->data.driver_location;
 262                 unsigned sz = glsl_count_attribute_slots(var->type, FALSE);
 263
 264                 for (int c = 0; c < sz; ++c) {
 265                         state->varyings_loc[loc + c] = var->data.location + c;
 266                         state->varyings[loc + c] = pan_format_from_glsl(var->type, var->data.location_frac);
 267                 }
 268         }
 269 }