2 * Copyright (C) 2018 Alyssa Rosenzweig
3 * Copyright (C) 2020 Collabora Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "util/macros.h"
26 #include "util/u_prim.h"
27 #include "util/u_vbuf.h"
29 #include "panfrost-quirks.h"
33 #include "pan_cmdstream.h"
34 #include "pan_context.h"
37 /* If a BO is accessed for a particular shader stage, will it be in the primary
38 * batch (vertex/tiler) or the secondary batch (fragment)? Anything but
39 * fragment will be primary, e.g. compute jobs will be considered
40 * "vertex/tiler" by analogy */
42 static inline uint32_t
43 panfrost_bo_access_for_stage(enum pipe_shader_type stage
)
45 assert(stage
== PIPE_SHADER_FRAGMENT
||
46 stage
== PIPE_SHADER_VERTEX
||
47 stage
== PIPE_SHADER_COMPUTE
);
49 return stage
== PIPE_SHADER_FRAGMENT
?
50 PAN_BO_ACCESS_FRAGMENT
:
51 PAN_BO_ACCESS_VERTEX_TILER
;
55 panfrost_vt_emit_shared_memory(struct panfrost_context
*ctx
,
56 struct mali_vertex_tiler_postfix
*postfix
)
58 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
59 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
61 struct mali_shared_memory shared
= {
62 .shared_workgroup_count
= ~0,
65 if (batch
->stack_size
) {
66 struct panfrost_bo
*stack
=
67 panfrost_batch_get_scratchpad(batch
, batch
->stack_size
,
68 dev
->thread_tls_alloc
,
71 shared
.stack_shift
= panfrost_get_stack_shift(batch
->stack_size
);
72 shared
.scratchpad
= stack
->gpu
;
75 postfix
->shared_memory
= panfrost_pool_upload(&batch
->pool
, &shared
, sizeof(shared
));
79 panfrost_vt_attach_framebuffer(struct panfrost_context
*ctx
,
80 struct mali_vertex_tiler_postfix
*postfix
)
82 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
83 postfix
->shared_memory
= panfrost_batch_reserve_framebuffer(batch
);
87 panfrost_vt_update_rasterizer(struct panfrost_rasterizer
*rasterizer
,
88 struct mali_vertex_tiler_prefix
*prefix
,
89 struct mali_vertex_tiler_postfix
*postfix
)
91 postfix
->gl_enables
|= 0x7;
92 SET_BIT(postfix
->gl_enables
, MALI_FRONT_CCW_TOP
,
93 rasterizer
->base
.front_ccw
);
94 SET_BIT(postfix
->gl_enables
, MALI_CULL_FACE_FRONT
,
95 (rasterizer
->base
.cull_face
& PIPE_FACE_FRONT
));
96 SET_BIT(postfix
->gl_enables
, MALI_CULL_FACE_BACK
,
97 (rasterizer
->base
.cull_face
& PIPE_FACE_BACK
));
98 SET_BIT(prefix
->unknown_draw
, MALI_DRAW_FLATSHADE_FIRST
,
99 rasterizer
->base
.flatshade_first
);
103 panfrost_vt_update_primitive_size(struct panfrost_context
*ctx
,
104 struct mali_vertex_tiler_prefix
*prefix
,
105 union midgard_primitive_size
*primitive_size
)
107 struct panfrost_rasterizer
*rasterizer
= ctx
->rasterizer
;
109 if (!panfrost_writes_point_size(ctx
)) {
110 float val
= (prefix
->draw_mode
== MALI_DRAW_MODE_POINTS
) ?
111 rasterizer
->base
.point_size
:
112 rasterizer
->base
.line_width
;
114 primitive_size
->constant
= val
;
119 panfrost_vt_update_occlusion_query(struct panfrost_context
*ctx
,
120 struct mali_vertex_tiler_postfix
*postfix
)
122 SET_BIT(postfix
->gl_enables
, MALI_OCCLUSION_QUERY
, ctx
->occlusion_query
);
123 if (ctx
->occlusion_query
) {
124 postfix
->occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
125 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
126 PAN_BO_ACCESS_SHARED
|
128 PAN_BO_ACCESS_FRAGMENT
);
130 postfix
->occlusion_counter
= 0;
135 panfrost_vt_init(struct panfrost_context
*ctx
,
136 enum pipe_shader_type stage
,
137 struct mali_vertex_tiler_prefix
*prefix
,
138 struct mali_vertex_tiler_postfix
*postfix
)
140 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
142 if (!ctx
->shader
[stage
])
145 memset(prefix
, 0, sizeof(*prefix
));
146 memset(postfix
, 0, sizeof(*postfix
));
148 if (device
->quirks
& IS_BIFROST
) {
149 postfix
->gl_enables
= 0x2;
150 panfrost_vt_emit_shared_memory(ctx
, postfix
);
152 postfix
->gl_enables
= 0x6;
153 panfrost_vt_attach_framebuffer(ctx
, postfix
);
156 if (stage
== PIPE_SHADER_FRAGMENT
) {
157 panfrost_vt_update_occlusion_query(ctx
, postfix
);
158 panfrost_vt_update_rasterizer(ctx
->rasterizer
, prefix
, postfix
);
163 panfrost_translate_index_size(unsigned size
)
167 return MALI_DRAW_INDEXED_UINT8
;
170 return MALI_DRAW_INDEXED_UINT16
;
173 return MALI_DRAW_INDEXED_UINT32
;
176 unreachable("Invalid index size");
180 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
181 * good for the duration of the draw (transient), could last longer. Also get
182 * the bounds on the index buffer for the range accessed by the draw. We do
183 * these operations together because there are natural optimizations which
184 * require them to be together. */
187 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
,
188 const struct pipe_draw_info
*info
,
189 unsigned *min_index
, unsigned *max_index
)
191 struct panfrost_resource
*rsrc
= pan_resource(info
->index
.resource
);
192 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
193 off_t offset
= info
->start
* info
->index_size
;
194 bool needs_indices
= true;
197 if (info
->max_index
!= ~0u) {
198 *min_index
= info
->min_index
;
199 *max_index
= info
->max_index
;
200 needs_indices
= false;
203 if (!info
->has_user_indices
) {
204 /* Only resources can be directly mapped */
205 panfrost_batch_add_bo(batch
, rsrc
->bo
,
206 PAN_BO_ACCESS_SHARED
|
208 PAN_BO_ACCESS_VERTEX_TILER
);
209 out
= rsrc
->bo
->gpu
+ offset
;
211 /* Check the cache */
212 needs_indices
= !panfrost_minmax_cache_get(rsrc
->index_cache
,
218 /* Otherwise, we need to upload to transient memory */
219 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
220 struct panfrost_transfer T
=
221 panfrost_pool_alloc_aligned(&batch
->pool
,
222 info
->count
* info
->index_size
,
225 memcpy(T
.cpu
, ibuf8
+ offset
, info
->count
* info
->index_size
);
231 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
233 if (!info
->has_user_indices
)
234 panfrost_minmax_cache_add(rsrc
->index_cache
,
235 info
->start
, info
->count
,
236 *min_index
, *max_index
);
243 panfrost_vt_set_draw_info(struct panfrost_context
*ctx
,
244 const struct pipe_draw_info
*info
,
245 enum mali_draw_mode draw_mode
,
246 struct mali_vertex_tiler_postfix
*vertex_postfix
,
247 struct mali_vertex_tiler_prefix
*tiler_prefix
,
248 struct mali_vertex_tiler_postfix
*tiler_postfix
,
249 unsigned *vertex_count
,
250 unsigned *padded_count
)
252 tiler_prefix
->draw_mode
= draw_mode
;
254 unsigned draw_flags
= 0;
256 if (panfrost_writes_point_size(ctx
))
257 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
259 if (info
->primitive_restart
)
260 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
262 /* These doesn't make much sense */
264 draw_flags
|= 0x3000;
266 if (info
->index_size
) {
267 unsigned min_index
= 0, max_index
= 0;
269 tiler_prefix
->indices
= panfrost_get_index_buffer_bounded(ctx
,
274 /* Use the corresponding values */
275 *vertex_count
= max_index
- min_index
+ 1;
276 tiler_postfix
->offset_start
= vertex_postfix
->offset_start
= min_index
+ info
->index_bias
;
277 tiler_prefix
->offset_bias_correction
= -min_index
;
278 tiler_prefix
->index_count
= MALI_POSITIVE(info
->count
);
279 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
281 tiler_prefix
->indices
= 0;
282 *vertex_count
= ctx
->vertex_count
;
283 tiler_postfix
->offset_start
= vertex_postfix
->offset_start
= info
->start
;
284 tiler_prefix
->offset_bias_correction
= 0;
285 tiler_prefix
->index_count
= MALI_POSITIVE(ctx
->vertex_count
);
288 tiler_prefix
->unknown_draw
= draw_flags
;
290 /* Encode the padded vertex count */
292 if (info
->instance_count
> 1) {
293 *padded_count
= panfrost_padded_vertex_count(*vertex_count
);
295 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
296 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
298 tiler_postfix
->instance_shift
= vertex_postfix
->instance_shift
= shift
;
299 tiler_postfix
->instance_odd
= vertex_postfix
->instance_odd
= k
;
301 *padded_count
= *vertex_count
;
303 /* Reset instancing state */
304 tiler_postfix
->instance_shift
= vertex_postfix
->instance_shift
= 0;
305 tiler_postfix
->instance_odd
= vertex_postfix
->instance_odd
= 0;
310 panfrost_shader_meta_init(struct panfrost_context
*ctx
,
311 enum pipe_shader_type st
,
312 struct mali_shader_meta
*meta
)
314 const struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
315 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, st
);
317 memset(meta
, 0, sizeof(*meta
));
318 meta
->shader
= (ss
->bo
? ss
->bo
->gpu
: 0) | ss
->first_tag
;
319 meta
->attribute_count
= ss
->attribute_count
;
320 meta
->varying_count
= ss
->varying_count
;
321 meta
->texture_count
= ctx
->sampler_view_count
[st
];
322 meta
->sampler_count
= ctx
->sampler_count
[st
];
324 if (dev
->quirks
& IS_BIFROST
) {
325 if (st
== PIPE_SHADER_VERTEX
)
326 meta
->bifrost1
.unk1
= 0x800000;
328 /* First clause ATEST |= 0x4000000.
329 * Less than 32 regs |= 0x200 */
330 meta
->bifrost1
.unk1
= 0x950020;
333 meta
->bifrost1
.uniform_buffer_count
= panfrost_ubo_count(ctx
, st
);
334 if (st
== PIPE_SHADER_VERTEX
)
335 meta
->bifrost2
.preload_regs
= 0xC0;
337 meta
->bifrost2
.preload_regs
= 0x1;
338 SET_BIT(meta
->bifrost2
.preload_regs
, 0x10, ss
->reads_frag_coord
);
341 meta
->bifrost2
.uniform_count
= MIN2(ss
->uniform_count
,
344 meta
->midgard1
.uniform_count
= MIN2(ss
->uniform_count
,
346 meta
->midgard1
.work_count
= ss
->work_reg_count
;
348 /* TODO: This is not conformant on ES3 */
349 meta
->midgard1
.flags_hi
= MALI_SUPPRESS_INF_NAN
;
351 meta
->midgard1
.flags_lo
= 0x20;
352 meta
->midgard1
.uniform_buffer_count
= panfrost_ubo_count(ctx
, st
);
354 SET_BIT(meta
->midgard1
.flags_lo
, MALI_WRITES_GLOBAL
, ss
->writes_global
);
359 translate_tex_wrap(enum pipe_tex_wrap w
)
362 case PIPE_TEX_WRAP_REPEAT
: return MALI_WRAP_MODE_REPEAT
;
363 case PIPE_TEX_WRAP_CLAMP
: return MALI_WRAP_MODE_CLAMP
;
364 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
: return MALI_WRAP_MODE_CLAMP_TO_EDGE
;
365 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
: return MALI_WRAP_MODE_CLAMP_TO_BORDER
;
366 case PIPE_TEX_WRAP_MIRROR_REPEAT
: return MALI_WRAP_MODE_MIRRORED_REPEAT
;
367 case PIPE_TEX_WRAP_MIRROR_CLAMP
: return MALI_WRAP_MODE_MIRRORED_CLAMP
;
368 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE
;
369 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER
;
370 default: unreachable("Invalid wrap");
374 /* The hardware compares in the wrong order order, so we have to flip before
375 * encoding. Yes, really. */
377 static enum mali_func
378 panfrost_sampler_compare_func(const struct pipe_sampler_state
*cso
)
380 if (!cso
->compare_mode
)
381 return MALI_FUNC_NEVER
;
383 enum mali_func f
= panfrost_translate_compare_func(cso
->compare_func
);
384 return panfrost_flip_compare_func(f
);
387 static enum mali_mipmap_mode
388 pan_pipe_to_mipmode(enum pipe_tex_mipfilter f
)
391 case PIPE_TEX_MIPFILTER_NEAREST
: return MALI_MIPMAP_MODE_NEAREST
;
392 case PIPE_TEX_MIPFILTER_LINEAR
: return MALI_MIPMAP_MODE_TRILINEAR
;
393 case PIPE_TEX_MIPFILTER_NONE
: return MALI_MIPMAP_MODE_NONE
;
394 default: unreachable("Invalid");
398 void panfrost_sampler_desc_init(const struct pipe_sampler_state
*cso
,
399 struct mali_midgard_sampler_packed
*hw
)
401 pan_pack(hw
, MIDGARD_SAMPLER
, cfg
) {
402 cfg
.magnify_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
403 cfg
.minify_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
404 cfg
.mipmap_mode
= (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
) ?
405 MALI_MIPMAP_MODE_TRILINEAR
: MALI_MIPMAP_MODE_NEAREST
;
406 cfg
.normalized_coordinates
= cso
->normalized_coords
;
408 cfg
.lod_bias
= FIXED_16(cso
->lod_bias
, true);
410 cfg
.minimum_lod
= FIXED_16(cso
->min_lod
, false);
412 /* If necessary, we disable mipmapping in the sampler descriptor by
413 * clamping the LOD as tight as possible (from 0 to epsilon,
414 * essentially -- remember these are fixed point numbers, so
417 cfg
.maximum_lod
= (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) ?
418 cfg
.minimum_lod
+ 1 :
419 FIXED_16(cso
->max_lod
, false);
421 cfg
.wrap_mode_s
= translate_tex_wrap(cso
->wrap_s
);
422 cfg
.wrap_mode_t
= translate_tex_wrap(cso
->wrap_t
);
423 cfg
.wrap_mode_r
= translate_tex_wrap(cso
->wrap_r
);
425 cfg
.compare_function
= panfrost_sampler_compare_func(cso
);
426 cfg
.seamless_cube_map
= cso
->seamless_cube_map
;
428 cfg
.border_color_r
= cso
->border_color
.f
[0];
429 cfg
.border_color_g
= cso
->border_color
.f
[1];
430 cfg
.border_color_b
= cso
->border_color
.f
[2];
431 cfg
.border_color_a
= cso
->border_color
.f
[3];
435 void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state
*cso
,
436 struct mali_bifrost_sampler_packed
*hw
)
438 pan_pack(hw
, BIFROST_SAMPLER
, cfg
) {
439 cfg
.magnify_linear
= cso
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
;
440 cfg
.minify_linear
= cso
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
;
441 cfg
.mipmap_mode
= pan_pipe_to_mipmode(cso
->min_mip_filter
);
442 cfg
.normalized_coordinates
= cso
->normalized_coords
;
444 cfg
.lod_bias
= FIXED_16(cso
->lod_bias
, true);
445 cfg
.minimum_lod
= FIXED_16(cso
->min_lod
, false);
446 cfg
.maximum_lod
= FIXED_16(cso
->max_lod
, false);
448 cfg
.wrap_mode_s
= translate_tex_wrap(cso
->wrap_s
);
449 cfg
.wrap_mode_t
= translate_tex_wrap(cso
->wrap_t
);
450 cfg
.wrap_mode_r
= translate_tex_wrap(cso
->wrap_r
);
452 cfg
.compare_function
= panfrost_sampler_compare_func(cso
);
453 cfg
.seamless_cube_map
= cso
->seamless_cube_map
;
458 panfrost_frag_meta_rasterizer_update(struct panfrost_context
*ctx
,
459 struct mali_shader_meta
*fragmeta
)
461 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
463 bool msaa
= rast
->multisample
;
465 /* TODO: Sample size */
466 SET_BIT(fragmeta
->unknown2_3
, MALI_HAS_MSAA
, msaa
);
467 SET_BIT(fragmeta
->unknown2_4
, MALI_NO_MSAA
, !msaa
);
469 struct panfrost_shader_state
*fs
;
470 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
472 /* EXT_shader_framebuffer_fetch requires the shader to be run
473 * per-sample when outputs are read. */
474 bool per_sample
= ctx
->min_samples
> 1 || fs
->outputs_read
;
475 SET_BIT(fragmeta
->unknown2_3
, MALI_PER_SAMPLE
, msaa
&& per_sample
);
477 fragmeta
->depth_units
= rast
->offset_units
* 2.0f
;
478 fragmeta
->depth_factor
= rast
->offset_scale
;
480 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
482 SET_BIT(fragmeta
->unknown2_4
, MALI_DEPTH_RANGE_A
, rast
->offset_tri
);
483 SET_BIT(fragmeta
->unknown2_4
, MALI_DEPTH_RANGE_B
, rast
->offset_tri
);
485 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_CLIP_NEAR
, rast
->depth_clip_near
);
486 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_CLIP_FAR
, rast
->depth_clip_far
);
490 panfrost_frag_meta_zsa_update(struct panfrost_context
*ctx
,
491 struct mali_shader_meta
*fragmeta
)
493 const struct panfrost_zsa_state
*so
= ctx
->depth_stencil
;
495 SET_BIT(fragmeta
->unknown2_4
, MALI_STENCIL_TEST
,
496 so
->base
.stencil
[0].enabled
);
498 fragmeta
->stencil_mask_front
= so
->stencil_mask_front
;
499 fragmeta
->stencil_mask_back
= so
->stencil_mask_back
;
501 /* Bottom bits for stencil ref, exactly one word */
502 fragmeta
->stencil_front
.opaque
[0] = so
->stencil_front
.opaque
[0] | ctx
->stencil_ref
.ref_value
[0];
504 /* If back-stencil is not enabled, use the front values */
506 if (so
->base
.stencil
[1].enabled
)
507 fragmeta
->stencil_back
.opaque
[0] = so
->stencil_back
.opaque
[0] | ctx
->stencil_ref
.ref_value
[1];
509 fragmeta
->stencil_back
= fragmeta
->stencil_front
;
511 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_WRITEMASK
,
512 so
->base
.depth
.writemask
);
514 fragmeta
->unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
515 fragmeta
->unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(
516 so
->base
.depth
.enabled
? so
->base
.depth
.func
: PIPE_FUNC_ALWAYS
));
520 panfrost_fs_required(
521 struct panfrost_shader_state
*fs
,
522 struct panfrost_blend_final
*blend
,
525 /* If we generally have side effects */
529 /* If colour is written we need to execute */
530 for (unsigned i
= 0; i
< rt_count
; ++i
) {
531 if (!blend
[i
].no_colour
)
535 /* If depth is written and not implied we need to execute.
536 * TODO: Predicate on Z/S writes being enabled */
537 return (fs
->writes_depth
|| fs
->writes_stencil
);
541 panfrost_frag_meta_blend_update(struct panfrost_context
*ctx
,
542 struct mali_shader_meta
*fragmeta
,
545 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
546 const struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
547 struct panfrost_shader_state
*fs
;
548 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
550 SET_BIT(fragmeta
->unknown2_4
, MALI_NO_DITHER
,
551 (dev
->quirks
& MIDGARD_SFBD
) && ctx
->blend
&&
552 !ctx
->blend
->base
.dither
);
554 SET_BIT(fragmeta
->unknown2_4
, MALI_ALPHA_TO_COVERAGE
,
555 ctx
->blend
->base
.alpha_to_coverage
);
557 /* Get blending setup */
558 unsigned rt_count
= ctx
->pipe_framebuffer
.nr_cbufs
;
560 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
562 for (unsigned c
= 0; c
< rt_count
; ++c
)
563 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
565 /* Disable shader execution if we can */
566 if (dev
->quirks
& MIDGARD_SHADERLESS
567 && !panfrost_fs_required(fs
, blend
, rt_count
)) {
568 fragmeta
->shader
= 0;
569 fragmeta
->attribute_count
= 0;
570 fragmeta
->varying_count
= 0;
571 fragmeta
->texture_count
= 0;
572 fragmeta
->sampler_count
= 0;
574 /* This feature is not known to work on Bifrost */
575 fragmeta
->midgard1
.work_count
= 1;
576 fragmeta
->midgard1
.uniform_count
= 0;
577 fragmeta
->midgard1
.uniform_buffer_count
= 0;
580 /* If there is a blend shader, work registers are shared. We impose 8
581 * work registers as a limit for blend shaders. Should be lower XXX */
583 if (!(dev
->quirks
& IS_BIFROST
)) {
584 for (unsigned c
= 0; c
< rt_count
; ++c
) {
585 if (blend
[c
].is_shader
) {
586 fragmeta
->midgard1
.work_count
=
587 MAX2(fragmeta
->midgard1
.work_count
, 8);
592 /* Even on MFBD, the shader descriptor gets blend shaders. It's *also*
593 * copied to the blend_meta appended (by convention), but this is the
594 * field actually read by the hardware. (Or maybe both are read...?).
595 * Specify the last RTi with a blend shader. */
597 fragmeta
->blend
.shader
= 0;
599 for (signed rt
= ((signed) rt_count
- 1); rt
>= 0; --rt
) {
600 if (!blend
[rt
].is_shader
)
603 fragmeta
->blend
.shader
= blend
[rt
].shader
.gpu
|
604 blend
[rt
].shader
.first_tag
;
608 if (dev
->quirks
& MIDGARD_SFBD
) {
609 /* When only a single render target platform is used, the blend
610 * information is inside the shader meta itself. We additionally
611 * need to signal CAN_DISCARD for nontrivial blend modes (so
612 * we're able to read back the destination buffer) */
614 SET_BIT(fragmeta
->unknown2_3
, MALI_HAS_BLEND_SHADER
,
617 if (!blend
[0].is_shader
) {
618 fragmeta
->blend
.equation
= *blend
[0].equation
.equation
;
619 fragmeta
->blend
.constant
= blend
[0].equation
.constant
;
622 SET_BIT(fragmeta
->unknown2_3
, MALI_CAN_DISCARD
,
623 !blend
[0].no_blending
|| fs
->can_discard
);
625 batch
->draws
|= PIPE_CLEAR_COLOR0
;
629 if (dev
->quirks
& IS_BIFROST
) {
630 bool no_blend
= true;
632 for (unsigned i
= 0; i
< rt_count
; ++i
)
633 no_blend
&= (blend
[i
].no_blending
| blend
[i
].no_colour
);
635 SET_BIT(fragmeta
->bifrost1
.unk1
, MALI_BIFROST_EARLY_Z
,
636 !fs
->can_discard
&& !fs
->writes_depth
&& no_blend
);
639 /* Additional blend descriptor tacked on for jobs using MFBD */
641 struct bifrost_blend_rt
*brts
= rts
;
642 struct midgard_blend_rt
*mrts
= rts
;
644 /* Disable blending for depth-only on Bifrost */
646 if (rt_count
== 0 && dev
->quirks
& IS_BIFROST
)
649 for (unsigned i
= 0; i
< rt_count
; ++i
) {
652 if (!blend
[i
].no_colour
) {
654 batch
->draws
|= (PIPE_CLEAR_COLOR0
<< i
);
656 bool is_srgb
= util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
658 SET_BIT(flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
659 SET_BIT(flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
660 SET_BIT(flags
, MALI_BLEND_SRGB
, is_srgb
);
661 SET_BIT(flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
664 if (dev
->quirks
& IS_BIFROST
) {
665 brts
[i
].flags
= flags
;
667 if (blend
[i
].is_shader
) {
668 /* The blend shader's address needs to be at
669 * the same top 32 bit as the fragment shader.
670 * TODO: Ensure that's always the case.
672 assert((blend
[i
].shader
.gpu
& (0xffffffffull
<< 32)) ==
673 (fs
->bo
->gpu
& (0xffffffffull
<< 32)));
674 brts
[i
].shader
= blend
[i
].shader
.gpu
;
677 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
678 const struct util_format_description
*format_desc
;
679 format_desc
= util_format_description(format
);
681 brts
[i
].equation
= *blend
[i
].equation
.equation
;
683 /* TODO: this is a bit more complicated */
684 brts
[i
].constant
= blend
[i
].equation
.constant
;
686 brts
[i
].format
= panfrost_format_to_bifrost_blend(format_desc
);
688 /* 0x19 disables blending and forces REPLACE
689 * mode (equivalent to rgb_mode = alpha_mode =
690 * x122, colour mask = 0xF). 0x1a allows
692 brts
[i
].unk2
= blend
[i
].no_blending
? 0x19 : 0x1a;
694 brts
[i
].shader_type
= fs
->blend_types
[i
];
697 mrts
[i
].flags
= flags
;
699 if (blend
[i
].is_shader
) {
700 mrts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
702 mrts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
703 mrts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
710 panfrost_frag_shader_meta_init(struct panfrost_context
*ctx
,
711 struct mali_shader_meta
*fragmeta
,
714 const struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
715 struct panfrost_shader_state
*fs
;
717 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
719 bool msaa
= ctx
->rasterizer
->base
.multisample
;
720 fragmeta
->coverage_mask
= msaa
? ctx
->sample_mask
: ~0;
722 fragmeta
->unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x10;
723 fragmeta
->unknown2_4
= 0x4e0;
725 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this
726 * is required (independent of 32-bit/64-bit descriptors), or why it's
727 * not used on later GPU revisions. Otherwise, all shader jobs fault on
728 * these earlier chips (perhaps this is a chicken bit of some kind).
729 * More investigation is needed. */
731 SET_BIT(fragmeta
->unknown2_4
, 0x10, dev
->quirks
& MIDGARD_SFBD
);
733 if (dev
->quirks
& IS_BIFROST
) {
736 /* Depending on whether it's legal to in the given shader, we try to
737 * enable early-z testing. TODO: respect e-z force */
739 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_EARLY_Z
,
740 !fs
->can_discard
&& !fs
->writes_global
&&
741 !fs
->writes_depth
&& !fs
->writes_stencil
&&
742 !ctx
->blend
->base
.alpha_to_coverage
);
744 /* Add the writes Z/S flags if needed. */
745 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_WRITES_Z
, fs
->writes_depth
);
746 SET_BIT(fragmeta
->midgard1
.flags_hi
, MALI_WRITES_S
, fs
->writes_stencil
);
748 /* Any time texturing is used, derivatives are implicitly calculated,
749 * so we need to enable helper invocations */
751 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
,
752 fs
->helper_invocations
);
754 /* If discard is enabled, which bit we set to convey this
755 * depends on if depth/stencil is used for the draw or not.
756 * Just one of depth OR stencil is enough to trigger this. */
758 const struct pipe_depth_stencil_alpha_state
*zsa
= &ctx
->depth_stencil
->base
;
760 fs
->writes_depth
|| fs
->writes_stencil
||
761 (zsa
->depth
.enabled
&& zsa
->depth
.func
!= PIPE_FUNC_ALWAYS
) ||
762 zsa
->stencil
[0].enabled
;
764 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_READS_TILEBUFFER
,
765 fs
->outputs_read
|| (!zs_enabled
&& fs
->can_discard
));
766 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_READS_ZS
, zs_enabled
&& fs
->can_discard
);
769 panfrost_frag_meta_rasterizer_update(ctx
, fragmeta
);
770 panfrost_frag_meta_zsa_update(ctx
, fragmeta
);
771 panfrost_frag_meta_blend_update(ctx
, fragmeta
, rts
);
775 panfrost_emit_shader_meta(struct panfrost_batch
*batch
,
776 enum pipe_shader_type st
,
777 struct mali_vertex_tiler_postfix
*postfix
)
779 struct panfrost_context
*ctx
= batch
->ctx
;
780 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, st
);
787 struct mali_shader_meta meta
;
789 panfrost_shader_meta_init(ctx
, st
, &meta
);
791 /* Add the shader BO to the batch. */
792 panfrost_batch_add_bo(batch
, ss
->bo
,
793 PAN_BO_ACCESS_PRIVATE
|
795 panfrost_bo_access_for_stage(st
));
799 if (st
== PIPE_SHADER_FRAGMENT
) {
800 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
801 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
802 size_t desc_size
= sizeof(meta
);
804 struct panfrost_transfer xfer
;
807 if (dev
->quirks
& MIDGARD_SFBD
)
809 else if (dev
->quirks
& IS_BIFROST
)
810 rt_size
= sizeof(struct bifrost_blend_rt
);
812 rt_size
= sizeof(struct midgard_blend_rt
);
814 desc_size
+= rt_size
* rt_count
;
817 rts
= rzalloc_size(ctx
, rt_size
* rt_count
);
819 panfrost_frag_shader_meta_init(ctx
, &meta
, rts
);
821 xfer
= panfrost_pool_alloc_aligned(&batch
->pool
, desc_size
, sizeof(meta
));
823 memcpy(xfer
.cpu
, &meta
, sizeof(meta
));
824 memcpy(xfer
.cpu
+ sizeof(meta
), rts
, rt_size
* rt_count
);
829 shader_ptr
= xfer
.gpu
;
831 shader_ptr
= panfrost_pool_upload(&batch
->pool
, &meta
,
835 postfix
->shader
= shader_ptr
;
839 panfrost_emit_viewport(struct panfrost_batch
*batch
,
840 struct mali_vertex_tiler_postfix
*tiler_postfix
)
842 struct panfrost_context
*ctx
= batch
->ctx
;
843 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
844 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
845 const struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
846 const struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
848 /* Derive min/max from translate/scale. Note since |x| >= 0 by
849 * definition, we have that -|x| <= |x| hence translate - |scale| <=
850 * translate + |scale|, so the ordering is correct here. */
851 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
852 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
853 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
854 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
855 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
856 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
858 /* Scissor to the intersection of viewport and to the scissor, clamped
859 * to the framebuffer */
861 unsigned minx
= MIN2(fb
->width
, vp_minx
);
862 unsigned maxx
= MIN2(fb
->width
, vp_maxx
);
863 unsigned miny
= MIN2(fb
->height
, vp_miny
);
864 unsigned maxy
= MIN2(fb
->height
, vp_maxy
);
866 if (ss
&& rast
->scissor
) {
867 minx
= MAX2(ss
->minx
, minx
);
868 miny
= MAX2(ss
->miny
, miny
);
869 maxx
= MIN2(ss
->maxx
, maxx
);
870 maxy
= MIN2(ss
->maxy
, maxy
);
873 struct panfrost_transfer T
= panfrost_pool_alloc(&batch
->pool
, MALI_VIEWPORT_LENGTH
);
875 pan_pack(T
.cpu
, VIEWPORT
, cfg
) {
876 cfg
.scissor_minimum_x
= minx
;
877 cfg
.scissor_minimum_y
= miny
;
878 cfg
.scissor_maximum_x
= maxx
- 1;
879 cfg
.scissor_maximum_y
= maxy
- 1;
881 cfg
.minimum_z
= rast
->depth_clip_near
? minz
: -INFINITY
;
882 cfg
.maximum_z
= rast
->depth_clip_far
? maxz
: INFINITY
;
885 tiler_postfix
->viewport
= T
.gpu
;
886 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
890 panfrost_map_constant_buffer_gpu(struct panfrost_batch
*batch
,
891 enum pipe_shader_type st
,
892 struct panfrost_constant_buffer
*buf
,
895 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
896 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
899 panfrost_batch_add_bo(batch
, rsrc
->bo
,
900 PAN_BO_ACCESS_SHARED
|
902 panfrost_bo_access_for_stage(st
));
904 /* Alignment gauranteed by
905 * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
906 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
907 } else if (cb
->user_buffer
) {
908 return panfrost_pool_upload(&batch
->pool
,
913 unreachable("No constant buffer");
917 struct sysval_uniform
{
927 panfrost_upload_viewport_scale_sysval(struct panfrost_batch
*batch
,
928 struct sysval_uniform
*uniform
)
930 struct panfrost_context
*ctx
= batch
->ctx
;
931 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
933 uniform
->f
[0] = vp
->scale
[0];
934 uniform
->f
[1] = vp
->scale
[1];
935 uniform
->f
[2] = vp
->scale
[2];
939 panfrost_upload_viewport_offset_sysval(struct panfrost_batch
*batch
,
940 struct sysval_uniform
*uniform
)
942 struct panfrost_context
*ctx
= batch
->ctx
;
943 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
945 uniform
->f
[0] = vp
->translate
[0];
946 uniform
->f
[1] = vp
->translate
[1];
947 uniform
->f
[2] = vp
->translate
[2];
950 static void panfrost_upload_txs_sysval(struct panfrost_batch
*batch
,
951 enum pipe_shader_type st
,
952 unsigned int sysvalid
,
953 struct sysval_uniform
*uniform
)
955 struct panfrost_context
*ctx
= batch
->ctx
;
956 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
957 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
958 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
959 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
962 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
965 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
966 tex
->u
.tex
.first_level
);
969 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
970 tex
->u
.tex
.first_level
);
973 uniform
->i
[dim
] = tex
->texture
->array_size
;
977 panfrost_upload_ssbo_sysval(struct panfrost_batch
*batch
,
978 enum pipe_shader_type st
,
980 struct sysval_uniform
*uniform
)
982 struct panfrost_context
*ctx
= batch
->ctx
;
984 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
985 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
987 /* Compute address */
988 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
990 panfrost_batch_add_bo(batch
, bo
,
991 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
992 panfrost_bo_access_for_stage(st
));
994 /* Upload address and size as sysval */
995 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
996 uniform
->u
[2] = sb
.buffer_size
;
1000 panfrost_upload_sampler_sysval(struct panfrost_batch
*batch
,
1001 enum pipe_shader_type st
,
1003 struct sysval_uniform
*uniform
)
1005 struct panfrost_context
*ctx
= batch
->ctx
;
1006 struct pipe_sampler_state
*sampl
= &ctx
->samplers
[st
][samp_idx
]->base
;
1008 uniform
->f
[0] = sampl
->min_lod
;
1009 uniform
->f
[1] = sampl
->max_lod
;
1010 uniform
->f
[2] = sampl
->lod_bias
;
1012 /* Even without any errata, Midgard represents "no mipmapping" as
1013 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
1014 * panfrost_create_sampler_state which also explains our choice of
1015 * epsilon value (again to keep behaviour consistent) */
1017 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1018 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
1022 panfrost_upload_num_work_groups_sysval(struct panfrost_batch
*batch
,
1023 struct sysval_uniform
*uniform
)
1025 struct panfrost_context
*ctx
= batch
->ctx
;
1027 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
1028 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
1029 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
1033 panfrost_upload_sysvals(struct panfrost_batch
*batch
, void *buf
,
1034 struct panfrost_shader_state
*ss
,
1035 enum pipe_shader_type st
)
1037 struct sysval_uniform
*uniforms
= (void *)buf
;
1039 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1040 int sysval
= ss
->sysval
[i
];
1042 switch (PAN_SYSVAL_TYPE(sysval
)) {
1043 case PAN_SYSVAL_VIEWPORT_SCALE
:
1044 panfrost_upload_viewport_scale_sysval(batch
,
1047 case PAN_SYSVAL_VIEWPORT_OFFSET
:
1048 panfrost_upload_viewport_offset_sysval(batch
,
1051 case PAN_SYSVAL_TEXTURE_SIZE
:
1052 panfrost_upload_txs_sysval(batch
, st
,
1053 PAN_SYSVAL_ID(sysval
),
1056 case PAN_SYSVAL_SSBO
:
1057 panfrost_upload_ssbo_sysval(batch
, st
,
1058 PAN_SYSVAL_ID(sysval
),
1061 case PAN_SYSVAL_NUM_WORK_GROUPS
:
1062 panfrost_upload_num_work_groups_sysval(batch
,
1065 case PAN_SYSVAL_SAMPLER
:
1066 panfrost_upload_sampler_sysval(batch
, st
,
1067 PAN_SYSVAL_ID(sysval
),
1077 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
,
1080 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
1081 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
1084 return rsrc
->bo
->cpu
;
1085 else if (cb
->user_buffer
)
1086 return cb
->user_buffer
;
1088 unreachable("No constant buffer");
1092 panfrost_emit_const_buf(struct panfrost_batch
*batch
,
1093 enum pipe_shader_type stage
,
1094 struct mali_vertex_tiler_postfix
*postfix
)
1096 struct panfrost_context
*ctx
= batch
->ctx
;
1097 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
1102 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[stage
];
1104 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1106 /* Uniforms are implicitly UBO #0 */
1107 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1109 /* Allocate room for the sysval and the uniforms */
1110 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1111 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1112 size_t size
= sys_size
+ uniform_size
;
1113 struct panfrost_transfer transfer
=
1114 panfrost_pool_alloc_aligned(&batch
->pool
, size
, 16);
1116 /* Upload sysvals requested by the shader */
1117 panfrost_upload_sysvals(batch
, transfer
.cpu
, ss
, stage
);
1119 /* Upload uniforms */
1120 if (has_uniforms
&& uniform_size
) {
1121 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1122 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1125 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1128 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
1129 assert(ubo_count
>= 1);
1131 size_t sz
= MALI_UNIFORM_BUFFER_LENGTH
* ubo_count
;
1132 struct panfrost_transfer ubos
=
1133 panfrost_pool_alloc_aligned(&batch
->pool
, sz
,
1134 MALI_UNIFORM_BUFFER_LENGTH
);
1136 uint64_t *ubo_ptr
= (uint64_t *) ubos
.cpu
;
1138 /* Upload uniforms as a UBO */
1140 if (ss
->uniform_count
) {
1141 pan_pack(ubo_ptr
, UNIFORM_BUFFER
, cfg
) {
1142 cfg
.entries
= ss
->uniform_count
;
1143 cfg
.pointer
= transfer
.gpu
;
1149 /* The rest are honest-to-goodness UBOs */
1151 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1152 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1153 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1154 bool empty
= usz
== 0;
1156 if (!enabled
|| empty
) {
1161 pan_pack(ubo_ptr
+ ubo
, UNIFORM_BUFFER
, cfg
) {
1162 cfg
.entries
= DIV_ROUND_UP(usz
, 16);
1163 cfg
.pointer
= panfrost_map_constant_buffer_gpu(batch
,
1168 postfix
->uniforms
= transfer
.gpu
;
1169 postfix
->uniform_buffers
= ubos
.gpu
;
1171 buf
->dirty_mask
= 0;
1175 panfrost_emit_shared_memory(struct panfrost_batch
*batch
,
1176 const struct pipe_grid_info
*info
,
1177 struct midgard_payload_vertex_tiler
*vtp
)
1179 struct panfrost_context
*ctx
= batch
->ctx
;
1180 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
1181 struct panfrost_shader_variants
*all
= ctx
->shader
[PIPE_SHADER_COMPUTE
];
1182 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1183 unsigned single_size
= util_next_power_of_two(MAX2(ss
->shared_size
,
1186 unsigned log2_instances
=
1187 util_logbase2_ceil(info
->grid
[0]) +
1188 util_logbase2_ceil(info
->grid
[1]) +
1189 util_logbase2_ceil(info
->grid
[2]);
1191 unsigned shared_size
= single_size
* (1 << log2_instances
) * dev
->core_count
;
1192 struct panfrost_bo
*bo
= panfrost_batch_get_shared_memory(batch
,
1196 struct mali_shared_memory shared
= {
1197 .shared_memory
= bo
->gpu
,
1198 .shared_workgroup_count
= log2_instances
,
1199 .shared_shift
= util_logbase2(single_size
) + 1
1202 vtp
->postfix
.shared_memory
= panfrost_pool_upload(&batch
->pool
, &shared
,
1207 panfrost_get_tex_desc(struct panfrost_batch
*batch
,
1208 enum pipe_shader_type st
,
1209 struct panfrost_sampler_view
*view
)
1212 return (mali_ptr
) 0;
1214 struct pipe_sampler_view
*pview
= &view
->base
;
1215 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
1217 /* Add the BO to the job so it's retained until the job is done. */
1219 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1220 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1221 panfrost_bo_access_for_stage(st
));
1223 panfrost_batch_add_bo(batch
, view
->bo
,
1224 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1225 panfrost_bo_access_for_stage(st
));
1227 return view
->bo
->gpu
;
1231 panfrost_update_sampler_view(struct panfrost_sampler_view
*view
,
1232 struct pipe_context
*pctx
)
1234 struct panfrost_resource
*rsrc
= pan_resource(view
->base
.texture
);
1235 if (view
->texture_bo
!= rsrc
->bo
->gpu
||
1236 view
->modifier
!= rsrc
->modifier
) {
1237 panfrost_bo_unreference(view
->bo
);
1238 panfrost_create_sampler_view_bo(view
, pctx
, &rsrc
->base
);
1243 panfrost_emit_texture_descriptors(struct panfrost_batch
*batch
,
1244 enum pipe_shader_type stage
,
1245 struct mali_vertex_tiler_postfix
*postfix
)
1247 struct panfrost_context
*ctx
= batch
->ctx
;
1248 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
1250 if (!ctx
->sampler_view_count
[stage
])
1253 if (device
->quirks
& IS_BIFROST
) {
1254 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
,
1255 MALI_BIFROST_TEXTURE_LENGTH
*
1256 ctx
->sampler_view_count
[stage
],
1257 MALI_BIFROST_TEXTURE_LENGTH
);
1259 struct mali_bifrost_texture_packed
*out
=
1260 (struct mali_bifrost_texture_packed
*) T
.cpu
;
1262 for (int i
= 0; i
< ctx
->sampler_view_count
[stage
]; ++i
) {
1263 struct panfrost_sampler_view
*view
= ctx
->sampler_views
[stage
][i
];
1264 struct pipe_sampler_view
*pview
= &view
->base
;
1265 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
1267 panfrost_update_sampler_view(view
, &ctx
->base
);
1268 out
[i
] = view
->bifrost_descriptor
;
1270 /* Add the BOs to the job so they are retained until the job is done. */
1272 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1273 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1274 panfrost_bo_access_for_stage(stage
));
1276 panfrost_batch_add_bo(batch
, view
->bo
,
1277 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1278 panfrost_bo_access_for_stage(stage
));
1281 postfix
->textures
= T
.gpu
;
1283 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1285 for (int i
= 0; i
< ctx
->sampler_view_count
[stage
]; ++i
) {
1286 struct panfrost_sampler_view
*view
= ctx
->sampler_views
[stage
][i
];
1288 panfrost_update_sampler_view(view
, &ctx
->base
);
1290 trampolines
[i
] = panfrost_get_tex_desc(batch
, stage
, view
);
1293 postfix
->textures
= panfrost_pool_upload(&batch
->pool
,
1296 ctx
->sampler_view_count
[stage
]);
1301 panfrost_emit_sampler_descriptors(struct panfrost_batch
*batch
,
1302 enum pipe_shader_type stage
,
1303 struct mali_vertex_tiler_postfix
*postfix
)
1305 struct panfrost_context
*ctx
= batch
->ctx
;
1307 if (!ctx
->sampler_count
[stage
])
1310 size_t desc_size
= MALI_BIFROST_SAMPLER_LENGTH
;
1311 assert(MALI_BIFROST_SAMPLER_LENGTH
== MALI_MIDGARD_SAMPLER_LENGTH
);
1313 size_t sz
= desc_size
* ctx
->sampler_count
[stage
];
1314 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
, sz
, desc_size
);
1315 struct mali_midgard_sampler_packed
*out
= (struct mali_midgard_sampler_packed
*) T
.cpu
;
1317 for (unsigned i
= 0; i
< ctx
->sampler_count
[stage
]; ++i
)
1318 out
[i
] = ctx
->samplers
[stage
][i
]->hw
;
1320 postfix
->sampler_descriptor
= T
.gpu
;
1324 panfrost_emit_vertex_data(struct panfrost_batch
*batch
,
1325 struct mali_vertex_tiler_postfix
*vertex_postfix
)
1327 struct panfrost_context
*ctx
= batch
->ctx
;
1328 struct panfrost_vertex_state
*so
= ctx
->vertex
;
1329 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
1331 unsigned instance_shift
= vertex_postfix
->instance_shift
;
1332 unsigned instance_odd
= vertex_postfix
->instance_odd
;
1334 /* Worst case: everything is NPOT */
1336 struct panfrost_transfer S
= panfrost_pool_alloc_aligned(&batch
->pool
,
1337 MALI_ATTRIBUTE_BUFFER_LENGTH
* PIPE_MAX_ATTRIBS
* 2,
1338 MALI_ATTRIBUTE_BUFFER_LENGTH
);
1340 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
,
1341 MALI_ATTRIBUTE_LENGTH
* vs
->attribute_count
,
1342 MALI_ATTRIBUTE_LENGTH
);
1344 struct mali_attribute_buffer_packed
*bufs
=
1345 (struct mali_attribute_buffer_packed
*) S
.cpu
;
1347 struct mali_attribute_packed
*out
=
1348 (struct mali_attribute_packed
*) T
.cpu
;
1350 unsigned attrib_to_buffer
[PIPE_MAX_ATTRIBS
] = { 0 };
1353 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
1354 /* We map buffers 1:1 with the attributes, which
1355 * means duplicating some vertex buffers (who cares? aside from
1356 * maybe some caching implications but I somehow doubt that
1359 struct pipe_vertex_element
*elem
= &so
->pipe
[i
];
1360 unsigned vbi
= elem
->vertex_buffer_index
;
1361 attrib_to_buffer
[i
] = k
;
1363 if (!(ctx
->vb_mask
& (1 << vbi
)))
1366 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
1367 struct panfrost_resource
*rsrc
;
1369 rsrc
= pan_resource(buf
->buffer
.resource
);
1373 /* Add a dependency of the batch on the vertex buffer */
1374 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1375 PAN_BO_ACCESS_SHARED
|
1376 PAN_BO_ACCESS_READ
|
1377 PAN_BO_ACCESS_VERTEX_TILER
);
1379 /* Mask off lower bits, see offset fixup below */
1380 mali_ptr raw_addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
1381 mali_ptr addr
= raw_addr
& ~63;
1383 /* Since we advanced the base pointer, we shrink the buffer
1384 * size, but add the offset we subtracted */
1385 unsigned size
= rsrc
->base
.width0
+ (raw_addr
- addr
)
1386 - buf
->buffer_offset
;
1388 /* When there is a divisor, the hardware-level divisor is
1389 * the product of the instance divisor and the padded count */
1390 unsigned divisor
= elem
->instance_divisor
;
1391 unsigned hw_divisor
= ctx
->padded_count
* divisor
;
1392 unsigned stride
= buf
->stride
;
1394 /* If there's a divisor(=1) but no instancing, we want every
1395 * attribute to be the same */
1397 if (divisor
&& ctx
->instance_count
== 1)
1400 if (!divisor
|| ctx
->instance_count
<= 1) {
1401 pan_pack(bufs
+ k
, ATTRIBUTE_BUFFER
, cfg
) {
1402 if (ctx
->instance_count
> 1)
1403 cfg
.type
= MALI_ATTRIBUTE_TYPE_1D_MODULUS
;
1406 cfg
.stride
= stride
;
1408 cfg
.divisor_r
= instance_shift
;
1409 cfg
.divisor_p
= instance_odd
;
1411 } else if (util_is_power_of_two_or_zero(hw_divisor
)) {
1412 pan_pack(bufs
+ k
, ATTRIBUTE_BUFFER
, cfg
) {
1413 cfg
.type
= MALI_ATTRIBUTE_TYPE_1D_POT_DIVISOR
;
1415 cfg
.stride
= stride
;
1417 cfg
.divisor_r
= __builtin_ctz(hw_divisor
);
1421 unsigned shift
= 0, extra_flags
= 0;
1423 unsigned magic_divisor
=
1424 panfrost_compute_magic_divisor(hw_divisor
, &shift
, &extra_flags
);
1426 pan_pack(bufs
+ k
, ATTRIBUTE_BUFFER
, cfg
) {
1427 cfg
.type
= MALI_ATTRIBUTE_TYPE_1D_NPOT_DIVISOR
;
1429 cfg
.stride
= stride
;
1432 cfg
.divisor_r
= shift
;
1433 cfg
.divisor_e
= extra_flags
;
1436 pan_pack(bufs
+ k
+ 1, ATTRIBUTE_BUFFER_CONTINUATION_NPOT
, cfg
) {
1437 cfg
.divisor_numerator
= magic_divisor
;
1438 cfg
.divisor
= divisor
;
1447 /* Add special gl_VertexID/gl_InstanceID buffers */
1449 if (unlikely(vs
->attribute_count
>= PAN_VERTEX_ID
)) {
1450 panfrost_vertex_id(ctx
->padded_count
, &bufs
[k
], ctx
->instance_count
> 1);
1452 pan_pack(out
+ PAN_VERTEX_ID
, ATTRIBUTE
, cfg
) {
1453 cfg
.buffer_index
= k
++;
1454 cfg
.format
= so
->formats
[PAN_VERTEX_ID
];
1457 panfrost_instance_id(ctx
->padded_count
, &bufs
[k
], ctx
->instance_count
> 1);
1459 pan_pack(out
+ PAN_INSTANCE_ID
, ATTRIBUTE
, cfg
) {
1460 cfg
.buffer_index
= k
++;
1461 cfg
.format
= so
->formats
[PAN_INSTANCE_ID
];
1465 /* Attribute addresses require 64-byte alignment, so let:
1467 * base' = base & ~63 = base - (base & 63)
1468 * offset' = offset + (base & 63)
1470 * Since base' + offset' = base + offset, these are equivalent
1471 * addressing modes and now base is 64 aligned.
1474 unsigned start
= vertex_postfix
->offset_start
;
1476 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
1477 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
1478 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
1480 /* Adjust by the masked off bits of the offset. Make sure we
1481 * read src_offset from so->hw (which is not GPU visible)
1482 * rather than target (which is) due to caching effects */
1484 unsigned src_offset
= so
->pipe
[i
].src_offset
;
1486 /* BOs aligned to 4k so guaranteed aligned to 64 */
1487 src_offset
+= (buf
->buffer_offset
& 63);
1489 /* Also, somewhat obscurely per-instance data needs to be
1490 * offset in response to a delayed start in an indexed draw */
1492 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
1493 src_offset
-= buf
->stride
* start
;
1495 pan_pack(out
+ i
, ATTRIBUTE
, cfg
) {
1496 cfg
.buffer_index
= attrib_to_buffer
[i
];
1497 cfg
.format
= so
->formats
[i
];
1498 cfg
.offset
= src_offset
;
1502 vertex_postfix
->attributes
= S
.gpu
;
1503 vertex_postfix
->attribute_meta
= T
.gpu
;
1507 panfrost_emit_varyings(struct panfrost_batch
*batch
,
1508 struct mali_attribute_buffer_packed
*slot
,
1509 unsigned stride
, unsigned count
)
1511 unsigned size
= stride
* count
;
1512 mali_ptr ptr
= panfrost_pool_alloc_aligned(&batch
->invisible_pool
, size
, 64).gpu
;
1514 pan_pack(slot
, ATTRIBUTE_BUFFER
, cfg
) {
1515 cfg
.stride
= stride
;
1524 panfrost_streamout_offset(unsigned stride
, unsigned offset
,
1525 struct pipe_stream_output_target
*target
)
1527 return (target
->buffer_offset
+ (offset
* stride
* 4)) & 63;
1531 panfrost_emit_streamout(struct panfrost_batch
*batch
,
1532 struct mali_attribute_buffer_packed
*slot
,
1533 unsigned stride_words
, unsigned offset
, unsigned count
,
1534 struct pipe_stream_output_target
*target
)
1536 unsigned stride
= stride_words
* 4;
1537 unsigned max_size
= target
->buffer_size
;
1538 unsigned expected_size
= stride
* count
;
1540 /* Grab the BO and bind it to the batch */
1541 struct panfrost_bo
*bo
= pan_resource(target
->buffer
)->bo
;
1543 /* Varyings are WRITE from the perspective of the VERTEX but READ from
1544 * the perspective of the TILER and FRAGMENT.
1546 panfrost_batch_add_bo(batch
, bo
,
1547 PAN_BO_ACCESS_SHARED
|
1549 PAN_BO_ACCESS_VERTEX_TILER
|
1550 PAN_BO_ACCESS_FRAGMENT
);
1552 /* We will have an offset applied to get alignment */
1553 mali_ptr addr
= bo
->gpu
+ target
->buffer_offset
+ (offset
* stride
);
1555 pan_pack(slot
, ATTRIBUTE_BUFFER
, cfg
) {
1556 cfg
.pointer
= (addr
& ~63);
1557 cfg
.stride
= stride
;
1558 cfg
.size
= MIN2(max_size
, expected_size
) + (addr
& 63);
1563 has_point_coord(unsigned mask
, gl_varying_slot loc
)
1565 if ((loc
>= VARYING_SLOT_TEX0
) && (loc
<= VARYING_SLOT_TEX7
))
1566 return (mask
& (1 << (loc
- VARYING_SLOT_TEX0
)));
1567 else if (loc
== VARYING_SLOT_PNTC
)
1568 return (mask
& (1 << 8));
1573 /* Helpers for manipulating stream out information so we can pack varyings
1574 * accordingly. Compute the src_offset for a given captured varying */
1576 static struct pipe_stream_output
*
1577 pan_get_so(struct pipe_stream_output_info
*info
, gl_varying_slot loc
)
1579 for (unsigned i
= 0; i
< info
->num_outputs
; ++i
) {
1580 if (info
->output
[i
].register_index
== loc
)
1581 return &info
->output
[i
];
1584 unreachable("Varying not captured");
1588 pan_varying_size(enum mali_format fmt
)
1590 unsigned type
= MALI_EXTRACT_TYPE(fmt
);
1591 unsigned chan
= MALI_EXTRACT_CHANNELS(fmt
);
1592 unsigned bits
= MALI_EXTRACT_BITS(fmt
);
1595 if (bits
== MALI_CHANNEL_FLOAT
) {
1597 bool fp16
= (type
== MALI_FORMAT_SINT
);
1598 assert(fp16
|| (type
== MALI_FORMAT_UNORM
));
1602 assert(type
>= MALI_FORMAT_SNORM
&& type
<= MALI_FORMAT_SINT
);
1613 /* Indices for named (non-XFB) varyings that are present. These are packed
1614 * tightly so they correspond to a bitfield present (P) indexed by (1 <<
1615 * PAN_VARY_*). This has the nice property that you can lookup the buffer index
1616 * of a given special field given a shift S by:
1618 * idx = popcount(P & ((1 << S) - 1))
1620 * That is... look at all of the varyings that come earlier and count them, the
1621 * count is the new index since plus one. Likewise, the total number of special
1622 * buffers required is simply popcount(P)
1625 enum pan_special_varying
{
1626 PAN_VARY_GENERAL
= 0,
1627 PAN_VARY_POSITION
= 1,
1629 PAN_VARY_PNTCOORD
= 3,
1631 PAN_VARY_FRAGCOORD
= 5,
1637 /* Given a varying, figure out which index it correpsonds to */
1639 static inline unsigned
1640 pan_varying_index(unsigned present
, enum pan_special_varying v
)
1642 unsigned mask
= (1 << v
) - 1;
1643 return util_bitcount(present
& mask
);
1646 /* Get the base offset for XFB buffers, which by convention come after
1647 * everything else. Wrapper function for semantic reasons; by construction this
1648 * is just popcount. */
1650 static inline unsigned
1651 pan_xfb_base(unsigned present
)
1653 return util_bitcount(present
);
1656 /* Computes the present mask for varyings so we can start emitting varying records */
1658 static inline unsigned
1659 pan_varying_present(
1660 struct panfrost_shader_state
*vs
,
1661 struct panfrost_shader_state
*fs
,
1664 /* At the moment we always emit general and position buffers. Not
1665 * strictly necessary but usually harmless */
1667 unsigned present
= (1 << PAN_VARY_GENERAL
) | (1 << PAN_VARY_POSITION
);
1669 /* Enable special buffers by the shader info */
1671 if (vs
->writes_point_size
)
1672 present
|= (1 << PAN_VARY_PSIZ
);
1674 if (fs
->reads_point_coord
)
1675 present
|= (1 << PAN_VARY_PNTCOORD
);
1678 present
|= (1 << PAN_VARY_FACE
);
1680 if (fs
->reads_frag_coord
&& !(quirks
& IS_BIFROST
))
1681 present
|= (1 << PAN_VARY_FRAGCOORD
);
1683 /* Also, if we have a point sprite, we need a point coord buffer */
1685 for (unsigned i
= 0; i
< fs
->varying_count
; i
++) {
1686 gl_varying_slot loc
= fs
->varyings_loc
[i
];
1688 if (has_point_coord(fs
->point_sprite_mask
, loc
))
1689 present
|= (1 << PAN_VARY_PNTCOORD
);
1695 /* Emitters for varying records */
1698 pan_emit_vary(struct mali_attribute_packed
*out
,
1699 unsigned present
, enum pan_special_varying buf
,
1700 unsigned quirks
, enum mali_format format
,
1703 unsigned nr_channels
= MALI_EXTRACT_CHANNELS(format
);
1704 unsigned swizzle
= quirks
& HAS_SWIZZLES
?
1705 panfrost_get_default_swizzle(nr_channels
) :
1706 panfrost_bifrost_swizzle(nr_channels
);
1708 pan_pack(out
, ATTRIBUTE
, cfg
) {
1709 cfg
.buffer_index
= pan_varying_index(present
, buf
);
1710 cfg
.unknown
= quirks
& IS_BIFROST
? 0x0 : 0x1;
1711 cfg
.format
= (format
<< 12) | swizzle
;
1712 cfg
.offset
= offset
;
1716 /* General varying that is unused */
1719 pan_emit_vary_only(struct mali_attribute_packed
*out
,
1720 unsigned present
, unsigned quirks
)
1722 pan_emit_vary(out
, present
, 0, quirks
, MALI_VARYING_DISCARD
, 0);
1725 /* Special records */
1727 static const enum mali_format pan_varying_formats
[PAN_VARY_MAX
] = {
1728 [PAN_VARY_POSITION
] = MALI_VARYING_POS
,
1729 [PAN_VARY_PSIZ
] = MALI_R16F
,
1730 [PAN_VARY_PNTCOORD
] = MALI_R16F
,
1731 [PAN_VARY_FACE
] = MALI_R32I
,
1732 [PAN_VARY_FRAGCOORD
] = MALI_RGBA32F
1736 pan_emit_vary_special(struct mali_attribute_packed
*out
,
1737 unsigned present
, enum pan_special_varying buf
,
1740 assert(buf
< PAN_VARY_MAX
);
1741 pan_emit_vary(out
, present
, buf
, quirks
, pan_varying_formats
[buf
], 0);
1744 static enum mali_format
1745 pan_xfb_format(enum mali_format format
, unsigned nr
)
1747 if (MALI_EXTRACT_BITS(format
) == MALI_CHANNEL_FLOAT
)
1748 return MALI_R32F
| MALI_NR_CHANNELS(nr
);
1750 return MALI_EXTRACT_TYPE(format
) | MALI_NR_CHANNELS(nr
) | MALI_CHANNEL_32
;
1753 /* Transform feedback records. Note struct pipe_stream_output is (if packed as
1754 * a bitfield) 32-bit, smaller than a 64-bit pointer, so may as well pass by
1758 pan_emit_vary_xfb(struct mali_attribute_packed
*out
,
1761 unsigned *streamout_offsets
,
1763 enum mali_format format
,
1764 struct pipe_stream_output o
)
1766 unsigned swizzle
= quirks
& HAS_SWIZZLES
?
1767 panfrost_get_default_swizzle(o
.num_components
) :
1768 panfrost_bifrost_swizzle(o
.num_components
);
1770 pan_pack(out
, ATTRIBUTE
, cfg
) {
1771 /* XFB buffers come after everything else */
1772 cfg
.buffer_index
= pan_xfb_base(present
) + o
.output_buffer
;
1773 cfg
.unknown
= quirks
& IS_BIFROST
? 0x0 : 0x1;
1775 /* Override number of channels and precision to highp */
1776 cfg
.format
= (pan_xfb_format(format
, o
.num_components
) << 12) | swizzle
;
1778 /* Apply given offsets together */
1779 cfg
.offset
= (o
.dst_offset
* 4) /* dwords */
1780 + streamout_offsets
[o
.output_buffer
];
1784 /* Determine if we should capture a varying for XFB. This requires actually
1785 * having a buffer for it. If we don't capture it, we'll fallback to a general
1786 * varying path (linked or unlinked, possibly discarding the write) */
1789 panfrost_xfb_captured(struct panfrost_shader_state
*xfb
,
1790 unsigned loc
, unsigned max_xfb
)
1792 if (!(xfb
->so_mask
& (1ll << loc
)))
1795 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1796 return o
->output_buffer
< max_xfb
;
1800 pan_emit_general_varying(struct mali_attribute_packed
*out
,
1801 struct panfrost_shader_state
*other
,
1802 struct panfrost_shader_state
*xfb
,
1803 gl_varying_slot loc
,
1804 enum mali_format format
,
1807 unsigned *gen_offsets
,
1808 enum mali_format
*gen_formats
,
1809 unsigned *gen_stride
,
1813 /* Check if we're linked */
1814 signed other_idx
= -1;
1816 for (unsigned j
= 0; j
< other
->varying_count
; ++j
) {
1817 if (other
->varyings_loc
[j
] == loc
) {
1823 if (other_idx
< 0) {
1824 pan_emit_vary_only(out
, present
, quirks
);
1828 unsigned offset
= gen_offsets
[other_idx
];
1831 /* We're linked, so allocate a space via a watermark allocation */
1832 enum mali_format alt
= other
->varyings
[other_idx
];
1834 /* Do interpolation at minimum precision */
1835 unsigned size_main
= pan_varying_size(format
);
1836 unsigned size_alt
= pan_varying_size(alt
);
1837 unsigned size
= MIN2(size_main
, size_alt
);
1839 /* If a varying is marked for XFB but not actually captured, we
1840 * should match the format to the format that would otherwise
1841 * be used for XFB, since dEQP checks for invariance here. It's
1842 * unclear if this is required by the spec. */
1844 if (xfb
->so_mask
& (1ull << loc
)) {
1845 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1846 format
= pan_xfb_format(format
, o
->num_components
);
1847 size
= pan_varying_size(format
);
1848 } else if (size
== size_alt
) {
1852 gen_offsets
[idx
] = *gen_stride
;
1853 gen_formats
[other_idx
] = format
;
1854 offset
= *gen_stride
;
1855 *gen_stride
+= size
;
1858 pan_emit_vary(out
, present
, PAN_VARY_GENERAL
, quirks
, format
, offset
);
1861 /* Higher-level wrapper around all of the above, classifying a varying into one
1862 * of the above types */
1865 panfrost_emit_varying(
1866 struct mali_attribute_packed
*out
,
1867 struct panfrost_shader_state
*stage
,
1868 struct panfrost_shader_state
*other
,
1869 struct panfrost_shader_state
*xfb
,
1872 unsigned *streamout_offsets
,
1874 unsigned *gen_offsets
,
1875 enum mali_format
*gen_formats
,
1876 unsigned *gen_stride
,
1881 gl_varying_slot loc
= stage
->varyings_loc
[idx
];
1882 enum mali_format format
= stage
->varyings
[idx
];
1884 /* Override format to match linkage */
1885 if (!should_alloc
&& gen_formats
[idx
])
1886 format
= gen_formats
[idx
];
1888 if (has_point_coord(stage
->point_sprite_mask
, loc
)) {
1889 pan_emit_vary_special(out
, present
, PAN_VARY_PNTCOORD
, quirks
);
1890 } else if (panfrost_xfb_captured(xfb
, loc
, max_xfb
)) {
1891 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1892 pan_emit_vary_xfb(out
, present
, max_xfb
, streamout_offsets
, quirks
, format
, *o
);
1893 } else if (loc
== VARYING_SLOT_POS
) {
1895 pan_emit_vary_special(out
, present
, PAN_VARY_FRAGCOORD
, quirks
);
1897 pan_emit_vary_special(out
, present
, PAN_VARY_POSITION
, quirks
);
1898 } else if (loc
== VARYING_SLOT_PSIZ
) {
1899 pan_emit_vary_special(out
, present
, PAN_VARY_PSIZ
, quirks
);
1900 } else if (loc
== VARYING_SLOT_PNTC
) {
1901 pan_emit_vary_special(out
, present
, PAN_VARY_PNTCOORD
, quirks
);
1902 } else if (loc
== VARYING_SLOT_FACE
) {
1903 pan_emit_vary_special(out
, present
, PAN_VARY_FACE
, quirks
);
1905 pan_emit_general_varying(out
, other
, xfb
, loc
, format
, present
,
1906 quirks
, gen_offsets
, gen_formats
, gen_stride
,
1912 pan_emit_special_input(struct mali_attribute_buffer_packed
*out
,
1914 enum pan_special_varying v
,
1917 if (present
& (1 << v
)) {
1918 unsigned idx
= pan_varying_index(present
, v
);
1920 pan_pack(out
+ idx
, ATTRIBUTE_BUFFER
, cfg
) {
1921 cfg
.special
= special
;
1928 panfrost_emit_varying_descriptor(struct panfrost_batch
*batch
,
1929 unsigned vertex_count
,
1930 struct mali_vertex_tiler_postfix
*vertex_postfix
,
1931 struct mali_vertex_tiler_postfix
*tiler_postfix
,
1932 union midgard_primitive_size
*primitive_size
)
1934 /* Load the shaders */
1935 struct panfrost_context
*ctx
= batch
->ctx
;
1936 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
1937 struct panfrost_shader_state
*vs
, *fs
;
1938 size_t vs_size
, fs_size
;
1940 /* Allocate the varying descriptor */
1942 vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
1943 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
1944 vs_size
= MALI_ATTRIBUTE_LENGTH
* vs
->varying_count
;
1945 fs_size
= MALI_ATTRIBUTE_LENGTH
* fs
->varying_count
;
1947 struct panfrost_transfer trans
= panfrost_pool_alloc_aligned(
1948 &batch
->pool
, vs_size
+ fs_size
, MALI_ATTRIBUTE_LENGTH
);
1950 struct pipe_stream_output_info
*so
= &vs
->stream_output
;
1951 unsigned present
= pan_varying_present(vs
, fs
, dev
->quirks
);
1953 /* Check if this varying is linked by us. This is the case for
1954 * general-purpose, non-captured varyings. If it is, link it. If it's
1955 * not, use the provided stream out information to determine the
1956 * offset, since it was already linked for us. */
1958 unsigned gen_offsets
[32];
1959 enum mali_format gen_formats
[32];
1960 memset(gen_offsets
, 0, sizeof(gen_offsets
));
1961 memset(gen_formats
, 0, sizeof(gen_formats
));
1963 unsigned gen_stride
= 0;
1964 assert(vs
->varying_count
< ARRAY_SIZE(gen_offsets
));
1965 assert(fs
->varying_count
< ARRAY_SIZE(gen_offsets
));
1967 unsigned streamout_offsets
[32];
1969 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1970 streamout_offsets
[i
] = panfrost_streamout_offset(
1972 ctx
->streamout
.offsets
[i
],
1973 ctx
->streamout
.targets
[i
]);
1976 struct mali_attribute_packed
*ovs
= (struct mali_attribute_packed
*)trans
.cpu
;
1977 struct mali_attribute_packed
*ofs
= ovs
+ vs
->varying_count
;
1979 for (unsigned i
= 0; i
< vs
->varying_count
; i
++) {
1980 panfrost_emit_varying(ovs
+ i
, vs
, fs
, vs
, present
,
1981 ctx
->streamout
.num_targets
, streamout_offsets
,
1983 gen_offsets
, gen_formats
, &gen_stride
, i
, true, false);
1986 for (unsigned i
= 0; i
< fs
->varying_count
; i
++) {
1987 panfrost_emit_varying(ofs
+ i
, fs
, vs
, vs
, present
,
1988 ctx
->streamout
.num_targets
, streamout_offsets
,
1990 gen_offsets
, gen_formats
, &gen_stride
, i
, false, true);
1993 unsigned xfb_base
= pan_xfb_base(present
);
1994 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
,
1995 MALI_ATTRIBUTE_BUFFER_LENGTH
* (xfb_base
+ ctx
->streamout
.num_targets
),
1996 MALI_ATTRIBUTE_BUFFER_LENGTH
);
1997 struct mali_attribute_buffer_packed
*varyings
=
1998 (struct mali_attribute_buffer_packed
*) T
.cpu
;
2000 /* Emit the stream out buffers */
2002 unsigned out_count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
2005 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
2006 panfrost_emit_streamout(batch
, &varyings
[xfb_base
+ i
],
2008 ctx
->streamout
.offsets
[i
],
2010 ctx
->streamout
.targets
[i
]);
2013 panfrost_emit_varyings(batch
,
2014 &varyings
[pan_varying_index(present
, PAN_VARY_GENERAL
)],
2015 gen_stride
, vertex_count
);
2017 /* fp32 vec4 gl_Position */
2018 tiler_postfix
->position_varying
= panfrost_emit_varyings(batch
,
2019 &varyings
[pan_varying_index(present
, PAN_VARY_POSITION
)],
2020 sizeof(float) * 4, vertex_count
);
2022 if (present
& (1 << PAN_VARY_PSIZ
)) {
2023 primitive_size
->pointer
= panfrost_emit_varyings(batch
,
2024 &varyings
[pan_varying_index(present
, PAN_VARY_PSIZ
)],
2028 pan_emit_special_input(varyings
, present
, PAN_VARY_PNTCOORD
, MALI_ATTRIBUTE_SPECIAL_POINT_COORD
);
2029 pan_emit_special_input(varyings
, present
, PAN_VARY_FACE
, MALI_ATTRIBUTE_SPECIAL_FRONT_FACING
);
2030 pan_emit_special_input(varyings
, present
, PAN_VARY_FRAGCOORD
, MALI_ATTRIBUTE_SPECIAL_FRAG_COORD
);
2032 vertex_postfix
->varyings
= T
.gpu
;
2033 tiler_postfix
->varyings
= T
.gpu
;
2035 vertex_postfix
->varying_meta
= trans
.gpu
;
2036 tiler_postfix
->varying_meta
= trans
.gpu
+ vs_size
;
2040 panfrost_emit_vertex_tiler_jobs(struct panfrost_batch
*batch
,
2041 struct mali_vertex_tiler_prefix
*vertex_prefix
,
2042 struct mali_vertex_tiler_postfix
*vertex_postfix
,
2043 struct mali_vertex_tiler_prefix
*tiler_prefix
,
2044 struct mali_vertex_tiler_postfix
*tiler_postfix
,
2045 union midgard_primitive_size
*primitive_size
)
2047 struct panfrost_context
*ctx
= batch
->ctx
;
2048 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
2049 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->scoreboard
.tiler_dep
;
2050 struct bifrost_payload_vertex bifrost_vertex
= {0,};
2051 struct bifrost_payload_tiler bifrost_tiler
= {0,};
2052 struct midgard_payload_vertex_tiler midgard_vertex
= {0,};
2053 struct midgard_payload_vertex_tiler midgard_tiler
= {0,};
2055 size_t vp_size
, tp_size
;
2057 if (device
->quirks
& IS_BIFROST
) {
2058 bifrost_vertex
.prefix
= *vertex_prefix
;
2059 bifrost_vertex
.postfix
= *vertex_postfix
;
2060 vp
= &bifrost_vertex
;
2061 vp_size
= sizeof(bifrost_vertex
);
2063 bifrost_tiler
.prefix
= *tiler_prefix
;
2064 bifrost_tiler
.tiler
.primitive_size
= *primitive_size
;
2065 bifrost_tiler
.tiler
.tiler_meta
= panfrost_batch_get_tiler_meta(batch
, ~0);
2066 bifrost_tiler
.postfix
= *tiler_postfix
;
2067 tp
= &bifrost_tiler
;
2068 tp_size
= sizeof(bifrost_tiler
);
2070 midgard_vertex
.prefix
= *vertex_prefix
;
2071 midgard_vertex
.postfix
= *vertex_postfix
;
2072 vp
= &midgard_vertex
;
2073 vp_size
= sizeof(midgard_vertex
);
2075 midgard_tiler
.prefix
= *tiler_prefix
;
2076 midgard_tiler
.postfix
= *tiler_postfix
;
2077 midgard_tiler
.primitive_size
= *primitive_size
;
2078 tp
= &midgard_tiler
;
2079 tp_size
= sizeof(midgard_tiler
);
2083 /* Inject in reverse order, with "predicted" job indices.
2084 * THIS IS A HACK XXX */
2085 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_TILER
, false,
2086 batch
->scoreboard
.job_index
+ 2, tp
, tp_size
, true);
2087 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_VERTEX
, false, 0,
2092 /* If rasterizer discard is enable, only submit the vertex */
2094 unsigned vertex
= panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_VERTEX
, false, 0,
2095 vp
, vp_size
, false);
2097 if (ctx
->rasterizer
->base
.rasterizer_discard
)
2100 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_TILER
, false, vertex
, tp
, tp_size
,
2104 /* TODO: stop hardcoding this */
2106 panfrost_emit_sample_locations(struct panfrost_batch
*batch
)
2108 uint16_t locations
[] = {
2159 return panfrost_pool_upload(&batch
->pool
, locations
, 96 * sizeof(uint16_t));