2 * Copyright (C) 2018 Alyssa Rosenzweig
3 * Copyright (C) 2020 Collabora Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "util/macros.h"
26 #include "util/u_prim.h"
27 #include "util/u_vbuf.h"
29 #include "panfrost-quirks.h"
33 #include "pan_cmdstream.h"
34 #include "pan_context.h"
37 /* If a BO is accessed for a particular shader stage, will it be in the primary
38 * batch (vertex/tiler) or the secondary batch (fragment)? Anything but
39 * fragment will be primary, e.g. compute jobs will be considered
40 * "vertex/tiler" by analogy */
42 static inline uint32_t
43 panfrost_bo_access_for_stage(enum pipe_shader_type stage
)
45 assert(stage
== PIPE_SHADER_FRAGMENT
||
46 stage
== PIPE_SHADER_VERTEX
||
47 stage
== PIPE_SHADER_COMPUTE
);
49 return stage
== PIPE_SHADER_FRAGMENT
?
50 PAN_BO_ACCESS_FRAGMENT
:
51 PAN_BO_ACCESS_VERTEX_TILER
;
55 panfrost_vt_emit_shared_memory(struct panfrost_context
*ctx
,
56 struct mali_vertex_tiler_postfix
*postfix
)
58 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
59 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
61 unsigned shift
= panfrost_get_stack_shift(batch
->stack_size
);
62 struct mali_shared_memory shared
= {
64 .scratchpad
= panfrost_batch_get_scratchpad(batch
, shift
, dev
->thread_tls_alloc
, dev
->core_count
)->gpu
,
65 .shared_workgroup_count
= ~0,
67 postfix
->shared_memory
= panfrost_pool_upload(&batch
->pool
, &shared
, sizeof(shared
));
71 panfrost_vt_attach_framebuffer(struct panfrost_context
*ctx
,
72 struct mali_vertex_tiler_postfix
*postfix
)
74 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
75 postfix
->shared_memory
= panfrost_batch_reserve_framebuffer(batch
);
79 panfrost_vt_update_rasterizer(struct panfrost_context
*ctx
,
80 struct mali_vertex_tiler_prefix
*prefix
,
81 struct mali_vertex_tiler_postfix
*postfix
)
83 struct panfrost_rasterizer
*rasterizer
= ctx
->rasterizer
;
85 postfix
->gl_enables
|= 0x7;
86 SET_BIT(postfix
->gl_enables
, MALI_FRONT_CCW_TOP
,
87 rasterizer
&& rasterizer
->base
.front_ccw
);
88 SET_BIT(postfix
->gl_enables
, MALI_CULL_FACE_FRONT
,
89 rasterizer
&& (rasterizer
->base
.cull_face
& PIPE_FACE_FRONT
));
90 SET_BIT(postfix
->gl_enables
, MALI_CULL_FACE_BACK
,
91 rasterizer
&& (rasterizer
->base
.cull_face
& PIPE_FACE_BACK
));
92 SET_BIT(prefix
->unknown_draw
, MALI_DRAW_FLATSHADE_FIRST
,
93 rasterizer
&& rasterizer
->base
.flatshade_first
);
97 panfrost_vt_update_primitive_size(struct panfrost_context
*ctx
,
98 struct mali_vertex_tiler_prefix
*prefix
,
99 union midgard_primitive_size
*primitive_size
)
101 struct panfrost_rasterizer
*rasterizer
= ctx
->rasterizer
;
103 if (!panfrost_writes_point_size(ctx
)) {
104 bool points
= prefix
->draw_mode
== MALI_DRAW_MODE_POINTS
;
109 rasterizer
->base
.point_size
:
110 rasterizer
->base
.line_width
;
112 primitive_size
->constant
= val
;
117 panfrost_vt_update_occlusion_query(struct panfrost_context
*ctx
,
118 struct mali_vertex_tiler_postfix
*postfix
)
120 SET_BIT(postfix
->gl_enables
, MALI_OCCLUSION_QUERY
, ctx
->occlusion_query
);
121 if (ctx
->occlusion_query
) {
122 postfix
->occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
123 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
124 PAN_BO_ACCESS_SHARED
|
126 PAN_BO_ACCESS_FRAGMENT
);
128 postfix
->occlusion_counter
= 0;
133 panfrost_vt_init(struct panfrost_context
*ctx
,
134 enum pipe_shader_type stage
,
135 struct mali_vertex_tiler_prefix
*prefix
,
136 struct mali_vertex_tiler_postfix
*postfix
)
138 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
140 if (!ctx
->shader
[stage
])
143 memset(prefix
, 0, sizeof(*prefix
));
144 memset(postfix
, 0, sizeof(*postfix
));
146 if (device
->quirks
& IS_BIFROST
) {
147 postfix
->gl_enables
= 0x2;
148 panfrost_vt_emit_shared_memory(ctx
, postfix
);
150 postfix
->gl_enables
= 0x6;
151 panfrost_vt_attach_framebuffer(ctx
, postfix
);
154 if (stage
== PIPE_SHADER_FRAGMENT
) {
155 panfrost_vt_update_occlusion_query(ctx
, postfix
);
156 panfrost_vt_update_rasterizer(ctx
, prefix
, postfix
);
161 panfrost_translate_index_size(unsigned size
)
165 return MALI_DRAW_INDEXED_UINT8
;
168 return MALI_DRAW_INDEXED_UINT16
;
171 return MALI_DRAW_INDEXED_UINT32
;
174 unreachable("Invalid index size");
178 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
179 * good for the duration of the draw (transient), could last longer. Also get
180 * the bounds on the index buffer for the range accessed by the draw. We do
181 * these operations together because there are natural optimizations which
182 * require them to be together. */
185 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
,
186 const struct pipe_draw_info
*info
,
187 unsigned *min_index
, unsigned *max_index
)
189 struct panfrost_resource
*rsrc
= pan_resource(info
->index
.resource
);
190 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
191 off_t offset
= info
->start
* info
->index_size
;
192 bool needs_indices
= true;
195 if (info
->max_index
!= ~0u) {
196 *min_index
= info
->min_index
;
197 *max_index
= info
->max_index
;
198 needs_indices
= false;
201 if (!info
->has_user_indices
) {
202 /* Only resources can be directly mapped */
203 panfrost_batch_add_bo(batch
, rsrc
->bo
,
204 PAN_BO_ACCESS_SHARED
|
206 PAN_BO_ACCESS_VERTEX_TILER
);
207 out
= rsrc
->bo
->gpu
+ offset
;
209 /* Check the cache */
210 needs_indices
= !panfrost_minmax_cache_get(rsrc
->index_cache
,
216 /* Otherwise, we need to upload to transient memory */
217 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
218 out
= panfrost_pool_upload(&batch
->pool
, ibuf8
+ offset
,
225 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
227 if (!info
->has_user_indices
)
228 panfrost_minmax_cache_add(rsrc
->index_cache
,
229 info
->start
, info
->count
,
230 *min_index
, *max_index
);
237 panfrost_vt_set_draw_info(struct panfrost_context
*ctx
,
238 const struct pipe_draw_info
*info
,
239 enum mali_draw_mode draw_mode
,
240 struct mali_vertex_tiler_postfix
*vertex_postfix
,
241 struct mali_vertex_tiler_prefix
*tiler_prefix
,
242 struct mali_vertex_tiler_postfix
*tiler_postfix
,
243 unsigned *vertex_count
,
244 unsigned *padded_count
)
246 tiler_prefix
->draw_mode
= draw_mode
;
248 unsigned draw_flags
= 0;
250 if (panfrost_writes_point_size(ctx
))
251 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
253 if (info
->primitive_restart
)
254 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
256 /* These doesn't make much sense */
258 draw_flags
|= 0x3000;
260 if (info
->index_size
) {
261 unsigned min_index
= 0, max_index
= 0;
263 tiler_prefix
->indices
= panfrost_get_index_buffer_bounded(ctx
,
268 /* Use the corresponding values */
269 *vertex_count
= max_index
- min_index
+ 1;
270 tiler_postfix
->offset_start
= vertex_postfix
->offset_start
= min_index
+ info
->index_bias
;
271 tiler_prefix
->offset_bias_correction
= -min_index
;
272 tiler_prefix
->index_count
= MALI_POSITIVE(info
->count
);
273 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
275 tiler_prefix
->indices
= 0;
276 *vertex_count
= ctx
->vertex_count
;
277 tiler_postfix
->offset_start
= vertex_postfix
->offset_start
= info
->start
;
278 tiler_prefix
->offset_bias_correction
= 0;
279 tiler_prefix
->index_count
= MALI_POSITIVE(ctx
->vertex_count
);
282 tiler_prefix
->unknown_draw
= draw_flags
;
284 /* Encode the padded vertex count */
286 if (info
->instance_count
> 1) {
287 *padded_count
= panfrost_padded_vertex_count(*vertex_count
);
289 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
290 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
292 tiler_postfix
->instance_shift
= vertex_postfix
->instance_shift
= shift
;
293 tiler_postfix
->instance_odd
= vertex_postfix
->instance_odd
= k
;
295 *padded_count
= *vertex_count
;
297 /* Reset instancing state */
298 tiler_postfix
->instance_shift
= vertex_postfix
->instance_shift
= 0;
299 tiler_postfix
->instance_odd
= vertex_postfix
->instance_odd
= 0;
304 panfrost_shader_meta_init(struct panfrost_context
*ctx
,
305 enum pipe_shader_type st
,
306 struct mali_shader_meta
*meta
)
308 const struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
309 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, st
);
311 memset(meta
, 0, sizeof(*meta
));
312 meta
->shader
= (ss
->bo
? ss
->bo
->gpu
: 0) | ss
->first_tag
;
313 meta
->attribute_count
= ss
->attribute_count
;
314 meta
->varying_count
= ss
->varying_count
;
315 meta
->texture_count
= ctx
->sampler_view_count
[st
];
316 meta
->sampler_count
= ctx
->sampler_count
[st
];
318 if (dev
->quirks
& IS_BIFROST
) {
319 if (st
== PIPE_SHADER_VERTEX
)
320 meta
->bifrost1
.unk1
= 0x800000;
322 /* First clause ATEST |= 0x4000000.
323 * Less than 32 regs |= 0x200 */
324 meta
->bifrost1
.unk1
= 0x950020;
327 meta
->bifrost1
.uniform_buffer_count
= panfrost_ubo_count(ctx
, st
);
328 if (st
== PIPE_SHADER_VERTEX
)
329 meta
->bifrost2
.preload_regs
= 0xC0;
331 meta
->bifrost2
.preload_regs
= 0x1;
332 SET_BIT(meta
->bifrost2
.preload_regs
, 0x10, ss
->reads_frag_coord
);
335 meta
->bifrost2
.uniform_count
= MIN2(ss
->uniform_count
,
338 meta
->midgard1
.uniform_count
= MIN2(ss
->uniform_count
,
340 meta
->midgard1
.work_count
= ss
->work_reg_count
;
342 /* TODO: This is not conformant on ES3 */
343 meta
->midgard1
.flags_hi
= MALI_SUPPRESS_INF_NAN
;
345 meta
->midgard1
.flags_lo
= 0x20;
346 meta
->midgard1
.uniform_buffer_count
= panfrost_ubo_count(ctx
, st
);
348 SET_BIT(meta
->midgard1
.flags_hi
, MALI_WRITES_GLOBAL
, ss
->writes_global
);
353 panfrost_translate_compare_func(enum pipe_compare_func in
)
356 case PIPE_FUNC_NEVER
:
357 return MALI_FUNC_NEVER
;
360 return MALI_FUNC_LESS
;
362 case PIPE_FUNC_EQUAL
:
363 return MALI_FUNC_EQUAL
;
365 case PIPE_FUNC_LEQUAL
:
366 return MALI_FUNC_LEQUAL
;
368 case PIPE_FUNC_GREATER
:
369 return MALI_FUNC_GREATER
;
371 case PIPE_FUNC_NOTEQUAL
:
372 return MALI_FUNC_NOT_EQUAL
;
374 case PIPE_FUNC_GEQUAL
:
375 return MALI_FUNC_GEQUAL
;
377 case PIPE_FUNC_ALWAYS
:
378 return MALI_FUNC_ALWAYS
;
381 unreachable("Invalid func");
386 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
389 case PIPE_STENCIL_OP_KEEP
:
390 return MALI_STENCIL_OP_KEEP
;
392 case PIPE_STENCIL_OP_ZERO
:
393 return MALI_STENCIL_OP_ZERO
;
395 case PIPE_STENCIL_OP_REPLACE
:
396 return MALI_STENCIL_OP_REPLACE
;
398 case PIPE_STENCIL_OP_INCR
:
399 return MALI_STENCIL_OP_INCR_SAT
;
401 case PIPE_STENCIL_OP_DECR
:
402 return MALI_STENCIL_OP_DECR_SAT
;
404 case PIPE_STENCIL_OP_INCR_WRAP
:
405 return MALI_STENCIL_OP_INCR_WRAP
;
407 case PIPE_STENCIL_OP_DECR_WRAP
:
408 return MALI_STENCIL_OP_DECR_WRAP
;
410 case PIPE_STENCIL_OP_INVERT
:
411 return MALI_STENCIL_OP_INVERT
;
414 unreachable("Invalid stencil op");
419 translate_tex_wrap(enum pipe_tex_wrap w
)
422 case PIPE_TEX_WRAP_REPEAT
:
423 return MALI_WRAP_MODE_REPEAT
;
425 case PIPE_TEX_WRAP_CLAMP
:
426 return MALI_WRAP_MODE_CLAMP
;
428 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
429 return MALI_WRAP_MODE_CLAMP_TO_EDGE
;
431 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
432 return MALI_WRAP_MODE_CLAMP_TO_BORDER
;
434 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
435 return MALI_WRAP_MODE_MIRRORED_REPEAT
;
437 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
438 return MALI_WRAP_MODE_MIRRORED_CLAMP
;
440 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
441 return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE
;
443 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
444 return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER
;
447 unreachable("Invalid wrap");
451 void panfrost_sampler_desc_init(const struct pipe_sampler_state
*cso
,
452 struct mali_sampler_descriptor
*hw
)
454 unsigned func
= panfrost_translate_compare_func(cso
->compare_func
);
455 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
456 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
457 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
458 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
459 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
460 unsigned mip_filter
= mip_linear
?
461 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
462 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
464 *hw
= (struct mali_sampler_descriptor
) {
465 .filter_mode
= min_filter
| mag_filter
| mip_filter
|
467 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
468 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
469 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
470 .compare_func
= cso
->compare_mode
?
471 panfrost_flip_compare_func(func
) :
474 cso
->border_color
.f
[0],
475 cso
->border_color
.f
[1],
476 cso
->border_color
.f
[2],
477 cso
->border_color
.f
[3]
479 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
480 .max_lod
= FIXED_16(cso
->max_lod
, false),
481 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
482 .seamless_cube_map
= cso
->seamless_cube_map
,
485 /* If necessary, we disable mipmapping in the sampler descriptor by
486 * clamping the LOD as tight as possible (from 0 to epsilon,
487 * essentially -- remember these are fixed point numbers, so
490 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
491 hw
->max_lod
= hw
->min_lod
+ 1;
494 void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state
*cso
,
495 struct bifrost_sampler_descriptor
*hw
)
497 *hw
= (struct bifrost_sampler_descriptor
) {
499 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
500 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
501 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
503 .min_filter
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
,
504 .norm_coords
= cso
->normalized_coords
,
505 .mip_filter
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
,
506 .mag_filter
= cso
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
,
507 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
508 .max_lod
= FIXED_16(cso
->max_lod
, false),
511 /* If necessary, we disable mipmapping in the sampler descriptor by
512 * clamping the LOD as tight as possible (from 0 to epsilon,
513 * essentially -- remember these are fixed point numbers, so
516 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
517 hw
->max_lod
= hw
->min_lod
+ 1;
521 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
,
524 pan_pack(out
, STENCIL
, cfg
) {
525 cfg
.mask
= in
->valuemask
;
526 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
527 cfg
.stencil_fail
= panfrost_translate_stencil_op(in
->fail_op
);
528 cfg
.depth_fail
= panfrost_translate_stencil_op(in
->zfail_op
);
529 cfg
.depth_pass
= panfrost_translate_stencil_op(in
->zpass_op
);
534 panfrost_frag_meta_rasterizer_update(struct panfrost_context
*ctx
,
535 struct mali_shader_meta
*fragmeta
)
537 if (!ctx
->rasterizer
) {
538 SET_BIT(fragmeta
->unknown2_4
, MALI_NO_MSAA
, true);
539 SET_BIT(fragmeta
->unknown2_3
, MALI_HAS_MSAA
, false);
540 fragmeta
->depth_units
= 0.0f
;
541 fragmeta
->depth_factor
= 0.0f
;
542 SET_BIT(fragmeta
->unknown2_4
, MALI_DEPTH_RANGE_A
, false);
543 SET_BIT(fragmeta
->unknown2_4
, MALI_DEPTH_RANGE_B
, false);
544 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_CLIP_NEAR
, true);
545 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_CLIP_FAR
, true);
549 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
551 bool msaa
= rast
->multisample
;
553 /* TODO: Sample size */
554 SET_BIT(fragmeta
->unknown2_3
, MALI_HAS_MSAA
, msaa
);
555 SET_BIT(fragmeta
->unknown2_4
, MALI_NO_MSAA
, !msaa
);
557 struct panfrost_shader_state
*fs
;
558 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
560 /* EXT_shader_framebuffer_fetch requires the shader to be run
561 * per-sample when outputs are read. */
562 bool per_sample
= ctx
->min_samples
> 1 || fs
->outputs_read
;
563 SET_BIT(fragmeta
->unknown2_3
, MALI_PER_SAMPLE
, msaa
&& per_sample
);
565 fragmeta
->depth_units
= rast
->offset_units
* 2.0f
;
566 fragmeta
->depth_factor
= rast
->offset_scale
;
568 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
570 SET_BIT(fragmeta
->unknown2_4
, MALI_DEPTH_RANGE_A
, rast
->offset_tri
);
571 SET_BIT(fragmeta
->unknown2_4
, MALI_DEPTH_RANGE_B
, rast
->offset_tri
);
573 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_CLIP_NEAR
, rast
->depth_clip_near
);
574 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_CLIP_FAR
, rast
->depth_clip_far
);
578 panfrost_frag_meta_zsa_update(struct panfrost_context
*ctx
,
579 struct mali_shader_meta
*fragmeta
)
581 const struct pipe_depth_stencil_alpha_state
*zsa
= ctx
->depth_stencil
;
582 int zfunc
= PIPE_FUNC_ALWAYS
;
585 struct pipe_stencil_state default_stencil
= {
587 .func
= PIPE_FUNC_ALWAYS
,
588 .fail_op
= PIPE_STENCIL_OP_KEEP
,
589 .zfail_op
= PIPE_STENCIL_OP_KEEP
,
590 .zpass_op
= PIPE_STENCIL_OP_KEEP
,
595 panfrost_make_stencil_state(&default_stencil
,
596 &fragmeta
->stencil_front
);
597 fragmeta
->stencil_mask_front
= default_stencil
.writemask
;
598 fragmeta
->stencil_back
= fragmeta
->stencil_front
;
599 fragmeta
->stencil_mask_back
= default_stencil
.writemask
;
600 SET_BIT(fragmeta
->unknown2_4
, MALI_STENCIL_TEST
, false);
601 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_WRITEMASK
, false);
603 SET_BIT(fragmeta
->unknown2_4
, MALI_STENCIL_TEST
,
604 zsa
->stencil
[0].enabled
);
605 panfrost_make_stencil_state(&zsa
->stencil
[0],
606 &fragmeta
->stencil_front
);
607 fragmeta
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
609 /* Bottom 8-bits of stencil state is the stencil ref, ref is no
610 * more than 8-bits. Be extra careful. */
611 fragmeta
->stencil_front
.opaque
[0] |= ctx
->stencil_ref
.ref_value
[0];
613 /* If back-stencil is not enabled, use the front values */
615 if (zsa
->stencil
[1].enabled
) {
616 panfrost_make_stencil_state(&zsa
->stencil
[1],
617 &fragmeta
->stencil_back
);
618 fragmeta
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
619 fragmeta
->stencil_back
.opaque
[0] |= ctx
->stencil_ref
.ref_value
[1];
621 fragmeta
->stencil_back
= fragmeta
->stencil_front
;
622 fragmeta
->stencil_mask_back
= fragmeta
->stencil_mask_front
;
625 if (zsa
->depth
.enabled
)
626 zfunc
= zsa
->depth
.func
;
628 /* Depth state (TODO: Refactor) */
630 SET_BIT(fragmeta
->unknown2_3
, MALI_DEPTH_WRITEMASK
,
631 zsa
->depth
.writemask
);
634 fragmeta
->unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
635 fragmeta
->unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(zfunc
));
639 panfrost_fs_required(
640 struct panfrost_shader_state
*fs
,
641 struct panfrost_blend_final
*blend
,
644 /* If we generally have side effects */
648 /* If colour is written we need to execute */
649 for (unsigned i
= 0; i
< rt_count
; ++i
) {
650 if (!blend
[i
].no_colour
)
654 /* If depth is written and not implied we need to execute.
655 * TODO: Predicate on Z/S writes being enabled */
656 return (fs
->writes_depth
|| fs
->writes_stencil
);
660 panfrost_frag_meta_blend_update(struct panfrost_context
*ctx
,
661 struct mali_shader_meta
*fragmeta
,
664 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
665 const struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
666 struct panfrost_shader_state
*fs
;
667 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
669 SET_BIT(fragmeta
->unknown2_4
, MALI_NO_DITHER
,
670 (dev
->quirks
& MIDGARD_SFBD
) && ctx
->blend
&&
671 !ctx
->blend
->base
.dither
);
673 SET_BIT(fragmeta
->unknown2_4
, MALI_ALPHA_TO_COVERAGE
,
674 ctx
->blend
->base
.alpha_to_coverage
);
676 /* Get blending setup */
677 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
679 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
680 unsigned shader_offset
= 0;
681 struct panfrost_bo
*shader_bo
= NULL
;
683 for (unsigned c
= 0; c
< rt_count
; ++c
)
684 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
,
687 /* Disable shader execution if we can */
688 if (dev
->quirks
& MIDGARD_SHADERLESS
689 && !panfrost_fs_required(fs
, blend
, rt_count
)) {
690 fragmeta
->shader
= 0;
691 fragmeta
->attribute_count
= 0;
692 fragmeta
->varying_count
= 0;
693 fragmeta
->texture_count
= 0;
694 fragmeta
->sampler_count
= 0;
696 /* This feature is not known to work on Bifrost */
697 fragmeta
->midgard1
.work_count
= 1;
698 fragmeta
->midgard1
.uniform_count
= 0;
699 fragmeta
->midgard1
.uniform_buffer_count
= 0;
702 /* If there is a blend shader, work registers are shared. We impose 8
703 * work registers as a limit for blend shaders. Should be lower XXX */
705 if (!(dev
->quirks
& IS_BIFROST
)) {
706 for (unsigned c
= 0; c
< rt_count
; ++c
) {
707 if (blend
[c
].is_shader
) {
708 fragmeta
->midgard1
.work_count
=
709 MAX2(fragmeta
->midgard1
.work_count
, 8);
714 /* Even on MFBD, the shader descriptor gets blend shaders. It's *also*
715 * copied to the blend_meta appended (by convention), but this is the
716 * field actually read by the hardware. (Or maybe both are read...?).
717 * Specify the last RTi with a blend shader. */
719 fragmeta
->blend
.shader
= 0;
721 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
722 if (!blend
[rt
].is_shader
)
725 fragmeta
->blend
.shader
= blend
[rt
].shader
.gpu
|
726 blend
[rt
].shader
.first_tag
;
730 if (dev
->quirks
& MIDGARD_SFBD
) {
731 /* When only a single render target platform is used, the blend
732 * information is inside the shader meta itself. We additionally
733 * need to signal CAN_DISCARD for nontrivial blend modes (so
734 * we're able to read back the destination buffer) */
736 SET_BIT(fragmeta
->unknown2_3
, MALI_HAS_BLEND_SHADER
,
739 if (!blend
[0].is_shader
) {
740 fragmeta
->blend
.equation
= *blend
[0].equation
.equation
;
741 fragmeta
->blend
.constant
= blend
[0].equation
.constant
;
744 SET_BIT(fragmeta
->unknown2_3
, MALI_CAN_DISCARD
,
745 !blend
[0].no_blending
|| fs
->can_discard
);
747 batch
->draws
|= PIPE_CLEAR_COLOR0
;
751 if (dev
->quirks
& IS_BIFROST
) {
752 bool no_blend
= true;
754 for (unsigned i
= 0; i
< rt_count
; ++i
)
755 no_blend
&= (blend
[i
].no_blending
| blend
[i
].no_colour
);
757 SET_BIT(fragmeta
->bifrost1
.unk1
, MALI_BIFROST_EARLY_Z
,
758 !fs
->can_discard
&& !fs
->writes_depth
&& no_blend
);
761 /* Additional blend descriptor tacked on for jobs using MFBD */
763 for (unsigned i
= 0; i
< rt_count
; ++i
) {
766 if (ctx
->pipe_framebuffer
.nr_cbufs
> i
&& !blend
[i
].no_colour
) {
768 batch
->draws
|= (PIPE_CLEAR_COLOR0
<< i
);
770 bool is_srgb
= (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
771 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
772 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
774 SET_BIT(flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
775 SET_BIT(flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
776 SET_BIT(flags
, MALI_BLEND_SRGB
, is_srgb
);
777 SET_BIT(flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
780 if (dev
->quirks
& IS_BIFROST
) {
781 struct bifrost_blend_rt
*brts
= rts
;
783 brts
[i
].flags
= flags
;
785 if (blend
[i
].is_shader
) {
786 /* The blend shader's address needs to be at
787 * the same top 32 bit as the fragment shader.
788 * TODO: Ensure that's always the case.
790 assert((blend
[i
].shader
.gpu
& (0xffffffffull
<< 32)) ==
791 (fs
->bo
->gpu
& (0xffffffffull
<< 32)));
792 brts
[i
].shader
= blend
[i
].shader
.gpu
;
794 } else if (ctx
->pipe_framebuffer
.nr_cbufs
> i
) {
795 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
796 const struct util_format_description
*format_desc
;
797 format_desc
= util_format_description(format
);
799 brts
[i
].equation
= *blend
[i
].equation
.equation
;
801 /* TODO: this is a bit more complicated */
802 brts
[i
].constant
= blend
[i
].equation
.constant
;
804 brts
[i
].format
= panfrost_format_to_bifrost_blend(format_desc
);
806 /* 0x19 disables blending and forces REPLACE
807 * mode (equivalent to rgb_mode = alpha_mode =
808 * x122, colour mask = 0xF). 0x1a allows
810 brts
[i
].unk2
= blend
[i
].no_blending
? 0x19 : 0x1a;
812 brts
[i
].shader_type
= fs
->blend_types
[i
];
814 /* Dummy attachment for depth-only */
816 brts
[i
].shader_type
= fs
->blend_types
[i
];
819 struct midgard_blend_rt
*mrts
= rts
;
820 mrts
[i
].flags
= flags
;
822 if (blend
[i
].is_shader
) {
823 mrts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
825 mrts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
826 mrts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
833 panfrost_frag_shader_meta_init(struct panfrost_context
*ctx
,
834 struct mali_shader_meta
*fragmeta
,
837 const struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
838 struct panfrost_shader_state
*fs
;
840 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
842 bool msaa
= ctx
->rasterizer
&& ctx
->rasterizer
->base
.multisample
;
843 fragmeta
->coverage_mask
= (msaa
? ctx
->sample_mask
: ~0) & 0xF;
845 fragmeta
->unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x10;
846 fragmeta
->unknown2_4
= 0x4e0;
848 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this
849 * is required (independent of 32-bit/64-bit descriptors), or why it's
850 * not used on later GPU revisions. Otherwise, all shader jobs fault on
851 * these earlier chips (perhaps this is a chicken bit of some kind).
852 * More investigation is needed. */
854 SET_BIT(fragmeta
->unknown2_4
, 0x10, dev
->quirks
& MIDGARD_SFBD
);
856 if (dev
->quirks
& IS_BIFROST
) {
859 /* Depending on whether it's legal to in the given shader, we try to
860 * enable early-z testing. TODO: respect e-z force */
862 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_EARLY_Z
,
863 !fs
->can_discard
&& !fs
->writes_global
&&
864 !fs
->writes_depth
&& !fs
->writes_stencil
&&
865 !ctx
->blend
->base
.alpha_to_coverage
);
867 /* Add the writes Z/S flags if needed. */
868 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_WRITES_Z
, fs
->writes_depth
);
869 SET_BIT(fragmeta
->midgard1
.flags_hi
, MALI_WRITES_S
, fs
->writes_stencil
);
871 /* Any time texturing is used, derivatives are implicitly calculated,
872 * so we need to enable helper invocations */
874 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
,
875 fs
->helper_invocations
);
877 /* If discard is enabled, which bit we set to convey this
878 * depends on if depth/stencil is used for the draw or not.
879 * Just one of depth OR stencil is enough to trigger this. */
881 const struct pipe_depth_stencil_alpha_state
*zsa
= ctx
->depth_stencil
;
882 bool zs_enabled
= fs
->writes_depth
|| fs
->writes_stencil
;
885 zs_enabled
|= (zsa
->depth
.enabled
&& zsa
->depth
.func
!= PIPE_FUNC_ALWAYS
);
886 zs_enabled
|= zsa
->stencil
[0].enabled
;
889 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_READS_TILEBUFFER
,
890 fs
->outputs_read
|| (!zs_enabled
&& fs
->can_discard
));
891 SET_BIT(fragmeta
->midgard1
.flags_lo
, MALI_READS_ZS
, zs_enabled
&& fs
->can_discard
);
894 panfrost_frag_meta_rasterizer_update(ctx
, fragmeta
);
895 panfrost_frag_meta_zsa_update(ctx
, fragmeta
);
896 panfrost_frag_meta_blend_update(ctx
, fragmeta
, rts
);
900 panfrost_emit_shader_meta(struct panfrost_batch
*batch
,
901 enum pipe_shader_type st
,
902 struct mali_vertex_tiler_postfix
*postfix
)
904 struct panfrost_context
*ctx
= batch
->ctx
;
905 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, st
);
912 struct mali_shader_meta meta
;
914 panfrost_shader_meta_init(ctx
, st
, &meta
);
916 /* Add the shader BO to the batch. */
917 panfrost_batch_add_bo(batch
, ss
->bo
,
918 PAN_BO_ACCESS_PRIVATE
|
920 panfrost_bo_access_for_stage(st
));
924 if (st
== PIPE_SHADER_FRAGMENT
) {
925 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
926 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
927 size_t desc_size
= sizeof(meta
);
929 struct panfrost_transfer xfer
;
932 if (dev
->quirks
& MIDGARD_SFBD
)
934 else if (dev
->quirks
& IS_BIFROST
)
935 rt_size
= sizeof(struct bifrost_blend_rt
);
937 rt_size
= sizeof(struct midgard_blend_rt
);
939 desc_size
+= rt_size
* rt_count
;
942 rts
= rzalloc_size(ctx
, rt_size
* rt_count
);
944 panfrost_frag_shader_meta_init(ctx
, &meta
, rts
);
946 xfer
= panfrost_pool_alloc(&batch
->pool
, desc_size
);
948 memcpy(xfer
.cpu
, &meta
, sizeof(meta
));
949 memcpy(xfer
.cpu
+ sizeof(meta
), rts
, rt_size
* rt_count
);
954 shader_ptr
= xfer
.gpu
;
956 shader_ptr
= panfrost_pool_upload(&batch
->pool
, &meta
,
960 postfix
->shader
= shader_ptr
;
964 panfrost_emit_viewport(struct panfrost_batch
*batch
,
965 struct mali_vertex_tiler_postfix
*tiler_postfix
)
967 struct panfrost_context
*ctx
= batch
->ctx
;
968 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
969 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
970 const struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
971 const struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
973 /* Derive min/max from translate/scale. Note since |x| >= 0 by
974 * definition, we have that -|x| <= |x| hence translate - |scale| <=
975 * translate + |scale|, so the ordering is correct here. */
976 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
977 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
978 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
979 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
980 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
981 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
983 /* Scissor to the intersection of viewport and to the scissor, clamped
984 * to the framebuffer */
986 unsigned minx
= MIN2(fb
->width
, vp_minx
);
987 unsigned maxx
= MIN2(fb
->width
, vp_maxx
);
988 unsigned miny
= MIN2(fb
->height
, vp_miny
);
989 unsigned maxy
= MIN2(fb
->height
, vp_maxy
);
991 if (ss
&& rast
&& rast
->scissor
) {
992 minx
= MAX2(ss
->minx
, minx
);
993 miny
= MAX2(ss
->miny
, miny
);
994 maxx
= MIN2(ss
->maxx
, maxx
);
995 maxy
= MIN2(ss
->maxy
, maxy
);
998 struct panfrost_transfer T
= panfrost_pool_alloc(&batch
->pool
, MALI_VIEWPORT_LENGTH
);
1000 pan_pack(T
.cpu
, VIEWPORT
, cfg
) {
1001 cfg
.scissor_minimum_x
= minx
;
1002 cfg
.scissor_minimum_y
= miny
;
1003 cfg
.scissor_maximum_x
= maxx
- 1;
1004 cfg
.scissor_maximum_y
= maxy
- 1;
1006 cfg
.minimum_z
= rast
->depth_clip_near
? minz
: -INFINITY
;
1007 cfg
.maximum_z
= rast
->depth_clip_far
? maxz
: INFINITY
;
1010 tiler_postfix
->viewport
= T
.gpu
;
1011 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1015 panfrost_map_constant_buffer_gpu(struct panfrost_batch
*batch
,
1016 enum pipe_shader_type st
,
1017 struct panfrost_constant_buffer
*buf
,
1020 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
1021 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
1024 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1025 PAN_BO_ACCESS_SHARED
|
1026 PAN_BO_ACCESS_READ
|
1027 panfrost_bo_access_for_stage(st
));
1029 /* Alignment gauranteed by
1030 * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
1031 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
1032 } else if (cb
->user_buffer
) {
1033 return panfrost_pool_upload(&batch
->pool
,
1038 unreachable("No constant buffer");
1042 struct sysval_uniform
{
1052 panfrost_upload_viewport_scale_sysval(struct panfrost_batch
*batch
,
1053 struct sysval_uniform
*uniform
)
1055 struct panfrost_context
*ctx
= batch
->ctx
;
1056 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1058 uniform
->f
[0] = vp
->scale
[0];
1059 uniform
->f
[1] = vp
->scale
[1];
1060 uniform
->f
[2] = vp
->scale
[2];
1064 panfrost_upload_viewport_offset_sysval(struct panfrost_batch
*batch
,
1065 struct sysval_uniform
*uniform
)
1067 struct panfrost_context
*ctx
= batch
->ctx
;
1068 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1070 uniform
->f
[0] = vp
->translate
[0];
1071 uniform
->f
[1] = vp
->translate
[1];
1072 uniform
->f
[2] = vp
->translate
[2];
1075 static void panfrost_upload_txs_sysval(struct panfrost_batch
*batch
,
1076 enum pipe_shader_type st
,
1077 unsigned int sysvalid
,
1078 struct sysval_uniform
*uniform
)
1080 struct panfrost_context
*ctx
= batch
->ctx
;
1081 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
1082 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
1083 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
1084 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
1087 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
1090 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
1091 tex
->u
.tex
.first_level
);
1094 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
1095 tex
->u
.tex
.first_level
);
1098 uniform
->i
[dim
] = tex
->texture
->array_size
;
1102 panfrost_upload_ssbo_sysval(struct panfrost_batch
*batch
,
1103 enum pipe_shader_type st
,
1105 struct sysval_uniform
*uniform
)
1107 struct panfrost_context
*ctx
= batch
->ctx
;
1109 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
1110 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
1112 /* Compute address */
1113 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
1115 panfrost_batch_add_bo(batch
, bo
,
1116 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
1117 panfrost_bo_access_for_stage(st
));
1119 /* Upload address and size as sysval */
1120 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
1121 uniform
->u
[2] = sb
.buffer_size
;
1125 panfrost_upload_sampler_sysval(struct panfrost_batch
*batch
,
1126 enum pipe_shader_type st
,
1128 struct sysval_uniform
*uniform
)
1130 struct panfrost_context
*ctx
= batch
->ctx
;
1131 struct pipe_sampler_state
*sampl
= &ctx
->samplers
[st
][samp_idx
]->base
;
1133 uniform
->f
[0] = sampl
->min_lod
;
1134 uniform
->f
[1] = sampl
->max_lod
;
1135 uniform
->f
[2] = sampl
->lod_bias
;
1137 /* Even without any errata, Midgard represents "no mipmapping" as
1138 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
1139 * panfrost_create_sampler_state which also explains our choice of
1140 * epsilon value (again to keep behaviour consistent) */
1142 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1143 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
1147 panfrost_upload_num_work_groups_sysval(struct panfrost_batch
*batch
,
1148 struct sysval_uniform
*uniform
)
1150 struct panfrost_context
*ctx
= batch
->ctx
;
1152 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
1153 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
1154 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
1158 panfrost_upload_sysvals(struct panfrost_batch
*batch
, void *buf
,
1159 struct panfrost_shader_state
*ss
,
1160 enum pipe_shader_type st
)
1162 struct sysval_uniform
*uniforms
= (void *)buf
;
1164 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1165 int sysval
= ss
->sysval
[i
];
1167 switch (PAN_SYSVAL_TYPE(sysval
)) {
1168 case PAN_SYSVAL_VIEWPORT_SCALE
:
1169 panfrost_upload_viewport_scale_sysval(batch
,
1172 case PAN_SYSVAL_VIEWPORT_OFFSET
:
1173 panfrost_upload_viewport_offset_sysval(batch
,
1176 case PAN_SYSVAL_TEXTURE_SIZE
:
1177 panfrost_upload_txs_sysval(batch
, st
,
1178 PAN_SYSVAL_ID(sysval
),
1181 case PAN_SYSVAL_SSBO
:
1182 panfrost_upload_ssbo_sysval(batch
, st
,
1183 PAN_SYSVAL_ID(sysval
),
1186 case PAN_SYSVAL_NUM_WORK_GROUPS
:
1187 panfrost_upload_num_work_groups_sysval(batch
,
1190 case PAN_SYSVAL_SAMPLER
:
1191 panfrost_upload_sampler_sysval(batch
, st
,
1192 PAN_SYSVAL_ID(sysval
),
1202 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
,
1205 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
1206 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
1209 return rsrc
->bo
->cpu
;
1210 else if (cb
->user_buffer
)
1211 return cb
->user_buffer
;
1213 unreachable("No constant buffer");
1217 panfrost_emit_const_buf(struct panfrost_batch
*batch
,
1218 enum pipe_shader_type stage
,
1219 struct mali_vertex_tiler_postfix
*postfix
)
1221 struct panfrost_context
*ctx
= batch
->ctx
;
1222 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
1227 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[stage
];
1229 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1231 /* Uniforms are implicitly UBO #0 */
1232 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1234 /* Allocate room for the sysval and the uniforms */
1235 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1236 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1237 size_t size
= sys_size
+ uniform_size
;
1238 struct panfrost_transfer transfer
= panfrost_pool_alloc(&batch
->pool
,
1241 /* Upload sysvals requested by the shader */
1242 panfrost_upload_sysvals(batch
, transfer
.cpu
, ss
, stage
);
1244 /* Upload uniforms */
1245 if (has_uniforms
&& uniform_size
) {
1246 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1247 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1250 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1253 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
1254 assert(ubo_count
>= 1);
1256 size_t sz
= MALI_UNIFORM_BUFFER_LENGTH
* ubo_count
;
1257 struct panfrost_transfer ubos
= panfrost_pool_alloc(&batch
->pool
, sz
);
1258 uint64_t *ubo_ptr
= (uint64_t *) ubos
.cpu
;
1260 /* Upload uniforms as a UBO */
1262 if (ss
->uniform_count
) {
1263 pan_pack(ubo_ptr
, UNIFORM_BUFFER
, cfg
) {
1264 cfg
.entries
= ss
->uniform_count
;
1265 cfg
.pointer
= transfer
.gpu
;
1271 /* The rest are honest-to-goodness UBOs */
1273 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1274 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1275 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1276 bool empty
= usz
== 0;
1278 if (!enabled
|| empty
) {
1283 pan_pack(ubo_ptr
+ ubo
, UNIFORM_BUFFER
, cfg
) {
1284 cfg
.entries
= DIV_ROUND_UP(usz
, 16);
1285 cfg
.pointer
= panfrost_map_constant_buffer_gpu(batch
,
1290 postfix
->uniforms
= transfer
.gpu
;
1291 postfix
->uniform_buffers
= ubos
.gpu
;
1293 buf
->dirty_mask
= 0;
1297 panfrost_emit_shared_memory(struct panfrost_batch
*batch
,
1298 const struct pipe_grid_info
*info
,
1299 struct midgard_payload_vertex_tiler
*vtp
)
1301 struct panfrost_context
*ctx
= batch
->ctx
;
1302 struct panfrost_shader_variants
*all
= ctx
->shader
[PIPE_SHADER_COMPUTE
];
1303 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1304 unsigned single_size
= util_next_power_of_two(MAX2(ss
->shared_size
,
1306 unsigned shared_size
= single_size
* info
->grid
[0] * info
->grid
[1] *
1308 struct panfrost_bo
*bo
= panfrost_batch_get_shared_memory(batch
,
1312 struct mali_shared_memory shared
= {
1313 .shared_memory
= bo
->gpu
,
1314 .shared_workgroup_count
=
1315 util_logbase2_ceil(info
->grid
[0]) +
1316 util_logbase2_ceil(info
->grid
[1]) +
1317 util_logbase2_ceil(info
->grid
[2]),
1319 .shared_shift
= util_logbase2(single_size
) - 1
1322 vtp
->postfix
.shared_memory
= panfrost_pool_upload(&batch
->pool
, &shared
,
1327 panfrost_get_tex_desc(struct panfrost_batch
*batch
,
1328 enum pipe_shader_type st
,
1329 struct panfrost_sampler_view
*view
)
1332 return (mali_ptr
) 0;
1334 struct pipe_sampler_view
*pview
= &view
->base
;
1335 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
1337 /* Add the BO to the job so it's retained until the job is done. */
1339 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1340 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1341 panfrost_bo_access_for_stage(st
));
1343 panfrost_batch_add_bo(batch
, view
->bo
,
1344 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1345 panfrost_bo_access_for_stage(st
));
1347 return view
->bo
->gpu
;
1351 panfrost_update_sampler_view(struct panfrost_sampler_view
*view
,
1352 struct pipe_context
*pctx
)
1354 struct panfrost_resource
*rsrc
= pan_resource(view
->base
.texture
);
1355 if (view
->texture_bo
!= rsrc
->bo
->gpu
||
1356 view
->modifier
!= rsrc
->modifier
) {
1357 panfrost_bo_unreference(view
->bo
);
1358 panfrost_create_sampler_view_bo(view
, pctx
, &rsrc
->base
);
1363 panfrost_emit_texture_descriptors(struct panfrost_batch
*batch
,
1364 enum pipe_shader_type stage
,
1365 struct mali_vertex_tiler_postfix
*postfix
)
1367 struct panfrost_context
*ctx
= batch
->ctx
;
1368 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
1370 if (!ctx
->sampler_view_count
[stage
])
1373 if (device
->quirks
& IS_BIFROST
) {
1374 struct bifrost_texture_descriptor
*descriptors
;
1376 descriptors
= malloc(sizeof(struct bifrost_texture_descriptor
) *
1377 ctx
->sampler_view_count
[stage
]);
1379 for (int i
= 0; i
< ctx
->sampler_view_count
[stage
]; ++i
) {
1380 struct panfrost_sampler_view
*view
= ctx
->sampler_views
[stage
][i
];
1381 struct pipe_sampler_view
*pview
= &view
->base
;
1382 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
1383 panfrost_update_sampler_view(view
, &ctx
->base
);
1385 /* Add the BOs to the job so they are retained until the job is done. */
1387 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1388 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1389 panfrost_bo_access_for_stage(stage
));
1391 panfrost_batch_add_bo(batch
, view
->bo
,
1392 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1393 panfrost_bo_access_for_stage(stage
));
1395 memcpy(&descriptors
[i
], view
->bifrost_descriptor
, sizeof(*view
->bifrost_descriptor
));
1398 postfix
->textures
= panfrost_pool_upload(&batch
->pool
,
1400 sizeof(struct bifrost_texture_descriptor
) *
1401 ctx
->sampler_view_count
[stage
]);
1405 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1407 for (int i
= 0; i
< ctx
->sampler_view_count
[stage
]; ++i
) {
1408 struct panfrost_sampler_view
*view
= ctx
->sampler_views
[stage
][i
];
1410 panfrost_update_sampler_view(view
, &ctx
->base
);
1412 trampolines
[i
] = panfrost_get_tex_desc(batch
, stage
, view
);
1415 postfix
->textures
= panfrost_pool_upload(&batch
->pool
,
1418 ctx
->sampler_view_count
[stage
]);
1423 panfrost_emit_sampler_descriptors(struct panfrost_batch
*batch
,
1424 enum pipe_shader_type stage
,
1425 struct mali_vertex_tiler_postfix
*postfix
)
1427 struct panfrost_context
*ctx
= batch
->ctx
;
1428 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
1430 if (!ctx
->sampler_count
[stage
])
1433 if (device
->quirks
& IS_BIFROST
) {
1434 size_t desc_size
= sizeof(struct bifrost_sampler_descriptor
);
1435 size_t transfer_size
= desc_size
* ctx
->sampler_count
[stage
];
1436 struct panfrost_transfer transfer
= panfrost_pool_alloc(&batch
->pool
,
1438 struct bifrost_sampler_descriptor
*desc
= (struct bifrost_sampler_descriptor
*)transfer
.cpu
;
1440 for (int i
= 0; i
< ctx
->sampler_count
[stage
]; ++i
)
1441 desc
[i
] = ctx
->samplers
[stage
][i
]->bifrost_hw
;
1443 postfix
->sampler_descriptor
= transfer
.gpu
;
1445 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
1446 size_t transfer_size
= desc_size
* ctx
->sampler_count
[stage
];
1447 struct panfrost_transfer transfer
= panfrost_pool_alloc(&batch
->pool
,
1449 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*)transfer
.cpu
;
1451 for (int i
= 0; i
< ctx
->sampler_count
[stage
]; ++i
)
1452 desc
[i
] = ctx
->samplers
[stage
][i
]->midgard_hw
;
1454 postfix
->sampler_descriptor
= transfer
.gpu
;
1459 panfrost_emit_vertex_attr_meta(struct panfrost_batch
*batch
,
1460 struct mali_vertex_tiler_postfix
*vertex_postfix
)
1462 struct panfrost_context
*ctx
= batch
->ctx
;
1467 struct panfrost_vertex_state
*so
= ctx
->vertex
;
1469 panfrost_vertex_state_upd_attr_offs(ctx
, vertex_postfix
);
1470 vertex_postfix
->attribute_meta
= panfrost_pool_upload(&batch
->pool
, so
->hw
,
1476 panfrost_emit_vertex_data(struct panfrost_batch
*batch
,
1477 struct mali_vertex_tiler_postfix
*vertex_postfix
)
1479 struct panfrost_context
*ctx
= batch
->ctx
;
1480 struct panfrost_vertex_state
*so
= ctx
->vertex
;
1482 /* Staged mali_attr, and index into them. i =/= k, depending on the
1483 * vertex buffer mask and instancing. Twice as much room is allocated,
1484 * for a worst case of NPOT_DIVIDEs which take up extra slot */
1485 union mali_attr attrs
[PIPE_MAX_ATTRIBS
* 2];
1488 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
1489 /* We map a mali_attr to be 1:1 with the mali_attr_meta, which
1490 * means duplicating some vertex buffers (who cares? aside from
1491 * maybe some caching implications but I somehow doubt that
1494 struct pipe_vertex_element
*elem
= &so
->pipe
[i
];
1495 unsigned vbi
= elem
->vertex_buffer_index
;
1497 /* The exception to 1:1 mapping is that we can have multiple
1498 * entries (NPOT divisors), so we fixup anyways */
1500 so
->hw
[i
].index
= k
;
1502 if (!(ctx
->vb_mask
& (1 << vbi
)))
1505 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
1506 struct panfrost_resource
*rsrc
;
1508 rsrc
= pan_resource(buf
->buffer
.resource
);
1512 /* Align to 64 bytes by masking off the lower bits. This
1513 * will be adjusted back when we fixup the src_offset in
1516 mali_ptr raw_addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
1517 mali_ptr addr
= raw_addr
& ~63;
1518 unsigned chopped_addr
= raw_addr
- addr
;
1520 /* Add a dependency of the batch on the vertex buffer */
1521 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1522 PAN_BO_ACCESS_SHARED
|
1523 PAN_BO_ACCESS_READ
|
1524 PAN_BO_ACCESS_VERTEX_TILER
);
1526 /* Set common fields */
1527 attrs
[k
].elements
= addr
;
1528 attrs
[k
].stride
= buf
->stride
;
1530 /* Since we advanced the base pointer, we shrink the buffer
1532 attrs
[k
].size
= rsrc
->base
.width0
- buf
->buffer_offset
;
1534 /* We need to add the extra size we masked off (for
1535 * correctness) so the data doesn't get clamped away */
1536 attrs
[k
].size
+= chopped_addr
;
1538 /* For non-instancing make sure we initialize */
1539 attrs
[k
].shift
= attrs
[k
].extra_flags
= 0;
1541 /* Instancing uses a dramatically different code path than
1542 * linear, so dispatch for the actual emission now that the
1543 * common code is finished */
1545 unsigned divisor
= elem
->instance_divisor
;
1547 if (divisor
&& ctx
->instance_count
== 1) {
1548 /* Silly corner case where there's a divisor(=1) but
1549 * there's no legitimate instancing. So we want *every*
1550 * attribute to be the same. So set stride to zero so
1551 * we don't go anywhere. */
1553 attrs
[k
].size
= attrs
[k
].stride
+ chopped_addr
;
1554 attrs
[k
].stride
= 0;
1555 attrs
[k
++].elements
|= MALI_ATTR_LINEAR
;
1556 } else if (ctx
->instance_count
<= 1) {
1557 /* Normal, non-instanced attributes */
1558 attrs
[k
++].elements
|= MALI_ATTR_LINEAR
;
1560 unsigned instance_shift
= vertex_postfix
->instance_shift
;
1561 unsigned instance_odd
= vertex_postfix
->instance_odd
;
1563 k
+= panfrost_vertex_instanced(ctx
->padded_count
,
1566 divisor
, &attrs
[k
]);
1570 /* Add special gl_VertexID/gl_InstanceID buffers */
1572 panfrost_vertex_id(ctx
->padded_count
, &attrs
[k
]);
1573 so
->hw
[PAN_VERTEX_ID
].index
= k
++;
1574 panfrost_instance_id(ctx
->padded_count
, &attrs
[k
]);
1575 so
->hw
[PAN_INSTANCE_ID
].index
= k
++;
1577 /* Upload whatever we emitted and go */
1579 vertex_postfix
->attributes
= panfrost_pool_upload(&batch
->pool
, attrs
,
1580 k
* sizeof(*attrs
));
1584 panfrost_emit_varyings(struct panfrost_batch
*batch
, union mali_attr
*slot
,
1585 unsigned stride
, unsigned count
)
1587 /* Fill out the descriptor */
1588 slot
->stride
= stride
;
1589 slot
->size
= stride
* count
;
1590 slot
->shift
= slot
->extra_flags
= 0;
1592 struct panfrost_transfer transfer
= panfrost_pool_alloc(&batch
->pool
,
1595 slot
->elements
= transfer
.gpu
| MALI_ATTR_LINEAR
;
1597 return transfer
.gpu
;
1601 panfrost_streamout_offset(unsigned stride
, unsigned offset
,
1602 struct pipe_stream_output_target
*target
)
1604 return (target
->buffer_offset
+ (offset
* stride
* 4)) & 63;
1608 panfrost_emit_streamout(struct panfrost_batch
*batch
, union mali_attr
*slot
,
1609 unsigned stride
, unsigned offset
, unsigned count
,
1610 struct pipe_stream_output_target
*target
)
1612 /* Fill out the descriptor */
1613 slot
->stride
= stride
* 4;
1614 slot
->shift
= slot
->extra_flags
= 0;
1616 unsigned max_size
= target
->buffer_size
;
1617 unsigned expected_size
= slot
->stride
* count
;
1619 /* Grab the BO and bind it to the batch */
1620 struct panfrost_bo
*bo
= pan_resource(target
->buffer
)->bo
;
1622 /* Varyings are WRITE from the perspective of the VERTEX but READ from
1623 * the perspective of the TILER and FRAGMENT.
1625 panfrost_batch_add_bo(batch
, bo
,
1626 PAN_BO_ACCESS_SHARED
|
1628 PAN_BO_ACCESS_VERTEX_TILER
|
1629 PAN_BO_ACCESS_FRAGMENT
);
1631 /* We will have an offset applied to get alignment */
1632 mali_ptr addr
= bo
->gpu
+ target
->buffer_offset
+ (offset
* slot
->stride
);
1633 slot
->elements
= (addr
& ~63) | MALI_ATTR_LINEAR
;
1634 slot
->size
= MIN2(max_size
, expected_size
) + (addr
& 63);
1638 has_point_coord(unsigned mask
, gl_varying_slot loc
)
1640 if ((loc
>= VARYING_SLOT_TEX0
) && (loc
<= VARYING_SLOT_TEX7
))
1641 return (mask
& (1 << (loc
- VARYING_SLOT_TEX0
)));
1642 else if (loc
== VARYING_SLOT_PNTC
)
1643 return (mask
& (1 << 8));
1648 /* Helpers for manipulating stream out information so we can pack varyings
1649 * accordingly. Compute the src_offset for a given captured varying */
1651 static struct pipe_stream_output
*
1652 pan_get_so(struct pipe_stream_output_info
*info
, gl_varying_slot loc
)
1654 for (unsigned i
= 0; i
< info
->num_outputs
; ++i
) {
1655 if (info
->output
[i
].register_index
== loc
)
1656 return &info
->output
[i
];
1659 unreachable("Varying not captured");
1663 pan_varying_size(enum mali_format fmt
)
1665 unsigned type
= MALI_EXTRACT_TYPE(fmt
);
1666 unsigned chan
= MALI_EXTRACT_CHANNELS(fmt
);
1667 unsigned bits
= MALI_EXTRACT_BITS(fmt
);
1670 if (bits
== MALI_CHANNEL_FLOAT
) {
1672 bool fp16
= (type
== MALI_FORMAT_SINT
);
1673 assert(fp16
|| (type
== MALI_FORMAT_UNORM
));
1677 assert(type
>= MALI_FORMAT_SNORM
&& type
<= MALI_FORMAT_SINT
);
1688 /* Indices for named (non-XFB) varyings that are present. These are packed
1689 * tightly so they correspond to a bitfield present (P) indexed by (1 <<
1690 * PAN_VARY_*). This has the nice property that you can lookup the buffer index
1691 * of a given special field given a shift S by:
1693 * idx = popcount(P & ((1 << S) - 1))
1695 * That is... look at all of the varyings that come earlier and count them, the
1696 * count is the new index since plus one. Likewise, the total number of special
1697 * buffers required is simply popcount(P)
1700 enum pan_special_varying
{
1701 PAN_VARY_GENERAL
= 0,
1702 PAN_VARY_POSITION
= 1,
1704 PAN_VARY_PNTCOORD
= 3,
1706 PAN_VARY_FRAGCOORD
= 5,
1712 /* Given a varying, figure out which index it correpsonds to */
1714 static inline unsigned
1715 pan_varying_index(unsigned present
, enum pan_special_varying v
)
1717 unsigned mask
= (1 << v
) - 1;
1718 return util_bitcount(present
& mask
);
1721 /* Get the base offset for XFB buffers, which by convention come after
1722 * everything else. Wrapper function for semantic reasons; by construction this
1723 * is just popcount. */
1725 static inline unsigned
1726 pan_xfb_base(unsigned present
)
1728 return util_bitcount(present
);
1731 /* Computes the present mask for varyings so we can start emitting varying records */
1733 static inline unsigned
1734 pan_varying_present(
1735 struct panfrost_shader_state
*vs
,
1736 struct panfrost_shader_state
*fs
,
1739 /* At the moment we always emit general and position buffers. Not
1740 * strictly necessary but usually harmless */
1742 unsigned present
= (1 << PAN_VARY_GENERAL
) | (1 << PAN_VARY_POSITION
);
1744 /* Enable special buffers by the shader info */
1746 if (vs
->writes_point_size
)
1747 present
|= (1 << PAN_VARY_PSIZ
);
1749 if (fs
->reads_point_coord
)
1750 present
|= (1 << PAN_VARY_PNTCOORD
);
1753 present
|= (1 << PAN_VARY_FACE
);
1755 if (fs
->reads_frag_coord
&& !(quirks
& IS_BIFROST
))
1756 present
|= (1 << PAN_VARY_FRAGCOORD
);
1758 /* Also, if we have a point sprite, we need a point coord buffer */
1760 for (unsigned i
= 0; i
< fs
->varying_count
; i
++) {
1761 gl_varying_slot loc
= fs
->varyings_loc
[i
];
1763 if (has_point_coord(fs
->point_sprite_mask
, loc
))
1764 present
|= (1 << PAN_VARY_PNTCOORD
);
1770 /* Emitters for varying records */
1772 static struct mali_attr_meta
1773 pan_emit_vary(unsigned present
, enum pan_special_varying buf
,
1774 unsigned quirks
, enum mali_format format
,
1777 unsigned nr_channels
= MALI_EXTRACT_CHANNELS(format
);
1779 struct mali_attr_meta meta
= {
1780 .index
= pan_varying_index(present
, buf
),
1781 .unknown1
= quirks
& IS_BIFROST
? 0x0 : 0x2,
1782 .swizzle
= quirks
& HAS_SWIZZLES
?
1783 panfrost_get_default_swizzle(nr_channels
) :
1784 panfrost_bifrost_swizzle(nr_channels
),
1786 .src_offset
= offset
1792 /* General varying that is unused */
1794 static struct mali_attr_meta
1795 pan_emit_vary_only(unsigned present
, unsigned quirks
)
1797 return pan_emit_vary(present
, 0, quirks
, MALI_VARYING_DISCARD
, 0);
1800 /* Special records */
1802 static const enum mali_format pan_varying_formats
[PAN_VARY_MAX
] = {
1803 [PAN_VARY_POSITION
] = MALI_VARYING_POS
,
1804 [PAN_VARY_PSIZ
] = MALI_R16F
,
1805 [PAN_VARY_PNTCOORD
] = MALI_R16F
,
1806 [PAN_VARY_FACE
] = MALI_R32I
,
1807 [PAN_VARY_FRAGCOORD
] = MALI_RGBA32F
1810 static struct mali_attr_meta
1811 pan_emit_vary_special(unsigned present
, enum pan_special_varying buf
,
1814 assert(buf
< PAN_VARY_MAX
);
1815 return pan_emit_vary(present
, buf
, quirks
, pan_varying_formats
[buf
], 0);
1818 static enum mali_format
1819 pan_xfb_format(enum mali_format format
, unsigned nr
)
1821 if (MALI_EXTRACT_BITS(format
) == MALI_CHANNEL_FLOAT
)
1822 return MALI_R32F
| MALI_NR_CHANNELS(nr
);
1824 return MALI_EXTRACT_TYPE(format
) | MALI_NR_CHANNELS(nr
) | MALI_CHANNEL_32
;
1827 /* Transform feedback records. Note struct pipe_stream_output is (if packed as
1828 * a bitfield) 32-bit, smaller than a 64-bit pointer, so may as well pass by
1831 static struct mali_attr_meta
1832 pan_emit_vary_xfb(unsigned present
,
1834 unsigned *streamout_offsets
,
1836 enum mali_format format
,
1837 struct pipe_stream_output o
)
1839 /* Otherwise construct a record for it */
1840 struct mali_attr_meta meta
= {
1841 /* XFB buffers come after everything else */
1842 .index
= pan_xfb_base(present
) + o
.output_buffer
,
1844 /* As usual unknown bit */
1845 .unknown1
= quirks
& IS_BIFROST
? 0x0 : 0x2,
1847 /* Override swizzle with number of channels */
1848 .swizzle
= quirks
& HAS_SWIZZLES
?
1849 panfrost_get_default_swizzle(o
.num_components
) :
1850 panfrost_bifrost_swizzle(o
.num_components
),
1852 /* Override number of channels and precision to highp */
1853 .format
= pan_xfb_format(format
, o
.num_components
),
1855 /* Apply given offsets together */
1856 .src_offset
= (o
.dst_offset
* 4) /* dwords */
1857 + streamout_offsets
[o
.output_buffer
]
1863 /* Determine if we should capture a varying for XFB. This requires actually
1864 * having a buffer for it. If we don't capture it, we'll fallback to a general
1865 * varying path (linked or unlinked, possibly discarding the write) */
1868 panfrost_xfb_captured(struct panfrost_shader_state
*xfb
,
1869 unsigned loc
, unsigned max_xfb
)
1871 if (!(xfb
->so_mask
& (1ll << loc
)))
1874 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1875 return o
->output_buffer
< max_xfb
;
1878 /* Higher-level wrapper around all of the above, classifying a varying into one
1879 * of the above types */
1881 static struct mali_attr_meta
1882 panfrost_emit_varying(
1883 struct panfrost_shader_state
*stage
,
1884 struct panfrost_shader_state
*other
,
1885 struct panfrost_shader_state
*xfb
,
1888 unsigned *streamout_offsets
,
1890 unsigned *gen_offsets
,
1891 enum mali_format
*gen_formats
,
1892 unsigned *gen_stride
,
1897 gl_varying_slot loc
= stage
->varyings_loc
[idx
];
1898 enum mali_format format
= stage
->varyings
[idx
];
1900 /* Override format to match linkage */
1901 if (!should_alloc
&& gen_formats
[idx
])
1902 format
= gen_formats
[idx
];
1904 if (has_point_coord(stage
->point_sprite_mask
, loc
)) {
1905 return pan_emit_vary_special(present
, PAN_VARY_PNTCOORD
, quirks
);
1906 } else if (panfrost_xfb_captured(xfb
, loc
, max_xfb
)) {
1907 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1908 return pan_emit_vary_xfb(present
, max_xfb
, streamout_offsets
, quirks
, format
, *o
);
1909 } else if (loc
== VARYING_SLOT_POS
) {
1911 return pan_emit_vary_special(present
, PAN_VARY_FRAGCOORD
, quirks
);
1913 return pan_emit_vary_special(present
, PAN_VARY_POSITION
, quirks
);
1914 } else if (loc
== VARYING_SLOT_PSIZ
) {
1915 return pan_emit_vary_special(present
, PAN_VARY_PSIZ
, quirks
);
1916 } else if (loc
== VARYING_SLOT_PNTC
) {
1917 return pan_emit_vary_special(present
, PAN_VARY_PNTCOORD
, quirks
);
1918 } else if (loc
== VARYING_SLOT_FACE
) {
1919 return pan_emit_vary_special(present
, PAN_VARY_FACE
, quirks
);
1922 /* We've exhausted special cases, so it's otherwise a general varying. Check if we're linked */
1923 signed other_idx
= -1;
1925 for (unsigned j
= 0; j
< other
->varying_count
; ++j
) {
1926 if (other
->varyings_loc
[j
] == loc
) {
1933 return pan_emit_vary_only(present
, quirks
);
1935 unsigned offset
= gen_offsets
[other_idx
];
1938 /* We're linked, so allocate a space via a watermark allocation */
1939 enum mali_format alt
= other
->varyings
[other_idx
];
1941 /* Do interpolation at minimum precision */
1942 unsigned size_main
= pan_varying_size(format
);
1943 unsigned size_alt
= pan_varying_size(alt
);
1944 unsigned size
= MIN2(size_main
, size_alt
);
1946 /* If a varying is marked for XFB but not actually captured, we
1947 * should match the format to the format that would otherwise
1948 * be used for XFB, since dEQP checks for invariance here. It's
1949 * unclear if this is required by the spec. */
1951 if (xfb
->so_mask
& (1ull << loc
)) {
1952 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1953 format
= pan_xfb_format(format
, o
->num_components
);
1954 size
= pan_varying_size(format
);
1955 } else if (size
== size_alt
) {
1959 gen_offsets
[idx
] = *gen_stride
;
1960 gen_formats
[other_idx
] = format
;
1961 offset
= *gen_stride
;
1962 *gen_stride
+= size
;
1965 return pan_emit_vary(present
, PAN_VARY_GENERAL
,
1966 quirks
, format
, offset
);
1970 pan_emit_special_input(union mali_attr
*varyings
,
1972 enum pan_special_varying v
,
1975 if (present
& (1 << v
)) {
1976 /* Ensure we write exactly once for performance and with fields
1977 * zeroed appropriately to avoid flakes */
1979 union mali_attr s
= {
1983 varyings
[pan_varying_index(present
, v
)] = s
;
1988 panfrost_emit_varying_descriptor(struct panfrost_batch
*batch
,
1989 unsigned vertex_count
,
1990 struct mali_vertex_tiler_postfix
*vertex_postfix
,
1991 struct mali_vertex_tiler_postfix
*tiler_postfix
,
1992 union midgard_primitive_size
*primitive_size
)
1994 /* Load the shaders */
1995 struct panfrost_context
*ctx
= batch
->ctx
;
1996 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
1997 struct panfrost_shader_state
*vs
, *fs
;
1998 size_t vs_size
, fs_size
;
2000 /* Allocate the varying descriptor */
2002 vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
2003 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
2004 vs_size
= sizeof(struct mali_attr_meta
) * vs
->varying_count
;
2005 fs_size
= sizeof(struct mali_attr_meta
) * fs
->varying_count
;
2007 struct panfrost_transfer trans
= panfrost_pool_alloc(&batch
->pool
,
2011 struct pipe_stream_output_info
*so
= &vs
->stream_output
;
2012 unsigned present
= pan_varying_present(vs
, fs
, dev
->quirks
);
2014 /* Check if this varying is linked by us. This is the case for
2015 * general-purpose, non-captured varyings. If it is, link it. If it's
2016 * not, use the provided stream out information to determine the
2017 * offset, since it was already linked for us. */
2019 unsigned gen_offsets
[32];
2020 enum mali_format gen_formats
[32];
2021 memset(gen_offsets
, 0, sizeof(gen_offsets
));
2022 memset(gen_formats
, 0, sizeof(gen_formats
));
2024 unsigned gen_stride
= 0;
2025 assert(vs
->varying_count
< ARRAY_SIZE(gen_offsets
));
2026 assert(fs
->varying_count
< ARRAY_SIZE(gen_offsets
));
2028 unsigned streamout_offsets
[32];
2030 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
2031 streamout_offsets
[i
] = panfrost_streamout_offset(
2033 ctx
->streamout
.offsets
[i
],
2034 ctx
->streamout
.targets
[i
]);
2037 struct mali_attr_meta
*ovs
= (struct mali_attr_meta
*)trans
.cpu
;
2038 struct mali_attr_meta
*ofs
= ovs
+ vs
->varying_count
;
2040 for (unsigned i
= 0; i
< vs
->varying_count
; i
++) {
2041 ovs
[i
] = panfrost_emit_varying(vs
, fs
, vs
, present
,
2042 ctx
->streamout
.num_targets
, streamout_offsets
,
2044 gen_offsets
, gen_formats
, &gen_stride
, i
, true, false);
2047 for (unsigned i
= 0; i
< fs
->varying_count
; i
++) {
2048 ofs
[i
] = panfrost_emit_varying(fs
, vs
, vs
, present
,
2049 ctx
->streamout
.num_targets
, streamout_offsets
,
2051 gen_offsets
, gen_formats
, &gen_stride
, i
, false, true);
2054 unsigned xfb_base
= pan_xfb_base(present
);
2055 struct panfrost_transfer T
= panfrost_pool_alloc(&batch
->pool
,
2056 sizeof(union mali_attr
) * (xfb_base
+ ctx
->streamout
.num_targets
));
2057 union mali_attr
*varyings
= (union mali_attr
*) T
.cpu
;
2059 /* Emit the stream out buffers */
2061 unsigned out_count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
2064 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
2065 panfrost_emit_streamout(batch
, &varyings
[xfb_base
+ i
],
2067 ctx
->streamout
.offsets
[i
],
2069 ctx
->streamout
.targets
[i
]);
2072 panfrost_emit_varyings(batch
,
2073 &varyings
[pan_varying_index(present
, PAN_VARY_GENERAL
)],
2074 gen_stride
, vertex_count
);
2076 /* fp32 vec4 gl_Position */
2077 tiler_postfix
->position_varying
= panfrost_emit_varyings(batch
,
2078 &varyings
[pan_varying_index(present
, PAN_VARY_POSITION
)],
2079 sizeof(float) * 4, vertex_count
);
2081 if (present
& (1 << PAN_VARY_PSIZ
)) {
2082 primitive_size
->pointer
= panfrost_emit_varyings(batch
,
2083 &varyings
[pan_varying_index(present
, PAN_VARY_PSIZ
)],
2087 pan_emit_special_input(varyings
, present
, PAN_VARY_PNTCOORD
, MALI_VARYING_POINT_COORD
);
2088 pan_emit_special_input(varyings
, present
, PAN_VARY_FACE
, MALI_VARYING_FRONT_FACING
);
2089 pan_emit_special_input(varyings
, present
, PAN_VARY_FRAGCOORD
, MALI_VARYING_FRAG_COORD
);
2091 vertex_postfix
->varyings
= T
.gpu
;
2092 tiler_postfix
->varyings
= T
.gpu
;
2094 vertex_postfix
->varying_meta
= trans
.gpu
;
2095 tiler_postfix
->varying_meta
= trans
.gpu
+ vs_size
;
2099 panfrost_emit_vertex_tiler_jobs(struct panfrost_batch
*batch
,
2100 struct mali_vertex_tiler_prefix
*vertex_prefix
,
2101 struct mali_vertex_tiler_postfix
*vertex_postfix
,
2102 struct mali_vertex_tiler_prefix
*tiler_prefix
,
2103 struct mali_vertex_tiler_postfix
*tiler_postfix
,
2104 union midgard_primitive_size
*primitive_size
)
2106 struct panfrost_context
*ctx
= batch
->ctx
;
2107 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
2108 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->scoreboard
.tiler_dep
;
2109 struct bifrost_payload_vertex bifrost_vertex
= {0,};
2110 struct bifrost_payload_tiler bifrost_tiler
= {0,};
2111 struct midgard_payload_vertex_tiler midgard_vertex
= {0,};
2112 struct midgard_payload_vertex_tiler midgard_tiler
= {0,};
2114 size_t vp_size
, tp_size
;
2116 if (device
->quirks
& IS_BIFROST
) {
2117 bifrost_vertex
.prefix
= *vertex_prefix
;
2118 bifrost_vertex
.postfix
= *vertex_postfix
;
2119 vp
= &bifrost_vertex
;
2120 vp_size
= sizeof(bifrost_vertex
);
2122 bifrost_tiler
.prefix
= *tiler_prefix
;
2123 bifrost_tiler
.tiler
.primitive_size
= *primitive_size
;
2124 bifrost_tiler
.tiler
.tiler_meta
= panfrost_batch_get_tiler_meta(batch
, ~0);
2125 bifrost_tiler
.postfix
= *tiler_postfix
;
2126 tp
= &bifrost_tiler
;
2127 tp_size
= sizeof(bifrost_tiler
);
2129 midgard_vertex
.prefix
= *vertex_prefix
;
2130 midgard_vertex
.postfix
= *vertex_postfix
;
2131 vp
= &midgard_vertex
;
2132 vp_size
= sizeof(midgard_vertex
);
2134 midgard_tiler
.prefix
= *tiler_prefix
;
2135 midgard_tiler
.postfix
= *tiler_postfix
;
2136 midgard_tiler
.primitive_size
= *primitive_size
;
2137 tp
= &midgard_tiler
;
2138 tp_size
= sizeof(midgard_tiler
);
2142 /* Inject in reverse order, with "predicted" job indices.
2143 * THIS IS A HACK XXX */
2144 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_TILER
, false,
2145 batch
->scoreboard
.job_index
+ 2, tp
, tp_size
, true);
2146 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_VERTEX
, false, 0,
2151 /* If rasterizer discard is enable, only submit the vertex */
2153 bool rasterizer_discard
= ctx
->rasterizer
&&
2154 ctx
->rasterizer
->base
.rasterizer_discard
;
2156 unsigned vertex
= panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_VERTEX
, false, 0,
2157 vp
, vp_size
, false);
2159 if (rasterizer_discard
)
2162 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_TILER
, false, vertex
, tp
, tp_size
,
2166 /* TODO: stop hardcoding this */
2168 panfrost_emit_sample_locations(struct panfrost_batch
*batch
)
2170 uint16_t locations
[] = {
2221 return panfrost_pool_upload(&batch
->pool
, locations
, 96 * sizeof(uint16_t));