2 * Copyright (C) 2018 Alyssa Rosenzweig
3 * Copyright (C) 2020 Collabora Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "util/macros.h"
26 #include "util/u_prim.h"
27 #include "util/u_vbuf.h"
29 #include "panfrost-quirks.h"
33 #include "pan_cmdstream.h"
34 #include "pan_context.h"
37 /* If a BO is accessed for a particular shader stage, will it be in the primary
38 * batch (vertex/tiler) or the secondary batch (fragment)? Anything but
39 * fragment will be primary, e.g. compute jobs will be considered
40 * "vertex/tiler" by analogy */
42 static inline uint32_t
43 panfrost_bo_access_for_stage(enum pipe_shader_type stage
)
45 assert(stage
== PIPE_SHADER_FRAGMENT
||
46 stage
== PIPE_SHADER_VERTEX
||
47 stage
== PIPE_SHADER_COMPUTE
);
49 return stage
== PIPE_SHADER_FRAGMENT
?
50 PAN_BO_ACCESS_FRAGMENT
:
51 PAN_BO_ACCESS_VERTEX_TILER
;
55 panfrost_vt_emit_shared_memory(struct panfrost_batch
*batch
)
57 struct panfrost_device
*dev
= pan_device(batch
->ctx
->base
.screen
);
59 struct mali_shared_memory shared
= {
60 .shared_workgroup_count
= ~0,
63 if (batch
->stack_size
) {
64 struct panfrost_bo
*stack
=
65 panfrost_batch_get_scratchpad(batch
, batch
->stack_size
,
66 dev
->thread_tls_alloc
,
69 shared
.stack_shift
= panfrost_get_stack_shift(batch
->stack_size
);
70 shared
.scratchpad
= stack
->gpu
;
73 return panfrost_pool_upload_aligned(&batch
->pool
, &shared
, sizeof(shared
), 64);
77 panfrost_vt_update_rasterizer(struct panfrost_rasterizer
*rasterizer
,
78 struct mali_vertex_tiler_prefix
*prefix
,
79 struct mali_vertex_tiler_postfix
*postfix
)
81 postfix
->gl_enables
|= 0x7;
82 SET_BIT(postfix
->gl_enables
, MALI_FRONT_CCW_TOP
,
83 rasterizer
->base
.front_ccw
);
84 SET_BIT(postfix
->gl_enables
, MALI_CULL_FACE_FRONT
,
85 (rasterizer
->base
.cull_face
& PIPE_FACE_FRONT
));
86 SET_BIT(postfix
->gl_enables
, MALI_CULL_FACE_BACK
,
87 (rasterizer
->base
.cull_face
& PIPE_FACE_BACK
));
88 SET_BIT(prefix
->unknown_draw
, MALI_DRAW_FLATSHADE_FIRST
,
89 rasterizer
->base
.flatshade_first
);
93 panfrost_vt_update_primitive_size(struct panfrost_context
*ctx
,
94 struct mali_vertex_tiler_prefix
*prefix
,
95 union midgard_primitive_size
*primitive_size
)
97 struct panfrost_rasterizer
*rasterizer
= ctx
->rasterizer
;
99 if (!panfrost_writes_point_size(ctx
)) {
100 float val
= (prefix
->draw_mode
== MALI_DRAW_MODE_POINTS
) ?
101 rasterizer
->base
.point_size
:
102 rasterizer
->base
.line_width
;
104 primitive_size
->constant
= val
;
109 panfrost_vt_update_occlusion_query(struct panfrost_context
*ctx
,
110 struct mali_vertex_tiler_postfix
*postfix
)
112 SET_BIT(postfix
->gl_enables
, MALI_OCCLUSION_QUERY
, ctx
->occlusion_query
);
113 if (ctx
->occlusion_query
) {
114 postfix
->occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
115 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
116 PAN_BO_ACCESS_SHARED
|
118 PAN_BO_ACCESS_FRAGMENT
);
120 postfix
->occlusion_counter
= 0;
125 panfrost_vt_init(struct panfrost_context
*ctx
,
126 enum pipe_shader_type stage
,
127 struct mali_vertex_tiler_prefix
*prefix
,
128 struct mali_vertex_tiler_postfix
*postfix
)
130 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
131 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
133 if (!ctx
->shader
[stage
])
136 memset(prefix
, 0, sizeof(*prefix
));
137 memset(postfix
, 0, sizeof(*postfix
));
139 if (device
->quirks
& IS_BIFROST
) {
140 postfix
->gl_enables
= 0x2;
141 postfix
->shared_memory
= panfrost_vt_emit_shared_memory(batch
);
143 postfix
->gl_enables
= 0x6;
144 postfix
->shared_memory
= panfrost_batch_reserve_framebuffer(batch
);
147 if (stage
== PIPE_SHADER_FRAGMENT
) {
148 panfrost_vt_update_occlusion_query(ctx
, postfix
);
149 panfrost_vt_update_rasterizer(ctx
->rasterizer
, prefix
, postfix
);
154 panfrost_translate_index_size(unsigned size
)
158 return MALI_DRAW_INDEXED_UINT8
;
161 return MALI_DRAW_INDEXED_UINT16
;
164 return MALI_DRAW_INDEXED_UINT32
;
167 unreachable("Invalid index size");
171 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
172 * good for the duration of the draw (transient), could last longer. Also get
173 * the bounds on the index buffer for the range accessed by the draw. We do
174 * these operations together because there are natural optimizations which
175 * require them to be together. */
178 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
,
179 const struct pipe_draw_info
*info
,
180 unsigned *min_index
, unsigned *max_index
)
182 struct panfrost_resource
*rsrc
= pan_resource(info
->index
.resource
);
183 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
184 off_t offset
= info
->start
* info
->index_size
;
185 bool needs_indices
= true;
188 if (info
->max_index
!= ~0u) {
189 *min_index
= info
->min_index
;
190 *max_index
= info
->max_index
;
191 needs_indices
= false;
194 if (!info
->has_user_indices
) {
195 /* Only resources can be directly mapped */
196 panfrost_batch_add_bo(batch
, rsrc
->bo
,
197 PAN_BO_ACCESS_SHARED
|
199 PAN_BO_ACCESS_VERTEX_TILER
);
200 out
= rsrc
->bo
->gpu
+ offset
;
202 /* Check the cache */
203 needs_indices
= !panfrost_minmax_cache_get(rsrc
->index_cache
,
209 /* Otherwise, we need to upload to transient memory */
210 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
211 struct panfrost_transfer T
=
212 panfrost_pool_alloc_aligned(&batch
->pool
,
213 info
->count
* info
->index_size
,
216 memcpy(T
.cpu
, ibuf8
+ offset
, info
->count
* info
->index_size
);
222 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
224 if (!info
->has_user_indices
)
225 panfrost_minmax_cache_add(rsrc
->index_cache
,
226 info
->start
, info
->count
,
227 *min_index
, *max_index
);
234 panfrost_vt_set_draw_info(struct panfrost_context
*ctx
,
235 const struct pipe_draw_info
*info
,
236 enum mali_draw_mode draw_mode
,
237 struct mali_vertex_tiler_postfix
*vertex_postfix
,
238 struct mali_vertex_tiler_prefix
*tiler_prefix
,
239 struct mali_vertex_tiler_postfix
*tiler_postfix
,
240 unsigned *vertex_count
,
241 unsigned *padded_count
)
243 tiler_prefix
->draw_mode
= draw_mode
;
245 unsigned draw_flags
= 0;
247 if (panfrost_writes_point_size(ctx
))
248 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
250 if (info
->primitive_restart
)
251 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
253 /* These doesn't make much sense */
255 draw_flags
|= 0x3000;
257 if (info
->index_size
) {
258 unsigned min_index
= 0, max_index
= 0;
260 tiler_prefix
->indices
= panfrost_get_index_buffer_bounded(ctx
,
265 /* Use the corresponding values */
266 *vertex_count
= max_index
- min_index
+ 1;
267 tiler_postfix
->offset_start
= vertex_postfix
->offset_start
= min_index
+ info
->index_bias
;
268 tiler_prefix
->offset_bias_correction
= -min_index
;
269 tiler_prefix
->index_count
= MALI_POSITIVE(info
->count
);
270 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
272 tiler_prefix
->indices
= 0;
273 *vertex_count
= ctx
->vertex_count
;
274 tiler_postfix
->offset_start
= vertex_postfix
->offset_start
= info
->start
;
275 tiler_prefix
->offset_bias_correction
= 0;
276 tiler_prefix
->index_count
= MALI_POSITIVE(ctx
->vertex_count
);
279 tiler_prefix
->unknown_draw
= draw_flags
;
281 /* Encode the padded vertex count */
283 if (info
->instance_count
> 1) {
284 *padded_count
= panfrost_padded_vertex_count(*vertex_count
);
286 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
287 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
289 tiler_postfix
->instance_shift
= vertex_postfix
->instance_shift
= shift
;
290 tiler_postfix
->instance_odd
= vertex_postfix
->instance_odd
= k
;
292 *padded_count
= *vertex_count
;
294 /* Reset instancing state */
295 tiler_postfix
->instance_shift
= vertex_postfix
->instance_shift
= 0;
296 tiler_postfix
->instance_odd
= vertex_postfix
->instance_odd
= 0;
301 translate_tex_wrap(enum pipe_tex_wrap w
)
304 case PIPE_TEX_WRAP_REPEAT
: return MALI_WRAP_MODE_REPEAT
;
305 case PIPE_TEX_WRAP_CLAMP
: return MALI_WRAP_MODE_CLAMP
;
306 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
: return MALI_WRAP_MODE_CLAMP_TO_EDGE
;
307 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
: return MALI_WRAP_MODE_CLAMP_TO_BORDER
;
308 case PIPE_TEX_WRAP_MIRROR_REPEAT
: return MALI_WRAP_MODE_MIRRORED_REPEAT
;
309 case PIPE_TEX_WRAP_MIRROR_CLAMP
: return MALI_WRAP_MODE_MIRRORED_CLAMP
;
310 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE
;
311 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER
;
312 default: unreachable("Invalid wrap");
316 /* The hardware compares in the wrong order order, so we have to flip before
317 * encoding. Yes, really. */
319 static enum mali_func
320 panfrost_sampler_compare_func(const struct pipe_sampler_state
*cso
)
322 if (!cso
->compare_mode
)
323 return MALI_FUNC_NEVER
;
325 enum mali_func f
= panfrost_translate_compare_func(cso
->compare_func
);
326 return panfrost_flip_compare_func(f
);
329 static enum mali_mipmap_mode
330 pan_pipe_to_mipmode(enum pipe_tex_mipfilter f
)
333 case PIPE_TEX_MIPFILTER_NEAREST
: return MALI_MIPMAP_MODE_NEAREST
;
334 case PIPE_TEX_MIPFILTER_LINEAR
: return MALI_MIPMAP_MODE_TRILINEAR
;
335 case PIPE_TEX_MIPFILTER_NONE
: return MALI_MIPMAP_MODE_NONE
;
336 default: unreachable("Invalid");
340 void panfrost_sampler_desc_init(const struct pipe_sampler_state
*cso
,
341 struct mali_midgard_sampler_packed
*hw
)
343 pan_pack(hw
, MIDGARD_SAMPLER
, cfg
) {
344 cfg
.magnify_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
345 cfg
.minify_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
346 cfg
.mipmap_mode
= (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
) ?
347 MALI_MIPMAP_MODE_TRILINEAR
: MALI_MIPMAP_MODE_NEAREST
;
348 cfg
.normalized_coordinates
= cso
->normalized_coords
;
350 cfg
.lod_bias
= FIXED_16(cso
->lod_bias
, true);
352 cfg
.minimum_lod
= FIXED_16(cso
->min_lod
, false);
354 /* If necessary, we disable mipmapping in the sampler descriptor by
355 * clamping the LOD as tight as possible (from 0 to epsilon,
356 * essentially -- remember these are fixed point numbers, so
359 cfg
.maximum_lod
= (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) ?
360 cfg
.minimum_lod
+ 1 :
361 FIXED_16(cso
->max_lod
, false);
363 cfg
.wrap_mode_s
= translate_tex_wrap(cso
->wrap_s
);
364 cfg
.wrap_mode_t
= translate_tex_wrap(cso
->wrap_t
);
365 cfg
.wrap_mode_r
= translate_tex_wrap(cso
->wrap_r
);
367 cfg
.compare_function
= panfrost_sampler_compare_func(cso
);
368 cfg
.seamless_cube_map
= cso
->seamless_cube_map
;
370 cfg
.border_color_r
= cso
->border_color
.f
[0];
371 cfg
.border_color_g
= cso
->border_color
.f
[1];
372 cfg
.border_color_b
= cso
->border_color
.f
[2];
373 cfg
.border_color_a
= cso
->border_color
.f
[3];
377 void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state
*cso
,
378 struct mali_bifrost_sampler_packed
*hw
)
380 pan_pack(hw
, BIFROST_SAMPLER
, cfg
) {
381 cfg
.magnify_linear
= cso
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
;
382 cfg
.minify_linear
= cso
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
;
383 cfg
.mipmap_mode
= pan_pipe_to_mipmode(cso
->min_mip_filter
);
384 cfg
.normalized_coordinates
= cso
->normalized_coords
;
386 cfg
.lod_bias
= FIXED_16(cso
->lod_bias
, true);
387 cfg
.minimum_lod
= FIXED_16(cso
->min_lod
, false);
388 cfg
.maximum_lod
= FIXED_16(cso
->max_lod
, false);
390 cfg
.wrap_mode_s
= translate_tex_wrap(cso
->wrap_s
);
391 cfg
.wrap_mode_t
= translate_tex_wrap(cso
->wrap_t
);
392 cfg
.wrap_mode_r
= translate_tex_wrap(cso
->wrap_r
);
394 cfg
.compare_function
= panfrost_sampler_compare_func(cso
);
395 cfg
.seamless_cube_map
= cso
->seamless_cube_map
;
400 panfrost_fs_required(
401 struct panfrost_shader_state
*fs
,
402 struct panfrost_blend_final
*blend
,
405 /* If we generally have side effects */
409 /* If colour is written we need to execute */
410 for (unsigned i
= 0; i
< rt_count
; ++i
) {
411 if (!blend
[i
].no_colour
)
415 /* If depth is written and not implied we need to execute.
416 * TODO: Predicate on Z/S writes being enabled */
417 return (fs
->writes_depth
|| fs
->writes_stencil
);
421 panfrost_emit_blend(struct panfrost_batch
*batch
, void *rts
,
422 struct panfrost_blend_final
*blend
)
424 const struct panfrost_device
*dev
= pan_device(batch
->ctx
->base
.screen
);
425 struct panfrost_shader_state
*fs
= panfrost_get_shader_state(batch
->ctx
, PIPE_SHADER_FRAGMENT
);
426 unsigned rt_count
= batch
->key
.nr_cbufs
;
428 struct bifrost_blend_rt
*brts
= rts
;
430 /* Disable blending for depth-only */
433 if (dev
->quirks
& IS_BIFROST
) {
434 memset(brts
, 0, sizeof(*brts
));
437 pan_pack(rts
, MIDGARD_BLEND_OPAQUE
, cfg
) {
438 cfg
.equation
= 0xf0122122; /* Replace */
443 for (unsigned i
= 0; i
< rt_count
; ++i
) {
444 struct mali_blend_flags_packed flags
= {};
446 pan_pack(&flags
, BLEND_FLAGS
, cfg
) {
447 if (blend
[i
].no_colour
) {
452 batch
->draws
|= (PIPE_CLEAR_COLOR0
<< i
);
454 cfg
.srgb
= util_format_is_srgb(batch
->key
.cbufs
[i
]->format
);
455 cfg
.load_destination
= blend
[i
].load_dest
;
456 cfg
.dither_disable
= !batch
->ctx
->blend
->base
.dither
;
458 if (!(dev
->quirks
& IS_BIFROST
))
459 cfg
.midgard_blend_shader
= blend
[i
].is_shader
;
462 if (dev
->quirks
& IS_BIFROST
) {
463 memset(brts
+ i
, 0, sizeof(brts
[i
]));
464 brts
[i
].flags
= flags
.opaque
[0];
466 if (blend
[i
].is_shader
) {
467 /* The blend shader's address needs to be at
468 * the same top 32 bit as the fragment shader.
469 * TODO: Ensure that's always the case.
471 assert((blend
[i
].shader
.gpu
& (0xffffffffull
<< 32)) ==
472 (fs
->bo
->gpu
& (0xffffffffull
<< 32)));
473 brts
[i
].shader
= blend
[i
].shader
.gpu
;
476 enum pipe_format format
= batch
->key
.cbufs
[i
]->format
;
477 const struct util_format_description
*format_desc
;
478 format_desc
= util_format_description(format
);
480 brts
[i
].equation
= blend
[i
].equation
.equation
;
482 /* TODO: this is a bit more complicated */
483 brts
[i
].constant
= blend
[i
].equation
.constant
;
485 brts
[i
].format
= panfrost_format_to_bifrost_blend(format_desc
);
487 /* 0x19 disables blending and forces REPLACE
488 * mode (equivalent to rgb_mode = alpha_mode =
489 * x122, colour mask = 0xF). 0x1a allows
491 brts
[i
].unk2
= blend
[i
].opaque
? 0x19 : 0x1a;
493 brts
[i
].shader_type
= fs
->blend_types
[i
];
496 pan_pack(rts
, MIDGARD_BLEND_OPAQUE
, cfg
) {
499 if (blend
[i
].is_shader
) {
500 cfg
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
502 cfg
.equation
= blend
[i
].equation
.equation
.opaque
[0];
503 cfg
.constant
= blend
[i
].equation
.constant
;
507 rts
+= MALI_MIDGARD_BLEND_LENGTH
;
513 panfrost_emit_frag_shader(struct panfrost_context
*ctx
,
514 struct mali_state_packed
*fragmeta
,
515 struct panfrost_blend_final
*blend
)
517 const struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
518 struct panfrost_shader_state
*fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
519 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
520 const struct panfrost_zsa_state
*zsa
= ctx
->depth_stencil
;
521 unsigned rt_count
= ctx
->pipe_framebuffer
.nr_cbufs
;
522 bool alpha_to_coverage
= ctx
->blend
->base
.alpha_to_coverage
;
525 struct mali_shader_packed shader
= fs
->shader
;
526 struct mali_preload_packed preload
= fs
->preload
;
528 struct mali_multisample_misc_packed multisample_misc
;
529 struct mali_stencil_mask_misc_packed stencil_mask_misc
;
530 union midgard_blend sfbd_blend
= { 0 };
532 if (!panfrost_fs_required(fs
, blend
, rt_count
)) {
533 if (dev
->quirks
& IS_BIFROST
) {
534 pan_pack(&shader
, SHADER
, cfg
) {}
536 pan_pack(&properties
, BIFROST_PROPERTIES
, cfg
) {
537 cfg
.unknown
= 0x950020; /* XXX */
538 cfg
.early_z_enable
= true;
541 preload
.opaque
[0] = 0;
543 pan_pack(&shader
, SHADER
, cfg
) {
547 pan_pack(&properties
, MIDGARD_PROPERTIES
, cfg
) {
548 cfg
.work_register_count
= 1;
549 cfg
.depth_source
= MALI_DEPTH_SOURCE_FIXED_FUNCTION
;
550 cfg
.early_z_enable
= true;
553 } else if (dev
->quirks
& IS_BIFROST
) {
554 bool no_blend
= true;
556 for (unsigned i
= 0; i
< rt_count
; ++i
)
557 no_blend
&= (!blend
[i
].load_dest
| blend
[i
].no_colour
);
559 pan_pack(&properties
, BIFROST_PROPERTIES
, cfg
) {
560 cfg
.early_z_enable
= !fs
->can_discard
&& !fs
->writes_depth
&& no_blend
;
563 /* Combine with prepacked properties */
564 properties
|= fs
->properties
.opaque
[0];
566 /* Reasons to disable early-Z from a shader perspective */
567 bool late_z
= fs
->can_discard
|| fs
->writes_global
||
568 fs
->writes_depth
|| fs
->writes_stencil
;
570 /* If either depth or stencil is enabled, discard matters */
572 (zsa
->base
.depth
.enabled
&& zsa
->base
.depth
.func
!= PIPE_FUNC_ALWAYS
) ||
573 zsa
->base
.stencil
[0].enabled
;
575 bool has_blend_shader
= false;
577 for (unsigned c
= 0; c
< rt_count
; ++c
)
578 has_blend_shader
|= blend
[c
].is_shader
;
580 pan_pack(&properties
, MIDGARD_PROPERTIES
, cfg
) {
581 /* TODO: Reduce this limit? */
582 if (has_blend_shader
)
583 cfg
.work_register_count
= MAX2(fs
->work_reg_count
, 8);
585 cfg
.work_register_count
= fs
->work_reg_count
;
587 cfg
.early_z_enable
= !(late_z
|| alpha_to_coverage
);
588 cfg
.reads_tilebuffer
= fs
->outputs_read
|| (!zs_enabled
&& fs
->can_discard
);
589 cfg
.reads_depth_stencil
= zs_enabled
&& fs
->can_discard
;
592 properties
|= fs
->properties
.opaque
[0];
595 pan_pack(&multisample_misc
, MULTISAMPLE_MISC
, cfg
) {
596 bool msaa
= rast
->multisample
;
597 cfg
.multisample_enable
= msaa
;
598 cfg
.sample_mask
= (msaa
? ctx
->sample_mask
: ~0) & 0xFFFF;
600 /* EXT_shader_framebuffer_fetch requires per-sample */
601 bool per_sample
= ctx
->min_samples
> 1 || fs
->outputs_read
;
602 cfg
.evaluate_per_sample
= msaa
&& per_sample
;
604 if (dev
->quirks
& MIDGARD_SFBD
) {
605 cfg
.sfbd_load_destination
= blend
[0].load_dest
;
606 cfg
.sfbd_blend_shader
= blend
[0].is_shader
;
609 cfg
.depth_function
= zsa
->base
.depth
.enabled
?
610 panfrost_translate_compare_func(zsa
->base
.depth
.func
) :
613 cfg
.depth_write_mask
= zsa
->base
.depth
.writemask
;
614 cfg
.near_discard
= rast
->depth_clip_near
;
615 cfg
.far_discard
= rast
->depth_clip_far
;
616 cfg
.unknown_2
= true;
619 pan_pack(&stencil_mask_misc
, STENCIL_MASK_MISC
, cfg
) {
620 cfg
.stencil_mask_front
= zsa
->stencil_mask_front
;
621 cfg
.stencil_mask_back
= zsa
->stencil_mask_back
;
622 cfg
.stencil_enable
= zsa
->base
.stencil
[0].enabled
;
623 cfg
.alpha_to_coverage
= alpha_to_coverage
;
625 if (dev
->quirks
& MIDGARD_SFBD
) {
626 cfg
.sfbd_write_enable
= !blend
[0].no_colour
;
627 cfg
.sfbd_srgb
= util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
628 cfg
.sfbd_dither_disable
= !ctx
->blend
->base
.dither
;
632 cfg
.depth_range_1
= cfg
.depth_range_2
= rast
->offset_tri
;
633 cfg
.single_sampled_lines
= !rast
->multisample
;
636 if (dev
->quirks
& MIDGARD_SFBD
) {
637 if (blend
[0].is_shader
) {
638 sfbd_blend
.shader
= blend
[0].shader
.gpu
|
639 blend
[0].shader
.first_tag
;
641 sfbd_blend
.equation
= blend
[0].equation
.equation
;
642 sfbd_blend
.constant
= blend
[0].equation
.constant
;
644 } else if (!(dev
->quirks
& IS_BIFROST
)) {
645 /* Bug where MRT-capable hw apparently reads the last blend
646 * shader from here instead of the usual location? */
648 for (signed rt
= ((signed) rt_count
- 1); rt
>= 0; --rt
) {
649 if (!blend
[rt
].is_shader
)
652 sfbd_blend
.shader
= blend
[rt
].shader
.gpu
|
653 blend
[rt
].shader
.first_tag
;
658 pan_pack(fragmeta
, STATE_OPAQUE
, cfg
) {
659 cfg
.shader
= fs
->shader
;
660 cfg
.properties
= properties
;
661 cfg
.depth_units
= rast
->offset_units
* 2.0f
;
662 cfg
.depth_factor
= rast
->offset_scale
;
663 cfg
.multisample_misc
= multisample_misc
;
664 cfg
.stencil_mask_misc
= stencil_mask_misc
;
666 cfg
.stencil_front
= zsa
->stencil_front
;
667 cfg
.stencil_back
= zsa
->stencil_back
;
669 /* Bottom bits for stencil ref, exactly one word */
670 bool back_enab
= zsa
->base
.stencil
[1].enabled
;
671 cfg
.stencil_front
.opaque
[0] |= ctx
->stencil_ref
.ref_value
[0];
672 cfg
.stencil_back
.opaque
[0] |= ctx
->stencil_ref
.ref_value
[back_enab
? 1 : 0];
674 if (dev
->quirks
& IS_BIFROST
)
675 cfg
.preload
= preload
;
677 memcpy(&cfg
.sfbd_blend
, &sfbd_blend
, sizeof(sfbd_blend
));
682 panfrost_emit_compute_shader_meta(struct panfrost_batch
*batch
, enum pipe_shader_type stage
)
684 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(batch
->ctx
, stage
);
686 panfrost_batch_add_bo(batch
, ss
->bo
,
687 PAN_BO_ACCESS_PRIVATE
|
689 PAN_BO_ACCESS_VERTEX_TILER
);
691 panfrost_batch_add_bo(batch
, pan_resource(ss
->upload
.rsrc
)->bo
,
692 PAN_BO_ACCESS_PRIVATE
|
694 PAN_BO_ACCESS_VERTEX_TILER
);
696 return pan_resource(ss
->upload
.rsrc
)->bo
->gpu
+ ss
->upload
.offset
;
700 panfrost_emit_frag_shader_meta(struct panfrost_batch
*batch
)
702 struct panfrost_context
*ctx
= batch
->ctx
;
703 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
705 /* Add the shader BO to the batch. */
706 panfrost_batch_add_bo(batch
, ss
->bo
,
707 PAN_BO_ACCESS_PRIVATE
|
709 PAN_BO_ACCESS_FRAGMENT
);
711 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
712 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
713 struct panfrost_transfer xfer
;
716 if (dev
->quirks
& MIDGARD_SFBD
)
718 else if (dev
->quirks
& IS_BIFROST
)
719 rt_size
= sizeof(struct bifrost_blend_rt
);
721 rt_size
= sizeof(struct midgard_blend_rt
);
723 unsigned desc_size
= MALI_STATE_LENGTH
+ rt_size
* rt_count
;
724 xfer
= panfrost_pool_alloc_aligned(&batch
->pool
, desc_size
, MALI_STATE_LENGTH
);
726 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
728 for (unsigned c
= 0; c
< ctx
->pipe_framebuffer
.nr_cbufs
; ++c
)
729 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
731 panfrost_emit_frag_shader(ctx
, (struct mali_state_packed
*) xfer
.cpu
, blend
);
733 if (!(dev
->quirks
& MIDGARD_SFBD
))
734 panfrost_emit_blend(batch
, xfer
.cpu
+ MALI_STATE_LENGTH
, blend
);
736 batch
->draws
|= PIPE_CLEAR_COLOR0
;
742 panfrost_emit_viewport(struct panfrost_batch
*batch
)
744 struct panfrost_context
*ctx
= batch
->ctx
;
745 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
746 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
747 const struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
748 const struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
750 /* Derive min/max from translate/scale. Note since |x| >= 0 by
751 * definition, we have that -|x| <= |x| hence translate - |scale| <=
752 * translate + |scale|, so the ordering is correct here. */
753 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
754 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
755 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
756 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
757 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
758 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
760 /* Scissor to the intersection of viewport and to the scissor, clamped
761 * to the framebuffer */
763 unsigned minx
= MIN2(fb
->width
, vp_minx
);
764 unsigned maxx
= MIN2(fb
->width
, vp_maxx
);
765 unsigned miny
= MIN2(fb
->height
, vp_miny
);
766 unsigned maxy
= MIN2(fb
->height
, vp_maxy
);
768 if (ss
&& rast
->scissor
) {
769 minx
= MAX2(ss
->minx
, minx
);
770 miny
= MAX2(ss
->miny
, miny
);
771 maxx
= MIN2(ss
->maxx
, maxx
);
772 maxy
= MIN2(ss
->maxy
, maxy
);
775 struct panfrost_transfer T
= panfrost_pool_alloc(&batch
->pool
, MALI_VIEWPORT_LENGTH
);
777 pan_pack(T
.cpu
, VIEWPORT
, cfg
) {
778 cfg
.scissor_minimum_x
= minx
;
779 cfg
.scissor_minimum_y
= miny
;
780 cfg
.scissor_maximum_x
= maxx
- 1;
781 cfg
.scissor_maximum_y
= maxy
- 1;
783 cfg
.minimum_z
= rast
->depth_clip_near
? minz
: -INFINITY
;
784 cfg
.maximum_z
= rast
->depth_clip_far
? maxz
: INFINITY
;
787 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
792 panfrost_map_constant_buffer_gpu(struct panfrost_batch
*batch
,
793 enum pipe_shader_type st
,
794 struct panfrost_constant_buffer
*buf
,
797 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
798 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
801 panfrost_batch_add_bo(batch
, rsrc
->bo
,
802 PAN_BO_ACCESS_SHARED
|
804 panfrost_bo_access_for_stage(st
));
806 /* Alignment gauranteed by
807 * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
808 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
809 } else if (cb
->user_buffer
) {
810 return panfrost_pool_upload_aligned(&batch
->pool
,
813 cb
->buffer_size
, 16);
815 unreachable("No constant buffer");
819 struct sysval_uniform
{
829 panfrost_upload_viewport_scale_sysval(struct panfrost_batch
*batch
,
830 struct sysval_uniform
*uniform
)
832 struct panfrost_context
*ctx
= batch
->ctx
;
833 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
835 uniform
->f
[0] = vp
->scale
[0];
836 uniform
->f
[1] = vp
->scale
[1];
837 uniform
->f
[2] = vp
->scale
[2];
841 panfrost_upload_viewport_offset_sysval(struct panfrost_batch
*batch
,
842 struct sysval_uniform
*uniform
)
844 struct panfrost_context
*ctx
= batch
->ctx
;
845 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
847 uniform
->f
[0] = vp
->translate
[0];
848 uniform
->f
[1] = vp
->translate
[1];
849 uniform
->f
[2] = vp
->translate
[2];
852 static void panfrost_upload_txs_sysval(struct panfrost_batch
*batch
,
853 enum pipe_shader_type st
,
854 unsigned int sysvalid
,
855 struct sysval_uniform
*uniform
)
857 struct panfrost_context
*ctx
= batch
->ctx
;
858 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
859 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
860 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
861 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
864 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
867 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
868 tex
->u
.tex
.first_level
);
871 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
872 tex
->u
.tex
.first_level
);
875 uniform
->i
[dim
] = tex
->texture
->array_size
;
879 panfrost_upload_ssbo_sysval(struct panfrost_batch
*batch
,
880 enum pipe_shader_type st
,
882 struct sysval_uniform
*uniform
)
884 struct panfrost_context
*ctx
= batch
->ctx
;
886 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
887 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
889 /* Compute address */
890 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
892 panfrost_batch_add_bo(batch
, bo
,
893 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
894 panfrost_bo_access_for_stage(st
));
896 /* Upload address and size as sysval */
897 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
898 uniform
->u
[2] = sb
.buffer_size
;
902 panfrost_upload_sampler_sysval(struct panfrost_batch
*batch
,
903 enum pipe_shader_type st
,
905 struct sysval_uniform
*uniform
)
907 struct panfrost_context
*ctx
= batch
->ctx
;
908 struct pipe_sampler_state
*sampl
= &ctx
->samplers
[st
][samp_idx
]->base
;
910 uniform
->f
[0] = sampl
->min_lod
;
911 uniform
->f
[1] = sampl
->max_lod
;
912 uniform
->f
[2] = sampl
->lod_bias
;
914 /* Even without any errata, Midgard represents "no mipmapping" as
915 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
916 * panfrost_create_sampler_state which also explains our choice of
917 * epsilon value (again to keep behaviour consistent) */
919 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
920 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
924 panfrost_upload_num_work_groups_sysval(struct panfrost_batch
*batch
,
925 struct sysval_uniform
*uniform
)
927 struct panfrost_context
*ctx
= batch
->ctx
;
929 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
930 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
931 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
935 panfrost_upload_sysvals(struct panfrost_batch
*batch
, void *buf
,
936 struct panfrost_shader_state
*ss
,
937 enum pipe_shader_type st
)
939 struct sysval_uniform
*uniforms
= (void *)buf
;
941 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
942 int sysval
= ss
->sysval
[i
];
944 switch (PAN_SYSVAL_TYPE(sysval
)) {
945 case PAN_SYSVAL_VIEWPORT_SCALE
:
946 panfrost_upload_viewport_scale_sysval(batch
,
949 case PAN_SYSVAL_VIEWPORT_OFFSET
:
950 panfrost_upload_viewport_offset_sysval(batch
,
953 case PAN_SYSVAL_TEXTURE_SIZE
:
954 panfrost_upload_txs_sysval(batch
, st
,
955 PAN_SYSVAL_ID(sysval
),
958 case PAN_SYSVAL_SSBO
:
959 panfrost_upload_ssbo_sysval(batch
, st
,
960 PAN_SYSVAL_ID(sysval
),
963 case PAN_SYSVAL_NUM_WORK_GROUPS
:
964 panfrost_upload_num_work_groups_sysval(batch
,
967 case PAN_SYSVAL_SAMPLER
:
968 panfrost_upload_sampler_sysval(batch
, st
,
969 PAN_SYSVAL_ID(sysval
),
979 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
,
982 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
983 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
986 return rsrc
->bo
->cpu
;
987 else if (cb
->user_buffer
)
988 return cb
->user_buffer
;
990 unreachable("No constant buffer");
994 panfrost_emit_const_buf(struct panfrost_batch
*batch
,
995 enum pipe_shader_type stage
,
996 struct mali_vertex_tiler_postfix
*postfix
)
998 struct panfrost_context
*ctx
= batch
->ctx
;
999 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
1004 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[stage
];
1006 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1008 /* Uniforms are implicitly UBO #0 */
1009 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1011 /* Allocate room for the sysval and the uniforms */
1012 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1013 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1014 size_t size
= sys_size
+ uniform_size
;
1015 struct panfrost_transfer transfer
=
1016 panfrost_pool_alloc_aligned(&batch
->pool
, size
, 16);
1018 /* Upload sysvals requested by the shader */
1019 panfrost_upload_sysvals(batch
, transfer
.cpu
, ss
, stage
);
1021 /* Upload uniforms */
1022 if (has_uniforms
&& uniform_size
) {
1023 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1024 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1027 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1028 * uploaded, so it's always included. The count is the highest UBO
1029 * addressable -- gaps are included. */
1031 unsigned ubo_count
= 32 - __builtin_clz(buf
->enabled_mask
| 1);
1033 size_t sz
= MALI_UNIFORM_BUFFER_LENGTH
* ubo_count
;
1034 struct panfrost_transfer ubos
=
1035 panfrost_pool_alloc_aligned(&batch
->pool
, sz
,
1036 MALI_UNIFORM_BUFFER_LENGTH
);
1038 uint64_t *ubo_ptr
= (uint64_t *) ubos
.cpu
;
1040 /* Upload uniforms as a UBO */
1043 pan_pack(ubo_ptr
, UNIFORM_BUFFER
, cfg
) {
1044 cfg
.entries
= DIV_ROUND_UP(size
, 16);
1045 cfg
.pointer
= transfer
.gpu
;
1051 /* The rest are honest-to-goodness UBOs */
1053 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1054 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1055 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1056 bool empty
= usz
== 0;
1058 if (!enabled
|| empty
) {
1063 pan_pack(ubo_ptr
+ ubo
, UNIFORM_BUFFER
, cfg
) {
1064 cfg
.entries
= DIV_ROUND_UP(usz
, 16);
1065 cfg
.pointer
= panfrost_map_constant_buffer_gpu(batch
,
1070 postfix
->uniforms
= transfer
.gpu
;
1071 postfix
->uniform_buffers
= ubos
.gpu
;
1073 buf
->dirty_mask
= 0;
1077 panfrost_emit_shared_memory(struct panfrost_batch
*batch
,
1078 const struct pipe_grid_info
*info
)
1080 struct panfrost_context
*ctx
= batch
->ctx
;
1081 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
1082 struct panfrost_shader_variants
*all
= ctx
->shader
[PIPE_SHADER_COMPUTE
];
1083 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1084 unsigned single_size
= util_next_power_of_two(MAX2(ss
->shared_size
,
1087 unsigned log2_instances
=
1088 util_logbase2_ceil(info
->grid
[0]) +
1089 util_logbase2_ceil(info
->grid
[1]) +
1090 util_logbase2_ceil(info
->grid
[2]);
1092 unsigned shared_size
= single_size
* (1 << log2_instances
) * dev
->core_count
;
1093 struct panfrost_bo
*bo
= panfrost_batch_get_shared_memory(batch
,
1097 struct mali_shared_memory shared
= {
1098 .shared_memory
= bo
->gpu
,
1099 .shared_workgroup_count
= log2_instances
,
1100 .shared_shift
= util_logbase2(single_size
) + 1
1103 return panfrost_pool_upload_aligned(&batch
->pool
, &shared
,
1104 sizeof(shared
), 64);
1108 panfrost_get_tex_desc(struct panfrost_batch
*batch
,
1109 enum pipe_shader_type st
,
1110 struct panfrost_sampler_view
*view
)
1113 return (mali_ptr
) 0;
1115 struct pipe_sampler_view
*pview
= &view
->base
;
1116 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
1118 /* Add the BO to the job so it's retained until the job is done. */
1120 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1121 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1122 panfrost_bo_access_for_stage(st
));
1124 panfrost_batch_add_bo(batch
, view
->bo
,
1125 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1126 panfrost_bo_access_for_stage(st
));
1128 return view
->bo
->gpu
;
1132 panfrost_update_sampler_view(struct panfrost_sampler_view
*view
,
1133 struct pipe_context
*pctx
)
1135 struct panfrost_resource
*rsrc
= pan_resource(view
->base
.texture
);
1136 if (view
->texture_bo
!= rsrc
->bo
->gpu
||
1137 view
->modifier
!= rsrc
->modifier
) {
1138 panfrost_bo_unreference(view
->bo
);
1139 panfrost_create_sampler_view_bo(view
, pctx
, &rsrc
->base
);
1144 panfrost_emit_texture_descriptors(struct panfrost_batch
*batch
,
1145 enum pipe_shader_type stage
)
1147 struct panfrost_context
*ctx
= batch
->ctx
;
1148 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
1150 if (!ctx
->sampler_view_count
[stage
])
1153 if (device
->quirks
& IS_BIFROST
) {
1154 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
,
1155 MALI_BIFROST_TEXTURE_LENGTH
*
1156 ctx
->sampler_view_count
[stage
],
1157 MALI_BIFROST_TEXTURE_LENGTH
);
1159 struct mali_bifrost_texture_packed
*out
=
1160 (struct mali_bifrost_texture_packed
*) T
.cpu
;
1162 for (int i
= 0; i
< ctx
->sampler_view_count
[stage
]; ++i
) {
1163 struct panfrost_sampler_view
*view
= ctx
->sampler_views
[stage
][i
];
1164 struct pipe_sampler_view
*pview
= &view
->base
;
1165 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
1167 panfrost_update_sampler_view(view
, &ctx
->base
);
1168 out
[i
] = view
->bifrost_descriptor
;
1170 /* Add the BOs to the job so they are retained until the job is done. */
1172 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1173 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1174 panfrost_bo_access_for_stage(stage
));
1176 panfrost_batch_add_bo(batch
, view
->bo
,
1177 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
1178 panfrost_bo_access_for_stage(stage
));
1183 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1185 for (int i
= 0; i
< ctx
->sampler_view_count
[stage
]; ++i
) {
1186 struct panfrost_sampler_view
*view
= ctx
->sampler_views
[stage
][i
];
1188 panfrost_update_sampler_view(view
, &ctx
->base
);
1190 trampolines
[i
] = panfrost_get_tex_desc(batch
, stage
, view
);
1193 return panfrost_pool_upload_aligned(&batch
->pool
, trampolines
,
1195 ctx
->sampler_view_count
[stage
],
1201 panfrost_emit_sampler_descriptors(struct panfrost_batch
*batch
,
1202 enum pipe_shader_type stage
)
1204 struct panfrost_context
*ctx
= batch
->ctx
;
1206 if (!ctx
->sampler_count
[stage
])
1209 size_t desc_size
= MALI_BIFROST_SAMPLER_LENGTH
;
1210 assert(MALI_BIFROST_SAMPLER_LENGTH
== MALI_MIDGARD_SAMPLER_LENGTH
);
1212 size_t sz
= desc_size
* ctx
->sampler_count
[stage
];
1213 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
, sz
, desc_size
);
1214 struct mali_midgard_sampler_packed
*out
= (struct mali_midgard_sampler_packed
*) T
.cpu
;
1216 for (unsigned i
= 0; i
< ctx
->sampler_count
[stage
]; ++i
)
1217 out
[i
] = ctx
->samplers
[stage
][i
]->hw
;
1223 panfrost_emit_vertex_data(struct panfrost_batch
*batch
,
1224 struct mali_vertex_tiler_postfix
*vertex_postfix
)
1226 struct panfrost_context
*ctx
= batch
->ctx
;
1227 struct panfrost_vertex_state
*so
= ctx
->vertex
;
1228 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
1230 unsigned instance_shift
= vertex_postfix
->instance_shift
;
1231 unsigned instance_odd
= vertex_postfix
->instance_odd
;
1233 /* Worst case: everything is NPOT, which is only possible if instancing
1234 * is enabled. Otherwise single record is gauranteed */
1235 bool could_npot
= instance_shift
|| instance_odd
;
1237 struct panfrost_transfer S
= panfrost_pool_alloc_aligned(&batch
->pool
,
1238 MALI_ATTRIBUTE_BUFFER_LENGTH
* vs
->attribute_count
*
1239 (could_npot
? 2 : 1),
1240 MALI_ATTRIBUTE_BUFFER_LENGTH
* 2);
1242 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
,
1243 MALI_ATTRIBUTE_LENGTH
* vs
->attribute_count
,
1244 MALI_ATTRIBUTE_LENGTH
);
1246 struct mali_attribute_buffer_packed
*bufs
=
1247 (struct mali_attribute_buffer_packed
*) S
.cpu
;
1249 struct mali_attribute_packed
*out
=
1250 (struct mali_attribute_packed
*) T
.cpu
;
1252 unsigned attrib_to_buffer
[PIPE_MAX_ATTRIBS
] = { 0 };
1255 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
1256 /* We map buffers 1:1 with the attributes, which
1257 * means duplicating some vertex buffers (who cares? aside from
1258 * maybe some caching implications but I somehow doubt that
1261 struct pipe_vertex_element
*elem
= &so
->pipe
[i
];
1262 unsigned vbi
= elem
->vertex_buffer_index
;
1263 attrib_to_buffer
[i
] = k
;
1265 if (!(ctx
->vb_mask
& (1 << vbi
)))
1268 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
1269 struct panfrost_resource
*rsrc
;
1271 rsrc
= pan_resource(buf
->buffer
.resource
);
1275 /* Add a dependency of the batch on the vertex buffer */
1276 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1277 PAN_BO_ACCESS_SHARED
|
1278 PAN_BO_ACCESS_READ
|
1279 PAN_BO_ACCESS_VERTEX_TILER
);
1281 /* Mask off lower bits, see offset fixup below */
1282 mali_ptr raw_addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
1283 mali_ptr addr
= raw_addr
& ~63;
1285 /* Since we advanced the base pointer, we shrink the buffer
1286 * size, but add the offset we subtracted */
1287 unsigned size
= rsrc
->base
.width0
+ (raw_addr
- addr
)
1288 - buf
->buffer_offset
;
1290 /* When there is a divisor, the hardware-level divisor is
1291 * the product of the instance divisor and the padded count */
1292 unsigned divisor
= elem
->instance_divisor
;
1293 unsigned hw_divisor
= ctx
->padded_count
* divisor
;
1294 unsigned stride
= buf
->stride
;
1296 /* If there's a divisor(=1) but no instancing, we want every
1297 * attribute to be the same */
1299 if (divisor
&& ctx
->instance_count
== 1)
1302 if (!divisor
|| ctx
->instance_count
<= 1) {
1303 pan_pack(bufs
+ k
, ATTRIBUTE_BUFFER
, cfg
) {
1304 if (ctx
->instance_count
> 1)
1305 cfg
.type
= MALI_ATTRIBUTE_TYPE_1D_MODULUS
;
1308 cfg
.stride
= stride
;
1310 cfg
.divisor_r
= instance_shift
;
1311 cfg
.divisor_p
= instance_odd
;
1313 } else if (util_is_power_of_two_or_zero(hw_divisor
)) {
1314 pan_pack(bufs
+ k
, ATTRIBUTE_BUFFER
, cfg
) {
1315 cfg
.type
= MALI_ATTRIBUTE_TYPE_1D_POT_DIVISOR
;
1317 cfg
.stride
= stride
;
1319 cfg
.divisor_r
= __builtin_ctz(hw_divisor
);
1323 unsigned shift
= 0, extra_flags
= 0;
1325 unsigned magic_divisor
=
1326 panfrost_compute_magic_divisor(hw_divisor
, &shift
, &extra_flags
);
1328 pan_pack(bufs
+ k
, ATTRIBUTE_BUFFER
, cfg
) {
1329 cfg
.type
= MALI_ATTRIBUTE_TYPE_1D_NPOT_DIVISOR
;
1331 cfg
.stride
= stride
;
1334 cfg
.divisor_r
= shift
;
1335 cfg
.divisor_e
= extra_flags
;
1338 pan_pack(bufs
+ k
+ 1, ATTRIBUTE_BUFFER_CONTINUATION_NPOT
, cfg
) {
1339 cfg
.divisor_numerator
= magic_divisor
;
1340 cfg
.divisor
= divisor
;
1349 /* Add special gl_VertexID/gl_InstanceID buffers */
1351 if (unlikely(vs
->attribute_count
>= PAN_VERTEX_ID
)) {
1352 panfrost_vertex_id(ctx
->padded_count
, &bufs
[k
], ctx
->instance_count
> 1);
1354 pan_pack(out
+ PAN_VERTEX_ID
, ATTRIBUTE
, cfg
) {
1355 cfg
.buffer_index
= k
++;
1356 cfg
.format
= so
->formats
[PAN_VERTEX_ID
];
1359 panfrost_instance_id(ctx
->padded_count
, &bufs
[k
], ctx
->instance_count
> 1);
1361 pan_pack(out
+ PAN_INSTANCE_ID
, ATTRIBUTE
, cfg
) {
1362 cfg
.buffer_index
= k
++;
1363 cfg
.format
= so
->formats
[PAN_INSTANCE_ID
];
1367 /* Attribute addresses require 64-byte alignment, so let:
1369 * base' = base & ~63 = base - (base & 63)
1370 * offset' = offset + (base & 63)
1372 * Since base' + offset' = base + offset, these are equivalent
1373 * addressing modes and now base is 64 aligned.
1376 unsigned start
= vertex_postfix
->offset_start
;
1378 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
1379 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
1380 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
1382 /* Adjust by the masked off bits of the offset. Make sure we
1383 * read src_offset from so->hw (which is not GPU visible)
1384 * rather than target (which is) due to caching effects */
1386 unsigned src_offset
= so
->pipe
[i
].src_offset
;
1388 /* BOs aligned to 4k so guaranteed aligned to 64 */
1389 src_offset
+= (buf
->buffer_offset
& 63);
1391 /* Also, somewhat obscurely per-instance data needs to be
1392 * offset in response to a delayed start in an indexed draw */
1394 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
1395 src_offset
-= buf
->stride
* start
;
1397 pan_pack(out
+ i
, ATTRIBUTE
, cfg
) {
1398 cfg
.buffer_index
= attrib_to_buffer
[i
];
1399 cfg
.format
= so
->formats
[i
];
1400 cfg
.offset
= src_offset
;
1404 vertex_postfix
->attributes
= S
.gpu
;
1405 vertex_postfix
->attribute_meta
= T
.gpu
;
1409 panfrost_emit_varyings(struct panfrost_batch
*batch
,
1410 struct mali_attribute_buffer_packed
*slot
,
1411 unsigned stride
, unsigned count
)
1413 unsigned size
= stride
* count
;
1414 mali_ptr ptr
= panfrost_pool_alloc_aligned(&batch
->invisible_pool
, size
, 64).gpu
;
1416 pan_pack(slot
, ATTRIBUTE_BUFFER
, cfg
) {
1417 cfg
.stride
= stride
;
1426 panfrost_streamout_offset(unsigned stride
, unsigned offset
,
1427 struct pipe_stream_output_target
*target
)
1429 return (target
->buffer_offset
+ (offset
* stride
* 4)) & 63;
1433 panfrost_emit_streamout(struct panfrost_batch
*batch
,
1434 struct mali_attribute_buffer_packed
*slot
,
1435 unsigned stride_words
, unsigned offset
, unsigned count
,
1436 struct pipe_stream_output_target
*target
)
1438 unsigned stride
= stride_words
* 4;
1439 unsigned max_size
= target
->buffer_size
;
1440 unsigned expected_size
= stride
* count
;
1442 /* Grab the BO and bind it to the batch */
1443 struct panfrost_bo
*bo
= pan_resource(target
->buffer
)->bo
;
1445 /* Varyings are WRITE from the perspective of the VERTEX but READ from
1446 * the perspective of the TILER and FRAGMENT.
1448 panfrost_batch_add_bo(batch
, bo
,
1449 PAN_BO_ACCESS_SHARED
|
1451 PAN_BO_ACCESS_VERTEX_TILER
|
1452 PAN_BO_ACCESS_FRAGMENT
);
1454 /* We will have an offset applied to get alignment */
1455 mali_ptr addr
= bo
->gpu
+ target
->buffer_offset
+ (offset
* stride
);
1457 pan_pack(slot
, ATTRIBUTE_BUFFER
, cfg
) {
1458 cfg
.pointer
= (addr
& ~63);
1459 cfg
.stride
= stride
;
1460 cfg
.size
= MIN2(max_size
, expected_size
) + (addr
& 63);
1465 has_point_coord(unsigned mask
, gl_varying_slot loc
)
1467 if ((loc
>= VARYING_SLOT_TEX0
) && (loc
<= VARYING_SLOT_TEX7
))
1468 return (mask
& (1 << (loc
- VARYING_SLOT_TEX0
)));
1469 else if (loc
== VARYING_SLOT_PNTC
)
1470 return (mask
& (1 << 8));
1475 /* Helpers for manipulating stream out information so we can pack varyings
1476 * accordingly. Compute the src_offset for a given captured varying */
1478 static struct pipe_stream_output
*
1479 pan_get_so(struct pipe_stream_output_info
*info
, gl_varying_slot loc
)
1481 for (unsigned i
= 0; i
< info
->num_outputs
; ++i
) {
1482 if (info
->output
[i
].register_index
== loc
)
1483 return &info
->output
[i
];
1486 unreachable("Varying not captured");
1490 pan_varying_size(enum mali_format fmt
)
1492 unsigned type
= MALI_EXTRACT_TYPE(fmt
);
1493 unsigned chan
= MALI_EXTRACT_CHANNELS(fmt
);
1494 unsigned bits
= MALI_EXTRACT_BITS(fmt
);
1497 if (bits
== MALI_CHANNEL_FLOAT
) {
1499 bool fp16
= (type
== MALI_FORMAT_SINT
);
1500 assert(fp16
|| (type
== MALI_FORMAT_UNORM
));
1504 assert(type
>= MALI_FORMAT_SNORM
&& type
<= MALI_FORMAT_SINT
);
1515 /* Indices for named (non-XFB) varyings that are present. These are packed
1516 * tightly so they correspond to a bitfield present (P) indexed by (1 <<
1517 * PAN_VARY_*). This has the nice property that you can lookup the buffer index
1518 * of a given special field given a shift S by:
1520 * idx = popcount(P & ((1 << S) - 1))
1522 * That is... look at all of the varyings that come earlier and count them, the
1523 * count is the new index since plus one. Likewise, the total number of special
1524 * buffers required is simply popcount(P)
1527 enum pan_special_varying
{
1528 PAN_VARY_GENERAL
= 0,
1529 PAN_VARY_POSITION
= 1,
1531 PAN_VARY_PNTCOORD
= 3,
1533 PAN_VARY_FRAGCOORD
= 5,
1539 /* Given a varying, figure out which index it correpsonds to */
1541 static inline unsigned
1542 pan_varying_index(unsigned present
, enum pan_special_varying v
)
1544 unsigned mask
= (1 << v
) - 1;
1545 return util_bitcount(present
& mask
);
1548 /* Get the base offset for XFB buffers, which by convention come after
1549 * everything else. Wrapper function for semantic reasons; by construction this
1550 * is just popcount. */
1552 static inline unsigned
1553 pan_xfb_base(unsigned present
)
1555 return util_bitcount(present
);
1558 /* Computes the present mask for varyings so we can start emitting varying records */
1560 static inline unsigned
1561 pan_varying_present(
1562 struct panfrost_shader_state
*vs
,
1563 struct panfrost_shader_state
*fs
,
1566 /* At the moment we always emit general and position buffers. Not
1567 * strictly necessary but usually harmless */
1569 unsigned present
= (1 << PAN_VARY_GENERAL
) | (1 << PAN_VARY_POSITION
);
1571 /* Enable special buffers by the shader info */
1573 if (vs
->writes_point_size
)
1574 present
|= (1 << PAN_VARY_PSIZ
);
1576 if (fs
->reads_point_coord
)
1577 present
|= (1 << PAN_VARY_PNTCOORD
);
1580 present
|= (1 << PAN_VARY_FACE
);
1582 if (fs
->reads_frag_coord
&& !(quirks
& IS_BIFROST
))
1583 present
|= (1 << PAN_VARY_FRAGCOORD
);
1585 /* Also, if we have a point sprite, we need a point coord buffer */
1587 for (unsigned i
= 0; i
< fs
->varying_count
; i
++) {
1588 gl_varying_slot loc
= fs
->varyings_loc
[i
];
1590 if (has_point_coord(fs
->point_sprite_mask
, loc
))
1591 present
|= (1 << PAN_VARY_PNTCOORD
);
1597 /* Emitters for varying records */
1600 pan_emit_vary(struct mali_attribute_packed
*out
,
1601 unsigned present
, enum pan_special_varying buf
,
1602 unsigned quirks
, enum mali_format format
,
1605 unsigned nr_channels
= MALI_EXTRACT_CHANNELS(format
);
1606 unsigned swizzle
= quirks
& HAS_SWIZZLES
?
1607 panfrost_get_default_swizzle(nr_channels
) :
1608 panfrost_bifrost_swizzle(nr_channels
);
1610 pan_pack(out
, ATTRIBUTE
, cfg
) {
1611 cfg
.buffer_index
= pan_varying_index(present
, buf
);
1612 cfg
.unknown
= quirks
& IS_BIFROST
? 0x0 : 0x1;
1613 cfg
.format
= (format
<< 12) | swizzle
;
1614 cfg
.offset
= offset
;
1618 /* General varying that is unused */
1621 pan_emit_vary_only(struct mali_attribute_packed
*out
,
1622 unsigned present
, unsigned quirks
)
1624 pan_emit_vary(out
, present
, 0, quirks
, MALI_VARYING_DISCARD
, 0);
1627 /* Special records */
1629 static const enum mali_format pan_varying_formats
[PAN_VARY_MAX
] = {
1630 [PAN_VARY_POSITION
] = MALI_VARYING_POS
,
1631 [PAN_VARY_PSIZ
] = MALI_R16F
,
1632 [PAN_VARY_PNTCOORD
] = MALI_R16F
,
1633 [PAN_VARY_FACE
] = MALI_R32I
,
1634 [PAN_VARY_FRAGCOORD
] = MALI_RGBA32F
1638 pan_emit_vary_special(struct mali_attribute_packed
*out
,
1639 unsigned present
, enum pan_special_varying buf
,
1642 assert(buf
< PAN_VARY_MAX
);
1643 pan_emit_vary(out
, present
, buf
, quirks
, pan_varying_formats
[buf
], 0);
1646 static enum mali_format
1647 pan_xfb_format(enum mali_format format
, unsigned nr
)
1649 if (MALI_EXTRACT_BITS(format
) == MALI_CHANNEL_FLOAT
)
1650 return MALI_R32F
| MALI_NR_CHANNELS(nr
);
1652 return MALI_EXTRACT_TYPE(format
) | MALI_NR_CHANNELS(nr
) | MALI_CHANNEL_32
;
1655 /* Transform feedback records. Note struct pipe_stream_output is (if packed as
1656 * a bitfield) 32-bit, smaller than a 64-bit pointer, so may as well pass by
1660 pan_emit_vary_xfb(struct mali_attribute_packed
*out
,
1663 unsigned *streamout_offsets
,
1665 enum mali_format format
,
1666 struct pipe_stream_output o
)
1668 unsigned swizzle
= quirks
& HAS_SWIZZLES
?
1669 panfrost_get_default_swizzle(o
.num_components
) :
1670 panfrost_bifrost_swizzle(o
.num_components
);
1672 pan_pack(out
, ATTRIBUTE
, cfg
) {
1673 /* XFB buffers come after everything else */
1674 cfg
.buffer_index
= pan_xfb_base(present
) + o
.output_buffer
;
1675 cfg
.unknown
= quirks
& IS_BIFROST
? 0x0 : 0x1;
1677 /* Override number of channels and precision to highp */
1678 cfg
.format
= (pan_xfb_format(format
, o
.num_components
) << 12) | swizzle
;
1680 /* Apply given offsets together */
1681 cfg
.offset
= (o
.dst_offset
* 4) /* dwords */
1682 + streamout_offsets
[o
.output_buffer
];
1686 /* Determine if we should capture a varying for XFB. This requires actually
1687 * having a buffer for it. If we don't capture it, we'll fallback to a general
1688 * varying path (linked or unlinked, possibly discarding the write) */
1691 panfrost_xfb_captured(struct panfrost_shader_state
*xfb
,
1692 unsigned loc
, unsigned max_xfb
)
1694 if (!(xfb
->so_mask
& (1ll << loc
)))
1697 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1698 return o
->output_buffer
< max_xfb
;
1702 pan_emit_general_varying(struct mali_attribute_packed
*out
,
1703 struct panfrost_shader_state
*other
,
1704 struct panfrost_shader_state
*xfb
,
1705 gl_varying_slot loc
,
1706 enum mali_format format
,
1709 unsigned *gen_offsets
,
1710 enum mali_format
*gen_formats
,
1711 unsigned *gen_stride
,
1715 /* Check if we're linked */
1716 signed other_idx
= -1;
1718 for (unsigned j
= 0; j
< other
->varying_count
; ++j
) {
1719 if (other
->varyings_loc
[j
] == loc
) {
1725 if (other_idx
< 0) {
1726 pan_emit_vary_only(out
, present
, quirks
);
1730 unsigned offset
= gen_offsets
[other_idx
];
1733 /* We're linked, so allocate a space via a watermark allocation */
1734 enum mali_format alt
= other
->varyings
[other_idx
];
1736 /* Do interpolation at minimum precision */
1737 unsigned size_main
= pan_varying_size(format
);
1738 unsigned size_alt
= pan_varying_size(alt
);
1739 unsigned size
= MIN2(size_main
, size_alt
);
1741 /* If a varying is marked for XFB but not actually captured, we
1742 * should match the format to the format that would otherwise
1743 * be used for XFB, since dEQP checks for invariance here. It's
1744 * unclear if this is required by the spec. */
1746 if (xfb
->so_mask
& (1ull << loc
)) {
1747 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1748 format
= pan_xfb_format(format
, o
->num_components
);
1749 size
= pan_varying_size(format
);
1750 } else if (size
== size_alt
) {
1754 gen_offsets
[idx
] = *gen_stride
;
1755 gen_formats
[other_idx
] = format
;
1756 offset
= *gen_stride
;
1757 *gen_stride
+= size
;
1760 pan_emit_vary(out
, present
, PAN_VARY_GENERAL
, quirks
, format
, offset
);
1763 /* Higher-level wrapper around all of the above, classifying a varying into one
1764 * of the above types */
1767 panfrost_emit_varying(
1768 struct mali_attribute_packed
*out
,
1769 struct panfrost_shader_state
*stage
,
1770 struct panfrost_shader_state
*other
,
1771 struct panfrost_shader_state
*xfb
,
1774 unsigned *streamout_offsets
,
1776 unsigned *gen_offsets
,
1777 enum mali_format
*gen_formats
,
1778 unsigned *gen_stride
,
1783 gl_varying_slot loc
= stage
->varyings_loc
[idx
];
1784 enum mali_format format
= stage
->varyings
[idx
];
1786 /* Override format to match linkage */
1787 if (!should_alloc
&& gen_formats
[idx
])
1788 format
= gen_formats
[idx
];
1790 if (has_point_coord(stage
->point_sprite_mask
, loc
)) {
1791 pan_emit_vary_special(out
, present
, PAN_VARY_PNTCOORD
, quirks
);
1792 } else if (panfrost_xfb_captured(xfb
, loc
, max_xfb
)) {
1793 struct pipe_stream_output
*o
= pan_get_so(&xfb
->stream_output
, loc
);
1794 pan_emit_vary_xfb(out
, present
, max_xfb
, streamout_offsets
, quirks
, format
, *o
);
1795 } else if (loc
== VARYING_SLOT_POS
) {
1797 pan_emit_vary_special(out
, present
, PAN_VARY_FRAGCOORD
, quirks
);
1799 pan_emit_vary_special(out
, present
, PAN_VARY_POSITION
, quirks
);
1800 } else if (loc
== VARYING_SLOT_PSIZ
) {
1801 pan_emit_vary_special(out
, present
, PAN_VARY_PSIZ
, quirks
);
1802 } else if (loc
== VARYING_SLOT_PNTC
) {
1803 pan_emit_vary_special(out
, present
, PAN_VARY_PNTCOORD
, quirks
);
1804 } else if (loc
== VARYING_SLOT_FACE
) {
1805 pan_emit_vary_special(out
, present
, PAN_VARY_FACE
, quirks
);
1807 pan_emit_general_varying(out
, other
, xfb
, loc
, format
, present
,
1808 quirks
, gen_offsets
, gen_formats
, gen_stride
,
1814 pan_emit_special_input(struct mali_attribute_buffer_packed
*out
,
1816 enum pan_special_varying v
,
1819 if (present
& (1 << v
)) {
1820 unsigned idx
= pan_varying_index(present
, v
);
1822 pan_pack(out
+ idx
, ATTRIBUTE_BUFFER
, cfg
) {
1823 cfg
.special
= special
;
1830 panfrost_emit_varying_descriptor(struct panfrost_batch
*batch
,
1831 unsigned vertex_count
,
1832 struct mali_vertex_tiler_postfix
*vertex_postfix
,
1833 struct mali_vertex_tiler_postfix
*tiler_postfix
,
1834 union midgard_primitive_size
*primitive_size
)
1836 /* Load the shaders */
1837 struct panfrost_context
*ctx
= batch
->ctx
;
1838 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
1839 struct panfrost_shader_state
*vs
, *fs
;
1840 size_t vs_size
, fs_size
;
1842 /* Allocate the varying descriptor */
1844 vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
1845 fs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
1846 vs_size
= MALI_ATTRIBUTE_LENGTH
* vs
->varying_count
;
1847 fs_size
= MALI_ATTRIBUTE_LENGTH
* fs
->varying_count
;
1849 struct panfrost_transfer trans
= panfrost_pool_alloc_aligned(
1850 &batch
->pool
, vs_size
+ fs_size
, MALI_ATTRIBUTE_LENGTH
);
1852 struct pipe_stream_output_info
*so
= &vs
->stream_output
;
1853 unsigned present
= pan_varying_present(vs
, fs
, dev
->quirks
);
1855 /* Check if this varying is linked by us. This is the case for
1856 * general-purpose, non-captured varyings. If it is, link it. If it's
1857 * not, use the provided stream out information to determine the
1858 * offset, since it was already linked for us. */
1860 unsigned gen_offsets
[32];
1861 enum mali_format gen_formats
[32];
1862 memset(gen_offsets
, 0, sizeof(gen_offsets
));
1863 memset(gen_formats
, 0, sizeof(gen_formats
));
1865 unsigned gen_stride
= 0;
1866 assert(vs
->varying_count
< ARRAY_SIZE(gen_offsets
));
1867 assert(fs
->varying_count
< ARRAY_SIZE(gen_offsets
));
1869 unsigned streamout_offsets
[32];
1871 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1872 streamout_offsets
[i
] = panfrost_streamout_offset(
1874 ctx
->streamout
.offsets
[i
],
1875 ctx
->streamout
.targets
[i
]);
1878 struct mali_attribute_packed
*ovs
= (struct mali_attribute_packed
*)trans
.cpu
;
1879 struct mali_attribute_packed
*ofs
= ovs
+ vs
->varying_count
;
1881 for (unsigned i
= 0; i
< vs
->varying_count
; i
++) {
1882 panfrost_emit_varying(ovs
+ i
, vs
, fs
, vs
, present
,
1883 ctx
->streamout
.num_targets
, streamout_offsets
,
1885 gen_offsets
, gen_formats
, &gen_stride
, i
, true, false);
1888 for (unsigned i
= 0; i
< fs
->varying_count
; i
++) {
1889 panfrost_emit_varying(ofs
+ i
, fs
, vs
, vs
, present
,
1890 ctx
->streamout
.num_targets
, streamout_offsets
,
1892 gen_offsets
, gen_formats
, &gen_stride
, i
, false, true);
1895 unsigned xfb_base
= pan_xfb_base(present
);
1896 struct panfrost_transfer T
= panfrost_pool_alloc_aligned(&batch
->pool
,
1897 MALI_ATTRIBUTE_BUFFER_LENGTH
* (xfb_base
+ ctx
->streamout
.num_targets
),
1898 MALI_ATTRIBUTE_BUFFER_LENGTH
* 2);
1899 struct mali_attribute_buffer_packed
*varyings
=
1900 (struct mali_attribute_buffer_packed
*) T
.cpu
;
1902 /* Emit the stream out buffers */
1904 unsigned out_count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
1907 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1908 panfrost_emit_streamout(batch
, &varyings
[xfb_base
+ i
],
1910 ctx
->streamout
.offsets
[i
],
1912 ctx
->streamout
.targets
[i
]);
1915 panfrost_emit_varyings(batch
,
1916 &varyings
[pan_varying_index(present
, PAN_VARY_GENERAL
)],
1917 gen_stride
, vertex_count
);
1919 /* fp32 vec4 gl_Position */
1920 tiler_postfix
->position_varying
= panfrost_emit_varyings(batch
,
1921 &varyings
[pan_varying_index(present
, PAN_VARY_POSITION
)],
1922 sizeof(float) * 4, vertex_count
);
1924 if (present
& (1 << PAN_VARY_PSIZ
)) {
1925 primitive_size
->pointer
= panfrost_emit_varyings(batch
,
1926 &varyings
[pan_varying_index(present
, PAN_VARY_PSIZ
)],
1930 pan_emit_special_input(varyings
, present
, PAN_VARY_PNTCOORD
, MALI_ATTRIBUTE_SPECIAL_POINT_COORD
);
1931 pan_emit_special_input(varyings
, present
, PAN_VARY_FACE
, MALI_ATTRIBUTE_SPECIAL_FRONT_FACING
);
1932 pan_emit_special_input(varyings
, present
, PAN_VARY_FRAGCOORD
, MALI_ATTRIBUTE_SPECIAL_FRAG_COORD
);
1934 vertex_postfix
->varyings
= T
.gpu
;
1935 tiler_postfix
->varyings
= T
.gpu
;
1937 vertex_postfix
->varying_meta
= trans
.gpu
;
1938 tiler_postfix
->varying_meta
= trans
.gpu
+ vs_size
;
1942 panfrost_emit_vertex_tiler_jobs(struct panfrost_batch
*batch
,
1943 struct mali_vertex_tiler_prefix
*vertex_prefix
,
1944 struct mali_vertex_tiler_postfix
*vertex_postfix
,
1945 struct mali_vertex_tiler_prefix
*tiler_prefix
,
1946 struct mali_vertex_tiler_postfix
*tiler_postfix
,
1947 union midgard_primitive_size
*primitive_size
)
1949 struct panfrost_context
*ctx
= batch
->ctx
;
1950 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
1951 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->scoreboard
.tiler_dep
;
1952 struct bifrost_payload_vertex bifrost_vertex
= {0,};
1953 struct bifrost_payload_tiler bifrost_tiler
= {0,};
1954 struct midgard_payload_vertex_tiler midgard_vertex
= {0,};
1955 struct midgard_payload_vertex_tiler midgard_tiler
= {0,};
1957 size_t vp_size
, tp_size
;
1959 if (device
->quirks
& IS_BIFROST
) {
1960 bifrost_vertex
.prefix
= *vertex_prefix
;
1961 bifrost_vertex
.postfix
= *vertex_postfix
;
1962 vp
= &bifrost_vertex
;
1963 vp_size
= sizeof(bifrost_vertex
);
1965 bifrost_tiler
.prefix
= *tiler_prefix
;
1966 bifrost_tiler
.tiler
.primitive_size
= *primitive_size
;
1967 bifrost_tiler
.tiler
.tiler_meta
= panfrost_batch_get_tiler_meta(batch
, ~0);
1968 bifrost_tiler
.postfix
= *tiler_postfix
;
1969 tp
= &bifrost_tiler
;
1970 tp_size
= sizeof(bifrost_tiler
);
1972 midgard_vertex
.prefix
= *vertex_prefix
;
1973 midgard_vertex
.postfix
= *vertex_postfix
;
1974 vp
= &midgard_vertex
;
1975 vp_size
= sizeof(midgard_vertex
);
1977 midgard_tiler
.prefix
= *tiler_prefix
;
1978 midgard_tiler
.postfix
= *tiler_postfix
;
1979 midgard_tiler
.primitive_size
= *primitive_size
;
1980 tp
= &midgard_tiler
;
1981 tp_size
= sizeof(midgard_tiler
);
1985 /* Inject in reverse order, with "predicted" job indices.
1986 * THIS IS A HACK XXX */
1987 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_TILER
, false,
1988 batch
->scoreboard
.job_index
+ 2, tp
, tp_size
, true);
1989 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_VERTEX
, false, 0,
1994 /* If rasterizer discard is enable, only submit the vertex */
1996 unsigned vertex
= panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_VERTEX
, false, 0,
1997 vp
, vp_size
, false);
1999 if (ctx
->rasterizer
->base
.rasterizer_discard
)
2002 panfrost_new_job(&batch
->pool
, &batch
->scoreboard
, MALI_JOB_TYPE_TILER
, false, vertex
, tp
, tp_size
,
2006 /* TODO: stop hardcoding this */
2008 panfrost_emit_sample_locations(struct panfrost_batch
*batch
)
2010 uint16_t locations
[] = {
2061 return panfrost_pool_upload_aligned(&batch
->pool
, locations
, 96 * sizeof(uint16_t), 64);