panfrost: Move attr_meta emission to the draw routine
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27 #include <sys/poll.h>
28 #include <errno.h>
29
30 #include "pan_bo.h"
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
34
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
50
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
55 #include "pan_util.h"
56 #include "decode.h"
57 #include "util/pan_lower_framebuffer.h"
58
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
61 {
62 struct panfrost_device *device = pan_device(batch->ctx->base.screen);
63 bool hierarchy = !(device->quirks & MIDGARD_NO_HIER_TILING);
64 struct midgard_tiler_descriptor t = {0};
65 unsigned height = batch->key.height;
66 unsigned width = batch->key.width;
67
68 t.hierarchy_mask =
69 panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
70
71 /* Compute the polygon header size and use that to offset the body */
72
73 unsigned header_size = panfrost_tiler_header_size(
74 width, height, t.hierarchy_mask, hierarchy);
75
76 t.polygon_list_size = panfrost_tiler_full_size(
77 width, height, t.hierarchy_mask, hierarchy);
78
79 /* Sanity check */
80
81 if (vertex_count) {
82 struct panfrost_bo *tiler_heap;
83
84 tiler_heap = panfrost_batch_get_tiler_heap(batch);
85 t.polygon_list = panfrost_batch_get_polygon_list(batch,
86 header_size +
87 t.polygon_list_size);
88
89
90 /* Allow the entire tiler heap */
91 t.heap_start = tiler_heap->gpu;
92 t.heap_end = tiler_heap->gpu + tiler_heap->size;
93 } else {
94 struct panfrost_bo *tiler_dummy;
95
96 tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
97 header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
98
99 /* The tiler is disabled, so don't allow the tiler heap */
100 t.heap_start = tiler_dummy->gpu;
101 t.heap_end = t.heap_start;
102
103 /* Use a dummy polygon list */
104 t.polygon_list = tiler_dummy->gpu;
105
106 /* Disable the tiler */
107 if (hierarchy)
108 t.hierarchy_mask |= MALI_TILER_DISABLED;
109 else {
110 t.hierarchy_mask = MALI_TILER_USER;
111 t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
112
113 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
114 uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
115 polygon_list_body[0] = 0xa0000000; /* TODO: Just that? */
116 }
117 }
118
119 t.polygon_list_body =
120 t.polygon_list + header_size;
121
122 return t;
123 }
124
125 static void
126 panfrost_clear(
127 struct pipe_context *pipe,
128 unsigned buffers,
129 const struct pipe_scissor_state *scissor_state,
130 const union pipe_color_union *color,
131 double depth, unsigned stencil)
132 {
133 struct panfrost_context *ctx = pan_context(pipe);
134
135 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
136 * the existing batch targeting this FBO has draws. We could probably
137 * avoid that by replacing plain clears by quad-draws with a specific
138 * color/depth/stencil value, thus avoiding the generation of extra
139 * fragment jobs.
140 */
141 struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx);
142
143 panfrost_batch_add_fbo_bos(batch);
144 panfrost_batch_clear(batch, buffers, color, depth, stencil);
145 }
146
147 /* Reset per-frame context, called on context initialisation as well as after
148 * flushing a frame */
149
150 void
151 panfrost_invalidate_frame(struct panfrost_context *ctx)
152 {
153 /* TODO: When does this need to be handled? */
154 ctx->active_queries = true;
155 }
156
157 bool
158 panfrost_writes_point_size(struct panfrost_context *ctx)
159 {
160 assert(ctx->shader[PIPE_SHADER_VERTEX]);
161 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
162
163 return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
164 }
165
166 /* Compute number of UBOs active (more specifically, compute the highest UBO
167 * number addressable -- if there are gaps, include them in the count anyway).
168 * We always include UBO #0 in the count, since we *need* uniforms enabled for
169 * sysvals. */
170
171 unsigned
172 panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
173 {
174 unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
175 return 32 - __builtin_clz(mask);
176 }
177
178 /* The entire frame is in memory -- send it off to the kernel! */
179
180 void
181 panfrost_flush(
182 struct pipe_context *pipe,
183 struct pipe_fence_handle **fence,
184 unsigned flags)
185 {
186 struct panfrost_context *ctx = pan_context(pipe);
187 struct panfrost_device *dev = pan_device(pipe->screen);
188 uint32_t syncobj = 0;
189
190 if (fence)
191 drmSyncobjCreate(dev->fd, 0, &syncobj);
192
193 /* Submit all pending jobs */
194 panfrost_flush_all_batches(ctx, syncobj);
195
196 if (fence) {
197 struct panfrost_fence *f = panfrost_fence_create(ctx, syncobj);
198 pipe->screen->fence_reference(pipe->screen, fence, NULL);
199 *fence = (struct pipe_fence_handle *)f;
200 }
201
202 if (dev->debug & PAN_DBG_TRACE)
203 pandecode_next_frame();
204 }
205
206 static void
207 panfrost_texture_barrier(struct pipe_context *pipe, unsigned flags)
208 {
209 struct panfrost_context *ctx = pan_context(pipe);
210 panfrost_flush_all_batches(ctx, 0);
211 }
212
213 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
214
215 static int
216 g2m_draw_mode(enum pipe_prim_type mode)
217 {
218 switch (mode) {
219 DEFINE_CASE(POINTS);
220 DEFINE_CASE(LINES);
221 DEFINE_CASE(LINE_LOOP);
222 DEFINE_CASE(LINE_STRIP);
223 DEFINE_CASE(TRIANGLES);
224 DEFINE_CASE(TRIANGLE_STRIP);
225 DEFINE_CASE(TRIANGLE_FAN);
226 DEFINE_CASE(QUADS);
227 DEFINE_CASE(QUAD_STRIP);
228 DEFINE_CASE(POLYGON);
229
230 default:
231 unreachable("Invalid draw mode");
232 }
233 }
234
235 #undef DEFINE_CASE
236
237 static bool
238 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
239 {
240 const struct pipe_scissor_state *ss = &ctx->scissor;
241
242 /* Check if we're scissoring at all */
243
244 if (!(ctx->rasterizer && ctx->rasterizer->base.scissor))
245 return false;
246
247 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
248 }
249
250 /* Count generated primitives (when there is no geom/tess shaders) for
251 * transform feedback */
252
253 static void
254 panfrost_statistics_record(
255 struct panfrost_context *ctx,
256 const struct pipe_draw_info *info)
257 {
258 if (!ctx->active_queries)
259 return;
260
261 uint32_t prims = u_prims_for_vertices(info->mode, info->count);
262 ctx->prims_generated += prims;
263
264 if (!ctx->streamout.num_targets)
265 return;
266
267 ctx->tf_prims_generated += prims;
268 }
269
270 static void
271 panfrost_update_streamout_offsets(struct panfrost_context *ctx)
272 {
273 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
274 unsigned count;
275
276 count = u_stream_outputs_for_vertices(ctx->active_prim,
277 ctx->vertex_count);
278 ctx->streamout.offsets[i] += count;
279 }
280 }
281
282 static void
283 panfrost_draw_vbo(
284 struct pipe_context *pipe,
285 const struct pipe_draw_info *info)
286 {
287 struct panfrost_context *ctx = pan_context(pipe);
288
289 /* First of all, check the scissor to see if anything is drawn at all.
290 * If it's not, we drop the draw (mostly a conformance issue;
291 * well-behaved apps shouldn't hit this) */
292
293 if (panfrost_scissor_culls_everything(ctx))
294 return;
295
296 int mode = info->mode;
297
298 /* Fallback unsupported restart index */
299 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
300
301 if (info->primitive_restart && info->index_size
302 && info->restart_index != primitive_index) {
303 util_draw_vbo_without_prim_restart(pipe, info);
304 return;
305 }
306
307 /* Fallback for unsupported modes */
308
309 assert(ctx->rasterizer != NULL);
310
311 if (!(ctx->draw_modes & (1 << mode))) {
312 if (mode == PIPE_PRIM_QUADS && info->count == 4 && !ctx->rasterizer->base.flatshade) {
313 mode = PIPE_PRIM_TRIANGLE_FAN;
314 } else {
315 if (info->count < 4) {
316 /* Degenerate case? */
317 return;
318 }
319
320 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
321 util_primconvert_draw_vbo(ctx->primconvert, info);
322 return;
323 }
324 }
325
326 /* Now that we have a guaranteed terminating path, find the job.
327 * Assignment commented out to prevent unused warning */
328
329 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
330
331 panfrost_batch_add_fbo_bos(batch);
332 panfrost_batch_set_requirements(batch);
333
334 /* Take into account a negative bias */
335 ctx->vertex_count = info->count + abs(info->index_bias);
336 ctx->instance_count = info->instance_count;
337 ctx->active_prim = info->mode;
338
339 struct mali_vertex_tiler_prefix vertex_prefix, tiler_prefix;
340 struct mali_vertex_tiler_postfix vertex_postfix, tiler_postfix;
341 union midgard_primitive_size primitive_size;
342 unsigned vertex_count;
343
344 panfrost_vt_init(ctx, PIPE_SHADER_VERTEX, &vertex_prefix, &vertex_postfix);
345 panfrost_vt_init(ctx, PIPE_SHADER_FRAGMENT, &tiler_prefix, &tiler_postfix);
346
347 panfrost_vt_set_draw_info(ctx, info, g2m_draw_mode(mode),
348 &vertex_postfix, &tiler_prefix,
349 &tiler_postfix, &vertex_count,
350 &ctx->padded_count);
351
352 panfrost_statistics_record(ctx, info);
353
354 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
355 * vertex_count, 1) */
356
357 panfrost_pack_work_groups_fused(&vertex_prefix, &tiler_prefix,
358 1, vertex_count, info->instance_count,
359 1, 1, 1);
360
361 /* Emit all sort of descriptors. */
362 panfrost_emit_vertex_data(batch, &vertex_postfix);
363 panfrost_emit_varying_descriptor(batch,
364 ctx->padded_count *
365 ctx->instance_count,
366 &vertex_postfix, &tiler_postfix,
367 &primitive_size);
368 panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
369 panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
370 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
371 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
372 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
373 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
374 panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
375 panfrost_emit_const_buf(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
376 panfrost_emit_viewport(batch, &tiler_postfix);
377
378 panfrost_vt_update_primitive_size(ctx, &tiler_prefix, &primitive_size);
379
380 /* Fire off the draw itself */
381 panfrost_emit_vertex_tiler_jobs(batch, &vertex_prefix, &vertex_postfix,
382 &tiler_prefix, &tiler_postfix,
383 &primitive_size);
384
385 /* Adjust the batch stack size based on the new shader stack sizes. */
386 panfrost_batch_adjust_stack_size(batch);
387
388 /* Increment transform feedback offsets */
389 panfrost_update_streamout_offsets(ctx);
390 }
391
392 /* CSO state */
393
394 static void
395 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
396 {
397 free(hwcso);
398 }
399
400 static void *
401 panfrost_create_rasterizer_state(
402 struct pipe_context *pctx,
403 const struct pipe_rasterizer_state *cso)
404 {
405 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
406
407 so->base = *cso;
408
409 return so;
410 }
411
412 static void
413 panfrost_bind_rasterizer_state(
414 struct pipe_context *pctx,
415 void *hwcso)
416 {
417 struct panfrost_context *ctx = pan_context(pctx);
418
419 ctx->rasterizer = hwcso;
420
421 if (!hwcso)
422 return;
423
424 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
425 assert(ctx->rasterizer->base.offset_clamp == 0.0);
426
427 /* Point sprites are emulated */
428
429 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
430
431 if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
432 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
433 }
434
435 static void *
436 panfrost_create_vertex_elements_state(
437 struct pipe_context *pctx,
438 unsigned num_elements,
439 const struct pipe_vertex_element *elements)
440 {
441 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
442 struct panfrost_device *dev = pan_device(pctx->screen);
443
444 so->num_elements = num_elements;
445 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
446
447 for (int i = 0; i < num_elements; ++i) {
448 enum pipe_format fmt = elements[i].src_format;
449 const struct util_format_description *desc = util_format_description(fmt);
450 unsigned swizzle = 0;
451 if (dev->quirks & HAS_SWIZZLES)
452 swizzle = panfrost_translate_swizzle_4(desc->swizzle);
453 else
454 swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
455
456 enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
457 so->formats[i] = (hw_format << 12) | swizzle;
458 assert(hw_format);
459 }
460
461 /* Let's also prepare vertex builtins */
462 if (dev->quirks & HAS_SWIZZLES)
463 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
464 else
465 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
466
467 if (dev->quirks & HAS_SWIZZLES)
468 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
469 else
470 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
471
472 return so;
473 }
474
475 static void
476 panfrost_bind_vertex_elements_state(
477 struct pipe_context *pctx,
478 void *hwcso)
479 {
480 struct panfrost_context *ctx = pan_context(pctx);
481 ctx->vertex = hwcso;
482 }
483
484 static void *
485 panfrost_create_shader_state(
486 struct pipe_context *pctx,
487 const struct pipe_shader_state *cso,
488 enum pipe_shader_type stage)
489 {
490 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
491 struct panfrost_device *dev = pan_device(pctx->screen);
492 so->base = *cso;
493
494 /* Token deep copy to prevent memory corruption */
495
496 if (cso->type == PIPE_SHADER_IR_TGSI)
497 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
498
499 /* Precompile for shader-db if we need to */
500 if (unlikely((dev->debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
501 struct panfrost_context *ctx = pan_context(pctx);
502
503 struct panfrost_shader_state state;
504 uint64_t outputs_written;
505
506 panfrost_shader_compile(ctx, PIPE_SHADER_IR_NIR,
507 so->base.ir.nir,
508 tgsi_processor_to_shader_stage(stage),
509 &state, &outputs_written);
510 }
511
512 return so;
513 }
514
515 static void
516 panfrost_delete_shader_state(
517 struct pipe_context *pctx,
518 void *so)
519 {
520 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
521
522 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
523 /* TODO: leaks TGSI tokens! */
524 }
525
526 for (unsigned i = 0; i < cso->variant_count; ++i) {
527 struct panfrost_shader_state *shader_state = &cso->variants[i];
528 panfrost_bo_unreference(shader_state->bo);
529 shader_state->bo = NULL;
530 }
531 free(cso->variants);
532
533 free(so);
534 }
535
536 static void *
537 panfrost_create_sampler_state(
538 struct pipe_context *pctx,
539 const struct pipe_sampler_state *cso)
540 {
541 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
542 struct panfrost_device *device = pan_device(pctx->screen);
543
544 so->base = *cso;
545
546 if (device->quirks & IS_BIFROST)
547 panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw);
548 else
549 panfrost_sampler_desc_init(cso, &so->hw);
550
551 return so;
552 }
553
554 static void
555 panfrost_bind_sampler_states(
556 struct pipe_context *pctx,
557 enum pipe_shader_type shader,
558 unsigned start_slot, unsigned num_sampler,
559 void **sampler)
560 {
561 assert(start_slot == 0);
562
563 struct panfrost_context *ctx = pan_context(pctx);
564
565 /* XXX: Should upload, not just copy? */
566 ctx->sampler_count[shader] = num_sampler;
567 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
568 }
569
570 static bool
571 panfrost_variant_matches(
572 struct panfrost_context *ctx,
573 struct panfrost_shader_state *variant,
574 enum pipe_shader_type type)
575 {
576 struct panfrost_device *dev = pan_device(ctx->base.screen);
577 struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
578
579 bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
580
581 if (variant->outputs_read) {
582 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
583
584 unsigned i;
585 BITSET_FOREACH_SET(i, &variant->outputs_read, 8) {
586 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
587
588 if ((fb->nr_cbufs > i) && fb->cbufs[i])
589 fmt = fb->cbufs[i]->format;
590
591 const struct util_format_description *desc =
592 util_format_description(fmt);
593
594 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
595 fmt = PIPE_FORMAT_NONE;
596
597 if (variant->rt_formats[i] != fmt)
598 return false;
599 }
600 }
601
602 /* Point sprites TODO on bifrost, always pass */
603 if (is_fragment && rasterizer && (rasterizer->sprite_coord_enable |
604 variant->point_sprite_mask)
605 && !(dev->quirks & IS_BIFROST)) {
606 /* Ensure the same varyings are turned to point sprites */
607 if (rasterizer->sprite_coord_enable != variant->point_sprite_mask)
608 return false;
609
610 /* Ensure the orientation is correct */
611 bool upper_left =
612 rasterizer->sprite_coord_mode ==
613 PIPE_SPRITE_COORD_UPPER_LEFT;
614
615 if (variant->point_sprite_upper_left != upper_left)
616 return false;
617 }
618
619 /* Otherwise, we're good to go */
620 return true;
621 }
622
623 /**
624 * Fix an uncompiled shader's stream output info, and produce a bitmask
625 * of which VARYING_SLOT_* are captured for stream output.
626 *
627 * Core Gallium stores output->register_index as a "slot" number, where
628 * slots are assigned consecutively to all outputs in info->outputs_written.
629 * This naive packing of outputs doesn't work for us - we too have slots,
630 * but the layout is defined by the VUE map, which we won't have until we
631 * compile a specific shader variant. So, we remap these and simply store
632 * VARYING_SLOT_* in our copy's output->register_index fields.
633 *
634 * We then produce a bitmask of outputs which are used for SO.
635 *
636 * Implementation from iris.
637 */
638
639 static uint64_t
640 update_so_info(struct pipe_stream_output_info *so_info,
641 uint64_t outputs_written)
642 {
643 uint64_t so_outputs = 0;
644 uint8_t reverse_map[64] = {0};
645 unsigned slot = 0;
646
647 while (outputs_written)
648 reverse_map[slot++] = u_bit_scan64(&outputs_written);
649
650 for (unsigned i = 0; i < so_info->num_outputs; i++) {
651 struct pipe_stream_output *output = &so_info->output[i];
652
653 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
654 output->register_index = reverse_map[output->register_index];
655
656 so_outputs |= 1ull << output->register_index;
657 }
658
659 return so_outputs;
660 }
661
662 static void
663 panfrost_bind_shader_state(
664 struct pipe_context *pctx,
665 void *hwcso,
666 enum pipe_shader_type type)
667 {
668 struct panfrost_context *ctx = pan_context(pctx);
669 struct panfrost_device *dev = pan_device(ctx->base.screen);
670 ctx->shader[type] = hwcso;
671
672 if (!hwcso) return;
673
674 /* Match the appropriate variant */
675
676 signed variant = -1;
677 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
678
679 for (unsigned i = 0; i < variants->variant_count; ++i) {
680 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
681 variant = i;
682 break;
683 }
684 }
685
686 if (variant == -1) {
687 /* No variant matched, so create a new one */
688 variant = variants->variant_count++;
689
690 if (variants->variant_count > variants->variant_space) {
691 unsigned old_space = variants->variant_space;
692
693 variants->variant_space *= 2;
694 if (variants->variant_space == 0)
695 variants->variant_space = 1;
696
697 /* Arbitrary limit to stop runaway programs from
698 * creating an unbounded number of shader variants. */
699 assert(variants->variant_space < 1024);
700
701 unsigned msize = sizeof(struct panfrost_shader_state);
702 variants->variants = realloc(variants->variants,
703 variants->variant_space * msize);
704
705 memset(&variants->variants[old_space], 0,
706 (variants->variant_space - old_space) * msize);
707 }
708
709 struct panfrost_shader_state *v =
710 &variants->variants[variant];
711
712 if (type == PIPE_SHADER_FRAGMENT) {
713 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
714 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
715 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
716
717 if ((fb->nr_cbufs > i) && fb->cbufs[i])
718 fmt = fb->cbufs[i]->format;
719
720 const struct util_format_description *desc =
721 util_format_description(fmt);
722
723 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
724 fmt = PIPE_FORMAT_NONE;
725
726 v->rt_formats[i] = fmt;
727 }
728
729 /* Point sprites are TODO on Bifrost */
730 if (ctx->rasterizer && !(dev->quirks & IS_BIFROST)) {
731 v->point_sprite_mask = ctx->rasterizer->base.sprite_coord_enable;
732 v->point_sprite_upper_left =
733 ctx->rasterizer->base.sprite_coord_mode ==
734 PIPE_SPRITE_COORD_UPPER_LEFT;
735 }
736 }
737 }
738
739 /* Select this variant */
740 variants->active_variant = variant;
741
742 struct panfrost_shader_state *shader_state = &variants->variants[variant];
743 assert(panfrost_variant_matches(ctx, shader_state, type));
744
745 /* We finally have a variant, so compile it */
746
747 if (!shader_state->compiled) {
748 uint64_t outputs_written = 0;
749
750 panfrost_shader_compile(ctx, variants->base.type,
751 variants->base.type == PIPE_SHADER_IR_NIR ?
752 variants->base.ir.nir :
753 variants->base.tokens,
754 tgsi_processor_to_shader_stage(type),
755 shader_state,
756 &outputs_written);
757
758 shader_state->compiled = true;
759
760 /* Fixup the stream out information, since what Gallium returns
761 * normally is mildly insane */
762
763 shader_state->stream_output = variants->base.stream_output;
764 shader_state->so_mask =
765 update_so_info(&shader_state->stream_output, outputs_written);
766 }
767 }
768
769 static void *
770 panfrost_create_vs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
771 {
772 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
773 }
774
775 static void *
776 panfrost_create_fs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
777 {
778 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
779 }
780
781 static void
782 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
783 {
784 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
785 }
786
787 static void
788 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
789 {
790 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
791 }
792
793 static void
794 panfrost_set_vertex_buffers(
795 struct pipe_context *pctx,
796 unsigned start_slot,
797 unsigned num_buffers,
798 const struct pipe_vertex_buffer *buffers)
799 {
800 struct panfrost_context *ctx = pan_context(pctx);
801
802 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
803 }
804
805 static void
806 panfrost_set_constant_buffer(
807 struct pipe_context *pctx,
808 enum pipe_shader_type shader, uint index,
809 const struct pipe_constant_buffer *buf)
810 {
811 struct panfrost_context *ctx = pan_context(pctx);
812 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
813
814 util_copy_constant_buffer(&pbuf->cb[index], buf);
815
816 unsigned mask = (1 << index);
817
818 if (unlikely(!buf)) {
819 pbuf->enabled_mask &= ~mask;
820 pbuf->dirty_mask &= ~mask;
821 return;
822 }
823
824 pbuf->enabled_mask |= mask;
825 pbuf->dirty_mask |= mask;
826 }
827
828 static void
829 panfrost_set_stencil_ref(
830 struct pipe_context *pctx,
831 const struct pipe_stencil_ref *ref)
832 {
833 struct panfrost_context *ctx = pan_context(pctx);
834 ctx->stencil_ref = *ref;
835 }
836
837 void
838 panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
839 struct pipe_context *pctx,
840 struct pipe_resource *texture)
841 {
842 struct panfrost_device *device = pan_device(pctx->screen);
843 struct panfrost_resource *prsrc = (struct panfrost_resource *)texture;
844 enum pipe_format format = so->base.format;
845 assert(prsrc->bo);
846
847 /* Format to access the stencil portion of a Z32_S8 texture */
848 if (format == PIPE_FORMAT_X32_S8X24_UINT) {
849 assert(prsrc->separate_stencil);
850 texture = &prsrc->separate_stencil->base;
851 prsrc = (struct panfrost_resource *)texture;
852 format = texture->format;
853 }
854
855 const struct util_format_description *desc = util_format_description(format);
856
857 bool fake_rgtc = !panfrost_supports_compressed_format(device, MALI_BC4_UNORM);
858
859 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC && fake_rgtc) {
860 if (desc->is_snorm)
861 format = PIPE_FORMAT_R8G8B8A8_SNORM;
862 else
863 format = PIPE_FORMAT_R8G8B8A8_UNORM;
864 desc = util_format_description(format);
865 }
866
867 so->texture_bo = prsrc->bo->gpu;
868 so->modifier = prsrc->modifier;
869
870 unsigned char user_swizzle[4] = {
871 so->base.swizzle_r,
872 so->base.swizzle_g,
873 so->base.swizzle_b,
874 so->base.swizzle_a
875 };
876
877 /* In the hardware, array_size refers specifically to array textures,
878 * whereas in Gallium, it also covers cubemaps */
879
880 unsigned array_size = texture->array_size;
881 unsigned depth = texture->depth0;
882
883 if (so->base.target == PIPE_TEXTURE_CUBE) {
884 /* TODO: Cubemap arrays */
885 assert(array_size == 6);
886 array_size /= 6;
887 }
888
889 /* MSAA only supported for 2D textures (and 2D texture arrays via an
890 * extension currently unimplemented */
891
892 if (so->base.target == PIPE_TEXTURE_2D) {
893 assert(depth == 1);
894 depth = texture->nr_samples;
895 } else {
896 /* MSAA only supported for 2D textures */
897 assert(texture->nr_samples <= 1);
898 }
899
900 enum mali_texture_dimension type =
901 panfrost_translate_texture_dimension(so->base.target);
902
903 if (device->quirks & IS_BIFROST) {
904 unsigned char composed_swizzle[4];
905 util_format_compose_swizzles(desc->swizzle, user_swizzle, composed_swizzle);
906
907 unsigned size = panfrost_estimate_texture_payload_size(
908 so->base.u.tex.first_level,
909 so->base.u.tex.last_level,
910 so->base.u.tex.first_layer,
911 so->base.u.tex.last_layer,
912 texture->nr_samples,
913 type, prsrc->modifier);
914
915 so->bo = panfrost_bo_create(device, size, 0);
916
917 panfrost_new_texture_bifrost(
918 &so->bifrost_descriptor,
919 texture->width0, texture->height0,
920 depth, array_size,
921 format,
922 type, prsrc->modifier,
923 so->base.u.tex.first_level,
924 so->base.u.tex.last_level,
925 so->base.u.tex.first_layer,
926 so->base.u.tex.last_layer,
927 texture->nr_samples,
928 prsrc->cubemap_stride,
929 panfrost_translate_swizzle_4(composed_swizzle),
930 prsrc->bo->gpu,
931 prsrc->slices,
932 so->bo);
933 } else {
934 unsigned size = panfrost_estimate_texture_payload_size(
935 so->base.u.tex.first_level,
936 so->base.u.tex.last_level,
937 so->base.u.tex.first_layer,
938 so->base.u.tex.last_layer,
939 texture->nr_samples,
940 type, prsrc->modifier);
941 size += MALI_MIDGARD_TEXTURE_LENGTH;
942
943 so->bo = panfrost_bo_create(device, size, 0);
944
945 panfrost_new_texture(
946 so->bo->cpu,
947 texture->width0, texture->height0,
948 depth, array_size,
949 format,
950 type, prsrc->modifier,
951 so->base.u.tex.first_level,
952 so->base.u.tex.last_level,
953 so->base.u.tex.first_layer,
954 so->base.u.tex.last_layer,
955 texture->nr_samples,
956 prsrc->cubemap_stride,
957 panfrost_translate_swizzle_4(user_swizzle),
958 prsrc->bo->gpu,
959 prsrc->slices);
960 }
961 }
962
963 static struct pipe_sampler_view *
964 panfrost_create_sampler_view(
965 struct pipe_context *pctx,
966 struct pipe_resource *texture,
967 const struct pipe_sampler_view *template)
968 {
969 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
970
971 pipe_reference(NULL, &texture->reference);
972
973 so->base = *template;
974 so->base.texture = texture;
975 so->base.reference.count = 1;
976 so->base.context = pctx;
977
978 panfrost_create_sampler_view_bo(so, pctx, texture);
979
980 return (struct pipe_sampler_view *) so;
981 }
982
983 static void
984 panfrost_set_sampler_views(
985 struct pipe_context *pctx,
986 enum pipe_shader_type shader,
987 unsigned start_slot, unsigned num_views,
988 struct pipe_sampler_view **views)
989 {
990 struct panfrost_context *ctx = pan_context(pctx);
991 unsigned new_nr = 0;
992 unsigned i;
993
994 assert(start_slot == 0);
995
996 for (i = 0; i < num_views; ++i) {
997 if (views[i])
998 new_nr = i + 1;
999 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
1000 views[i]);
1001 }
1002
1003 for (; i < ctx->sampler_view_count[shader]; i++) {
1004 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
1005 NULL);
1006 }
1007 ctx->sampler_view_count[shader] = new_nr;
1008 }
1009
1010 static void
1011 panfrost_sampler_view_destroy(
1012 struct pipe_context *pctx,
1013 struct pipe_sampler_view *pview)
1014 {
1015 struct panfrost_sampler_view *view = (struct panfrost_sampler_view *) pview;
1016
1017 pipe_resource_reference(&pview->texture, NULL);
1018 panfrost_bo_unreference(view->bo);
1019 ralloc_free(view);
1020 }
1021
1022 static void
1023 panfrost_set_shader_buffers(
1024 struct pipe_context *pctx,
1025 enum pipe_shader_type shader,
1026 unsigned start, unsigned count,
1027 const struct pipe_shader_buffer *buffers,
1028 unsigned writable_bitmask)
1029 {
1030 struct panfrost_context *ctx = pan_context(pctx);
1031
1032 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
1033 buffers, start, count);
1034 }
1035
1036 static void
1037 panfrost_set_framebuffer_state(struct pipe_context *pctx,
1038 const struct pipe_framebuffer_state *fb)
1039 {
1040 struct panfrost_context *ctx = pan_context(pctx);
1041
1042 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
1043 ctx->batch = NULL;
1044 panfrost_invalidate_frame(ctx);
1045
1046 /* We may need to generate a new variant if the fragment shader is
1047 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1048 struct panfrost_shader_variants *fs = ctx->shader[PIPE_SHADER_FRAGMENT];
1049
1050 if (fs && fs->variant_count && fs->variants[fs->active_variant].outputs_read)
1051 ctx->base.bind_fs_state(&ctx->base, fs);
1052 }
1053
1054 static inline unsigned
1055 pan_pipe_to_stencil_op(enum pipe_stencil_op in)
1056 {
1057 switch (in) {
1058 case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
1059 case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
1060 case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
1061 case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
1062 case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
1063 case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
1064 case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
1065 case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
1066 default: unreachable("Invalid stencil op");
1067 }
1068 }
1069
1070 static inline void
1071 pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
1072 {
1073 pan_pack(out, STENCIL, cfg) {
1074 cfg.mask = in->valuemask;
1075 cfg.compare_function = panfrost_translate_compare_func(in->func);
1076 cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
1077 cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
1078 cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
1079 }
1080 }
1081
1082 static void *
1083 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
1084 const struct pipe_depth_stencil_alpha_state *zsa)
1085 {
1086 struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
1087 so->base = *zsa;
1088
1089 pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
1090 pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
1091
1092 so->stencil_mask_front = zsa->stencil[0].writemask;
1093
1094 if (zsa->stencil[1].enabled)
1095 so->stencil_mask_back = zsa->stencil[1].writemask;
1096 else
1097 so->stencil_mask_back = so->stencil_mask_front;
1098
1099 /* Alpha lowered by frontend */
1100 assert(!zsa->alpha.enabled);
1101
1102 /* TODO: Bounds test should be easy */
1103 assert(!zsa->depth.bounds_test);
1104
1105 return so;
1106 }
1107
1108 static void
1109 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
1110 void *cso)
1111 {
1112 struct panfrost_context *ctx = pan_context(pipe);
1113 struct panfrost_zsa_state *zsa = cso;
1114 ctx->depth_stencil = zsa;
1115 }
1116
1117 static void
1118 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
1119 {
1120 free( depth );
1121 }
1122
1123 static void
1124 panfrost_set_sample_mask(struct pipe_context *pipe,
1125 unsigned sample_mask)
1126 {
1127 struct panfrost_context *ctx = pan_context(pipe);
1128 ctx->sample_mask = sample_mask;
1129 }
1130
1131 static void
1132 panfrost_set_min_samples(struct pipe_context *pipe,
1133 unsigned min_samples)
1134 {
1135 struct panfrost_context *ctx = pan_context(pipe);
1136 ctx->min_samples = min_samples;
1137 }
1138
1139
1140 static void
1141 panfrost_set_clip_state(struct pipe_context *pipe,
1142 const struct pipe_clip_state *clip)
1143 {
1144 //struct panfrost_context *panfrost = pan_context(pipe);
1145 }
1146
1147 static void
1148 panfrost_set_viewport_states(struct pipe_context *pipe,
1149 unsigned start_slot,
1150 unsigned num_viewports,
1151 const struct pipe_viewport_state *viewports)
1152 {
1153 struct panfrost_context *ctx = pan_context(pipe);
1154
1155 assert(start_slot == 0);
1156 assert(num_viewports == 1);
1157
1158 ctx->pipe_viewport = *viewports;
1159 }
1160
1161 static void
1162 panfrost_set_scissor_states(struct pipe_context *pipe,
1163 unsigned start_slot,
1164 unsigned num_scissors,
1165 const struct pipe_scissor_state *scissors)
1166 {
1167 struct panfrost_context *ctx = pan_context(pipe);
1168
1169 assert(start_slot == 0);
1170 assert(num_scissors == 1);
1171
1172 ctx->scissor = *scissors;
1173 }
1174
1175 static void
1176 panfrost_set_polygon_stipple(struct pipe_context *pipe,
1177 const struct pipe_poly_stipple *stipple)
1178 {
1179 //struct panfrost_context *panfrost = pan_context(pipe);
1180 }
1181
1182 static void
1183 panfrost_set_active_query_state(struct pipe_context *pipe,
1184 bool enable)
1185 {
1186 struct panfrost_context *ctx = pan_context(pipe);
1187 ctx->active_queries = enable;
1188 }
1189
1190 static void
1191 panfrost_destroy(struct pipe_context *pipe)
1192 {
1193 struct panfrost_context *panfrost = pan_context(pipe);
1194
1195 if (panfrost->blitter)
1196 util_blitter_destroy(panfrost->blitter);
1197
1198 if (panfrost->blitter_wallpaper)
1199 util_blitter_destroy(panfrost->blitter_wallpaper);
1200
1201 util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
1202 u_upload_destroy(pipe->stream_uploader);
1203
1204 ralloc_free(pipe);
1205 }
1206
1207 static struct pipe_query *
1208 panfrost_create_query(struct pipe_context *pipe,
1209 unsigned type,
1210 unsigned index)
1211 {
1212 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
1213
1214 q->type = type;
1215 q->index = index;
1216
1217 return (struct pipe_query *) q;
1218 }
1219
1220 static void
1221 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
1222 {
1223 struct panfrost_query *query = (struct panfrost_query *) q;
1224
1225 if (query->bo) {
1226 panfrost_bo_unreference(query->bo);
1227 query->bo = NULL;
1228 }
1229
1230 ralloc_free(q);
1231 }
1232
1233 static bool
1234 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
1235 {
1236 struct panfrost_context *ctx = pan_context(pipe);
1237 struct panfrost_query *query = (struct panfrost_query *) q;
1238
1239 switch (query->type) {
1240 case PIPE_QUERY_OCCLUSION_COUNTER:
1241 case PIPE_QUERY_OCCLUSION_PREDICATE:
1242 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1243 /* Allocate a bo for the query results to be stored */
1244 if (!query->bo) {
1245 query->bo = panfrost_bo_create(
1246 pan_device(ctx->base.screen),
1247 sizeof(unsigned), 0);
1248 }
1249
1250 unsigned *result = (unsigned *)query->bo->cpu;
1251 *result = 0; /* Default to 0 if nothing at all drawn. */
1252 ctx->occlusion_query = query;
1253 break;
1254
1255 /* Geometry statistics are computed in the driver. XXX: geom/tess
1256 * shaders.. */
1257
1258 case PIPE_QUERY_PRIMITIVES_GENERATED:
1259 query->start = ctx->prims_generated;
1260 break;
1261 case PIPE_QUERY_PRIMITIVES_EMITTED:
1262 query->start = ctx->tf_prims_generated;
1263 break;
1264
1265 default:
1266 /* TODO: timestamp queries, etc? */
1267 break;
1268 }
1269
1270 return true;
1271 }
1272
1273 static bool
1274 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
1275 {
1276 struct panfrost_context *ctx = pan_context(pipe);
1277 struct panfrost_query *query = (struct panfrost_query *) q;
1278
1279 switch (query->type) {
1280 case PIPE_QUERY_OCCLUSION_COUNTER:
1281 case PIPE_QUERY_OCCLUSION_PREDICATE:
1282 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1283 ctx->occlusion_query = NULL;
1284 break;
1285 case PIPE_QUERY_PRIMITIVES_GENERATED:
1286 query->end = ctx->prims_generated;
1287 break;
1288 case PIPE_QUERY_PRIMITIVES_EMITTED:
1289 query->end = ctx->tf_prims_generated;
1290 break;
1291 }
1292
1293 return true;
1294 }
1295
1296 static bool
1297 panfrost_get_query_result(struct pipe_context *pipe,
1298 struct pipe_query *q,
1299 bool wait,
1300 union pipe_query_result *vresult)
1301 {
1302 struct panfrost_query *query = (struct panfrost_query *) q;
1303 struct panfrost_context *ctx = pan_context(pipe);
1304
1305
1306 switch (query->type) {
1307 case PIPE_QUERY_OCCLUSION_COUNTER:
1308 case PIPE_QUERY_OCCLUSION_PREDICATE:
1309 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1310 panfrost_flush_batches_accessing_bo(ctx, query->bo, false);
1311 panfrost_bo_wait(query->bo, INT64_MAX, false);
1312
1313 /* Read back the query results */
1314 unsigned *result = (unsigned *) query->bo->cpu;
1315 unsigned passed = *result;
1316
1317 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1318 vresult->u64 = passed;
1319 } else {
1320 vresult->b = !!passed;
1321 }
1322
1323 break;
1324
1325 case PIPE_QUERY_PRIMITIVES_GENERATED:
1326 case PIPE_QUERY_PRIMITIVES_EMITTED:
1327 panfrost_flush_all_batches(ctx, 0);
1328 vresult->u64 = query->end - query->start;
1329 break;
1330
1331 default:
1332 /* TODO: more queries */
1333 break;
1334 }
1335
1336 return true;
1337 }
1338
1339 static struct pipe_stream_output_target *
1340 panfrost_create_stream_output_target(struct pipe_context *pctx,
1341 struct pipe_resource *prsc,
1342 unsigned buffer_offset,
1343 unsigned buffer_size)
1344 {
1345 struct pipe_stream_output_target *target;
1346
1347 target = rzalloc(pctx, struct pipe_stream_output_target);
1348
1349 if (!target)
1350 return NULL;
1351
1352 pipe_reference_init(&target->reference, 1);
1353 pipe_resource_reference(&target->buffer, prsc);
1354
1355 target->context = pctx;
1356 target->buffer_offset = buffer_offset;
1357 target->buffer_size = buffer_size;
1358
1359 return target;
1360 }
1361
1362 static void
1363 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
1364 struct pipe_stream_output_target *target)
1365 {
1366 pipe_resource_reference(&target->buffer, NULL);
1367 ralloc_free(target);
1368 }
1369
1370 static void
1371 panfrost_set_stream_output_targets(struct pipe_context *pctx,
1372 unsigned num_targets,
1373 struct pipe_stream_output_target **targets,
1374 const unsigned *offsets)
1375 {
1376 struct panfrost_context *ctx = pan_context(pctx);
1377 struct panfrost_streamout *so = &ctx->streamout;
1378
1379 assert(num_targets <= ARRAY_SIZE(so->targets));
1380
1381 for (unsigned i = 0; i < num_targets; i++) {
1382 if (offsets[i] != -1)
1383 so->offsets[i] = offsets[i];
1384
1385 pipe_so_target_reference(&so->targets[i], targets[i]);
1386 }
1387
1388 for (unsigned i = 0; i < so->num_targets; i++)
1389 pipe_so_target_reference(&so->targets[i], NULL);
1390
1391 so->num_targets = num_targets;
1392 }
1393
1394 struct pipe_context *
1395 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
1396 {
1397 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
1398 struct pipe_context *gallium = (struct pipe_context *) ctx;
1399 struct panfrost_device *dev = pan_device(screen);
1400
1401 gallium->screen = screen;
1402
1403 gallium->destroy = panfrost_destroy;
1404
1405 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
1406
1407 gallium->flush = panfrost_flush;
1408 gallium->clear = panfrost_clear;
1409 gallium->draw_vbo = panfrost_draw_vbo;
1410 gallium->texture_barrier = panfrost_texture_barrier;
1411
1412 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
1413 gallium->set_constant_buffer = panfrost_set_constant_buffer;
1414 gallium->set_shader_buffers = panfrost_set_shader_buffers;
1415
1416 gallium->set_stencil_ref = panfrost_set_stencil_ref;
1417
1418 gallium->create_sampler_view = panfrost_create_sampler_view;
1419 gallium->set_sampler_views = panfrost_set_sampler_views;
1420 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
1421
1422 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
1423 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
1424 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
1425
1426 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
1427 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
1428 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
1429
1430 gallium->create_fs_state = panfrost_create_fs_state;
1431 gallium->delete_fs_state = panfrost_delete_shader_state;
1432 gallium->bind_fs_state = panfrost_bind_fs_state;
1433
1434 gallium->create_vs_state = panfrost_create_vs_state;
1435 gallium->delete_vs_state = panfrost_delete_shader_state;
1436 gallium->bind_vs_state = panfrost_bind_vs_state;
1437
1438 gallium->create_sampler_state = panfrost_create_sampler_state;
1439 gallium->delete_sampler_state = panfrost_generic_cso_delete;
1440 gallium->bind_sampler_states = panfrost_bind_sampler_states;
1441
1442 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
1443 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
1444 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
1445
1446 gallium->set_sample_mask = panfrost_set_sample_mask;
1447 gallium->set_min_samples = panfrost_set_min_samples;
1448
1449 gallium->set_clip_state = panfrost_set_clip_state;
1450 gallium->set_viewport_states = panfrost_set_viewport_states;
1451 gallium->set_scissor_states = panfrost_set_scissor_states;
1452 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
1453 gallium->set_active_query_state = panfrost_set_active_query_state;
1454
1455 gallium->create_query = panfrost_create_query;
1456 gallium->destroy_query = panfrost_destroy_query;
1457 gallium->begin_query = panfrost_begin_query;
1458 gallium->end_query = panfrost_end_query;
1459 gallium->get_query_result = panfrost_get_query_result;
1460
1461 gallium->create_stream_output_target = panfrost_create_stream_output_target;
1462 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
1463 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
1464
1465 panfrost_resource_context_init(gallium);
1466 panfrost_blend_context_init(gallium);
1467 panfrost_compute_context_init(gallium);
1468
1469 gallium->stream_uploader = u_upload_create_default(gallium);
1470 gallium->const_uploader = gallium->stream_uploader;
1471 assert(gallium->stream_uploader);
1472
1473 /* All of our GPUs support ES mode. Midgard supports additionally
1474 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1475
1476 ctx->draw_modes = (1 << (PIPE_PRIM_QUADS + 1)) - 1;
1477
1478 if (!(dev->quirks & IS_BIFROST)) {
1479 ctx->draw_modes |= (1 << PIPE_PRIM_QUAD_STRIP);
1480 ctx->draw_modes |= (1 << PIPE_PRIM_POLYGON);
1481 }
1482
1483 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
1484
1485 ctx->blitter = util_blitter_create(gallium);
1486 ctx->blitter_wallpaper = util_blitter_create(gallium);
1487
1488 assert(ctx->blitter);
1489 assert(ctx->blitter_wallpaper);
1490
1491 /* Prepare for render! */
1492
1493 panfrost_batch_init(ctx);
1494 panfrost_invalidate_frame(ctx);
1495
1496 if (!(dev->quirks & IS_BIFROST)) {
1497 for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c)
1498 ctx->blit_blend.rt[c].shaders = _mesa_hash_table_u64_create(ctx);
1499 }
1500
1501 /* By default mask everything on */
1502 ctx->sample_mask = ~0;
1503
1504 return gallium;
1505 }