2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
85 t
.heap_start
= device
->tiler_heap
->gpu
;
86 t
.heap_end
= device
->tiler_heap
->gpu
+ device
->tiler_heap
->size
;
88 struct panfrost_bo
*tiler_dummy
;
90 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
91 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t
.heap_start
= tiler_dummy
->gpu
;
95 t
.heap_end
= t
.heap_start
;
97 /* Use a dummy polygon list */
98 t
.polygon_list
= tiler_dummy
->gpu
;
100 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
104 t
.hierarchy_mask
= MALI_TILER_USER
;
105 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
109 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
113 t
.polygon_list_body
=
114 t
.polygon_list
+ header_size
;
121 struct pipe_context
*pipe
,
123 const struct pipe_scissor_state
*scissor_state
,
124 const union pipe_color_union
*color
,
125 double depth
, unsigned stencil
)
127 struct panfrost_context
*ctx
= pan_context(pipe
);
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
135 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
136 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
140 panfrost_writes_point_size(struct panfrost_context
*ctx
)
142 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
143 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
145 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
148 /* The entire frame is in memory -- send it off to the kernel! */
152 struct pipe_context
*pipe
,
153 struct pipe_fence_handle
**fence
,
156 struct panfrost_context
*ctx
= pan_context(pipe
);
157 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
158 uint32_t syncobj
= 0;
161 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
163 /* Submit all pending jobs */
164 panfrost_flush_all_batches(ctx
, syncobj
);
167 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
168 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
169 *fence
= (struct pipe_fence_handle
*)f
;
172 if (dev
->debug
& PAN_DBG_TRACE
)
173 pandecode_next_frame();
177 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
179 struct panfrost_context
*ctx
= pan_context(pipe
);
180 panfrost_flush_all_batches(ctx
, 0);
183 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
186 pan_draw_mode(enum pipe_prim_type mode
)
191 DEFINE_CASE(LINE_LOOP
);
192 DEFINE_CASE(LINE_STRIP
);
193 DEFINE_CASE(TRIANGLES
);
194 DEFINE_CASE(TRIANGLE_STRIP
);
195 DEFINE_CASE(TRIANGLE_FAN
);
197 DEFINE_CASE(QUAD_STRIP
);
198 DEFINE_CASE(POLYGON
);
201 unreachable("Invalid draw mode");
208 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
210 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
212 /* Check if we're scissoring at all */
214 if (!ctx
->rasterizer
->base
.scissor
)
217 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
220 /* Count generated primitives (when there is no geom/tess shaders) for
221 * transform feedback */
224 panfrost_statistics_record(
225 struct panfrost_context
*ctx
,
226 const struct pipe_draw_info
*info
)
228 if (!ctx
->active_queries
)
231 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
232 ctx
->prims_generated
+= prims
;
234 if (!ctx
->streamout
.num_targets
)
237 ctx
->tf_prims_generated
+= prims
;
241 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
243 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
246 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
248 ctx
->streamout
.offsets
[i
] += count
;
253 pan_emit_draw_descs(struct panfrost_batch
*batch
,
254 struct MALI_DRAW
*d
, enum pipe_shader_type st
)
256 d
->offset_start
= batch
->ctx
->offset_start
;
257 d
->instances
= batch
->ctx
->instance_count
> 1 ?
258 batch
->ctx
->padded_count
: 1;
260 d
->uniform_buffers
= panfrost_emit_const_buf(batch
, st
, &d
->push_uniforms
);
261 d
->textures
= panfrost_emit_texture_descriptors(batch
, st
);
262 d
->samplers
= panfrost_emit_sampler_descriptors(batch
, st
);
267 struct pipe_context
*pipe
,
268 const struct pipe_draw_info
*info
)
270 struct panfrost_context
*ctx
= pan_context(pipe
);
271 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
273 /* First of all, check the scissor to see if anything is drawn at all.
274 * If it's not, we drop the draw (mostly a conformance issue;
275 * well-behaved apps shouldn't hit this) */
277 if (panfrost_scissor_culls_everything(ctx
))
280 int mode
= info
->mode
;
282 /* Fallback unsupported restart index */
283 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
285 if (info
->primitive_restart
&& info
->index_size
286 && info
->restart_index
!= primitive_index
) {
287 util_draw_vbo_without_prim_restart(pipe
, info
);
291 /* Fallback for unsupported modes */
293 assert(ctx
->rasterizer
!= NULL
);
295 if (!(ctx
->draw_modes
& (1 << mode
))) {
296 if (info
->count
< 4) {
297 /* Degenerate case? */
301 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
302 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
306 /* Now that we have a guaranteed terminating path, find the job. */
308 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
309 panfrost_batch_set_requirements(batch
);
311 /* Take into account a negative bias */
312 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
313 ctx
->instance_count
= info
->instance_count
;
314 ctx
->active_prim
= info
->mode
;
316 struct mali_vertex_tiler_prefix vertex_prefix
= { 0 }, tiler_prefix
= { 0 };
317 struct mali_draw_packed vertex_postfix
, tiler_postfix
;
318 union midgard_primitive_size primitive_size
;
319 unsigned vertex_count
;
321 mali_ptr shared_mem
= (device
->quirks
& IS_BIFROST
) ?
322 panfrost_vt_emit_shared_memory(batch
) :
323 panfrost_batch_reserve_framebuffer(batch
);
325 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
326 SET_BIT(tiler_prefix
.unknown_draw
, MALI_DRAW_FLATSHADE_FIRST
,
327 rast
->flatshade_first
);
329 tiler_prefix
.draw_mode
= pan_draw_mode(mode
);
331 unsigned draw_flags
= 0x3000;
333 if (panfrost_writes_point_size(ctx
))
334 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
336 if (info
->primitive_restart
)
337 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
339 if (info
->index_size
) {
340 unsigned min_index
= 0, max_index
= 0;
342 tiler_prefix
.indices
= panfrost_get_index_buffer_bounded(ctx
,
347 /* Use the corresponding values */
348 vertex_count
= max_index
- min_index
+ 1;
349 ctx
->offset_start
= min_index
+ info
->index_bias
;
350 tiler_prefix
.offset_bias_correction
= -min_index
;
351 tiler_prefix
.index_count
= MALI_POSITIVE(info
->count
);
352 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
354 vertex_count
= ctx
->vertex_count
;
355 ctx
->offset_start
= info
->start
;
356 tiler_prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
359 tiler_prefix
.unknown_draw
= draw_flags
;
361 /* Encode the padded vertex count */
363 if (info
->instance_count
> 1)
364 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
366 ctx
->padded_count
= vertex_count
;
368 panfrost_statistics_record(ctx
, info
);
370 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
371 1, vertex_count
, info
->instance_count
,
374 /* Emit all sort of descriptors. */
375 mali_ptr varyings
= 0, vs_vary
= 0, fs_vary
= 0, pos
= 0, psiz
= 0;
377 panfrost_emit_varying_descriptor(batch
,
380 &vs_vary
, &fs_vary
, &varyings
,
383 pan_pack(&vertex_postfix
, DRAW
, cfg
) {
384 cfg
.unknown_1
= (device
->quirks
& IS_BIFROST
) ? 0x2 : 0x6;
385 cfg
.state
= panfrost_emit_compute_shader_meta(batch
, PIPE_SHADER_VERTEX
);
386 cfg
.attributes
= panfrost_emit_vertex_data(batch
, &cfg
.attribute_buffers
);
387 cfg
.varyings
= vs_vary
;
388 cfg
.varying_buffers
= varyings
;
389 cfg
.shared
= shared_mem
;
390 pan_emit_draw_descs(batch
, &cfg
, PIPE_SHADER_VERTEX
);
393 pan_pack(&tiler_postfix
, DRAW
, cfg
) {
394 cfg
.unknown_1
= (device
->quirks
& IS_BIFROST
) ? 0x3 : 0x7;
395 cfg
.front_face_ccw
= rast
->front_ccw
;
396 cfg
.cull_front_face
= rast
->cull_face
& PIPE_FACE_FRONT
;
397 cfg
.cull_back_face
= rast
->cull_face
& PIPE_FACE_BACK
;
399 cfg
.state
= panfrost_emit_frag_shader_meta(batch
);
400 cfg
.viewport
= panfrost_emit_viewport(batch
);
401 cfg
.varyings
= fs_vary
;
402 cfg
.varying_buffers
= varyings
;
403 cfg
.shared
= shared_mem
;
405 pan_emit_draw_descs(batch
, &cfg
, PIPE_SHADER_FRAGMENT
);
407 if (ctx
->occlusion_query
) {
408 cfg
.occlusion_query
= MALI_OCCLUSION_MODE_PREDICATE
;
409 cfg
.occlusion
= ctx
->occlusion_query
->bo
->gpu
;
410 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
411 PAN_BO_ACCESS_SHARED
|
413 PAN_BO_ACCESS_FRAGMENT
);
417 primitive_size
.pointer
= psiz
;
418 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
420 /* Fire off the draw itself */
421 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
422 &tiler_prefix
, &tiler_postfix
,
425 /* Adjust the batch stack size based on the new shader stack sizes. */
426 panfrost_batch_adjust_stack_size(batch
);
428 /* Increment transform feedback offsets */
429 panfrost_update_streamout_offsets(ctx
);
435 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
441 panfrost_create_rasterizer_state(
442 struct pipe_context
*pctx
,
443 const struct pipe_rasterizer_state
*cso
)
445 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
449 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
450 assert(cso
->offset_clamp
== 0.0);
456 panfrost_bind_rasterizer_state(
457 struct pipe_context
*pctx
,
460 struct panfrost_context
*ctx
= pan_context(pctx
);
462 ctx
->rasterizer
= hwcso
;
467 /* Point sprites are emulated */
469 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
471 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
472 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
476 panfrost_create_vertex_elements_state(
477 struct pipe_context
*pctx
,
478 unsigned num_elements
,
479 const struct pipe_vertex_element
*elements
)
481 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
482 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
484 so
->num_elements
= num_elements
;
485 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
487 for (int i
= 0; i
< num_elements
; ++i
) {
488 enum pipe_format fmt
= elements
[i
].src_format
;
489 const struct util_format_description
*desc
= util_format_description(fmt
);
490 unsigned swizzle
= 0;
491 if (dev
->quirks
& HAS_SWIZZLES
)
492 swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
494 swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
496 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
497 so
->formats
[i
] = (hw_format
<< 12) | swizzle
;
501 /* Let's also prepare vertex builtins */
502 if (dev
->quirks
& HAS_SWIZZLES
)
503 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
505 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
507 if (dev
->quirks
& HAS_SWIZZLES
)
508 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
510 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
516 panfrost_bind_vertex_elements_state(
517 struct pipe_context
*pctx
,
520 struct panfrost_context
*ctx
= pan_context(pctx
);
525 panfrost_create_shader_state(
526 struct pipe_context
*pctx
,
527 const struct pipe_shader_state
*cso
,
528 enum pipe_shader_type stage
)
530 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
531 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
534 /* Token deep copy to prevent memory corruption */
536 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
537 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
539 /* Precompile for shader-db if we need to */
540 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
541 struct panfrost_context
*ctx
= pan_context(pctx
);
543 struct panfrost_shader_state state
= { 0 };
544 uint64_t outputs_written
;
546 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
548 tgsi_processor_to_shader_stage(stage
),
549 &state
, &outputs_written
);
556 panfrost_delete_shader_state(
557 struct pipe_context
*pctx
,
560 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
562 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
563 /* TODO: leaks TGSI tokens! */
566 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
567 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
568 panfrost_bo_unreference(shader_state
->bo
);
570 if (shader_state
->upload
.rsrc
)
571 pipe_resource_reference(&shader_state
->upload
.rsrc
, NULL
);
573 shader_state
->bo
= NULL
;
582 panfrost_create_sampler_state(
583 struct pipe_context
*pctx
,
584 const struct pipe_sampler_state
*cso
)
586 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
587 struct panfrost_device
*device
= pan_device(pctx
->screen
);
591 if (device
->quirks
& IS_BIFROST
)
592 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
594 panfrost_sampler_desc_init(cso
, &so
->hw
);
600 panfrost_bind_sampler_states(
601 struct pipe_context
*pctx
,
602 enum pipe_shader_type shader
,
603 unsigned start_slot
, unsigned num_sampler
,
606 assert(start_slot
== 0);
608 struct panfrost_context
*ctx
= pan_context(pctx
);
610 /* XXX: Should upload, not just copy? */
611 ctx
->sampler_count
[shader
] = num_sampler
;
612 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
616 panfrost_variant_matches(
617 struct panfrost_context
*ctx
,
618 struct panfrost_shader_state
*variant
,
619 enum pipe_shader_type type
)
621 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
622 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
624 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
626 if (variant
->outputs_read
) {
627 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
630 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
631 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
633 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
634 fmt
= fb
->cbufs
[i
]->format
;
636 const struct util_format_description
*desc
=
637 util_format_description(fmt
);
639 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
640 fmt
= PIPE_FORMAT_NONE
;
642 if (variant
->rt_formats
[i
] != fmt
)
647 /* Point sprites TODO on bifrost, always pass */
648 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
649 variant
->point_sprite_mask
)
650 && !(dev
->quirks
& IS_BIFROST
)) {
651 /* Ensure the same varyings are turned to point sprites */
652 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
655 /* Ensure the orientation is correct */
657 rasterizer
->sprite_coord_mode
==
658 PIPE_SPRITE_COORD_UPPER_LEFT
;
660 if (variant
->point_sprite_upper_left
!= upper_left
)
664 /* Otherwise, we're good to go */
669 * Fix an uncompiled shader's stream output info, and produce a bitmask
670 * of which VARYING_SLOT_* are captured for stream output.
672 * Core Gallium stores output->register_index as a "slot" number, where
673 * slots are assigned consecutively to all outputs in info->outputs_written.
674 * This naive packing of outputs doesn't work for us - we too have slots,
675 * but the layout is defined by the VUE map, which we won't have until we
676 * compile a specific shader variant. So, we remap these and simply store
677 * VARYING_SLOT_* in our copy's output->register_index fields.
679 * We then produce a bitmask of outputs which are used for SO.
681 * Implementation from iris.
685 update_so_info(struct pipe_stream_output_info
*so_info
,
686 uint64_t outputs_written
)
688 uint64_t so_outputs
= 0;
689 uint8_t reverse_map
[64] = {0};
692 while (outputs_written
)
693 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
695 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
696 struct pipe_stream_output
*output
= &so_info
->output
[i
];
698 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
699 output
->register_index
= reverse_map
[output
->register_index
];
701 so_outputs
|= 1ull << output
->register_index
;
708 panfrost_bind_shader_state(
709 struct pipe_context
*pctx
,
711 enum pipe_shader_type type
)
713 struct panfrost_context
*ctx
= pan_context(pctx
);
714 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
715 ctx
->shader
[type
] = hwcso
;
719 /* Match the appropriate variant */
722 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
724 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
725 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
732 /* No variant matched, so create a new one */
733 variant
= variants
->variant_count
++;
735 if (variants
->variant_count
> variants
->variant_space
) {
736 unsigned old_space
= variants
->variant_space
;
738 variants
->variant_space
*= 2;
739 if (variants
->variant_space
== 0)
740 variants
->variant_space
= 1;
742 /* Arbitrary limit to stop runaway programs from
743 * creating an unbounded number of shader variants. */
744 assert(variants
->variant_space
< 1024);
746 unsigned msize
= sizeof(struct panfrost_shader_state
);
747 variants
->variants
= realloc(variants
->variants
,
748 variants
->variant_space
* msize
);
750 memset(&variants
->variants
[old_space
], 0,
751 (variants
->variant_space
- old_space
) * msize
);
754 struct panfrost_shader_state
*v
=
755 &variants
->variants
[variant
];
757 if (type
== PIPE_SHADER_FRAGMENT
) {
758 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
759 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
760 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
762 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
763 fmt
= fb
->cbufs
[i
]->format
;
765 const struct util_format_description
*desc
=
766 util_format_description(fmt
);
768 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
769 fmt
= PIPE_FORMAT_NONE
;
771 v
->rt_formats
[i
] = fmt
;
774 /* Point sprites are TODO on Bifrost */
775 if (ctx
->rasterizer
&& !(dev
->quirks
& IS_BIFROST
)) {
776 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
777 v
->point_sprite_upper_left
=
778 ctx
->rasterizer
->base
.sprite_coord_mode
==
779 PIPE_SPRITE_COORD_UPPER_LEFT
;
784 /* Select this variant */
785 variants
->active_variant
= variant
;
787 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
788 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
790 /* We finally have a variant, so compile it */
792 if (!shader_state
->compiled
) {
793 uint64_t outputs_written
= 0;
795 panfrost_shader_compile(ctx
, variants
->base
.type
,
796 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
797 variants
->base
.ir
.nir
:
798 variants
->base
.tokens
,
799 tgsi_processor_to_shader_stage(type
),
803 shader_state
->compiled
= true;
805 /* Fixup the stream out information, since what Gallium returns
806 * normally is mildly insane */
808 shader_state
->stream_output
= variants
->base
.stream_output
;
809 shader_state
->so_mask
=
810 update_so_info(&shader_state
->stream_output
, outputs_written
);
815 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
817 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
821 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
823 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
827 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
829 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
833 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
835 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
839 panfrost_set_vertex_buffers(
840 struct pipe_context
*pctx
,
842 unsigned num_buffers
,
843 const struct pipe_vertex_buffer
*buffers
)
845 struct panfrost_context
*ctx
= pan_context(pctx
);
847 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
851 panfrost_set_constant_buffer(
852 struct pipe_context
*pctx
,
853 enum pipe_shader_type shader
, uint index
,
854 const struct pipe_constant_buffer
*buf
)
856 struct panfrost_context
*ctx
= pan_context(pctx
);
857 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
859 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
861 unsigned mask
= (1 << index
);
863 if (unlikely(!buf
)) {
864 pbuf
->enabled_mask
&= ~mask
;
865 pbuf
->dirty_mask
&= ~mask
;
869 pbuf
->enabled_mask
|= mask
;
870 pbuf
->dirty_mask
|= mask
;
874 panfrost_set_stencil_ref(
875 struct pipe_context
*pctx
,
876 const struct pipe_stencil_ref
*ref
)
878 struct panfrost_context
*ctx
= pan_context(pctx
);
879 ctx
->stencil_ref
= *ref
;
883 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
884 struct pipe_context
*pctx
,
885 struct pipe_resource
*texture
)
887 struct panfrost_device
*device
= pan_device(pctx
->screen
);
888 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
889 enum pipe_format format
= so
->base
.format
;
892 /* Format to access the stencil portion of a Z32_S8 texture */
893 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
894 assert(prsrc
->separate_stencil
);
895 texture
= &prsrc
->separate_stencil
->base
;
896 prsrc
= (struct panfrost_resource
*)texture
;
897 format
= texture
->format
;
900 const struct util_format_description
*desc
= util_format_description(format
);
902 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
904 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
906 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
908 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
909 desc
= util_format_description(format
);
912 so
->texture_bo
= prsrc
->bo
->gpu
;
913 so
->modifier
= prsrc
->modifier
;
915 unsigned char user_swizzle
[4] = {
922 /* In the hardware, array_size refers specifically to array textures,
923 * whereas in Gallium, it also covers cubemaps */
925 unsigned array_size
= texture
->array_size
;
926 unsigned depth
= texture
->depth0
;
928 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
929 /* TODO: Cubemap arrays */
930 assert(array_size
== 6);
934 /* MSAA only supported for 2D textures (and 2D texture arrays via an
935 * extension currently unimplemented */
937 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
939 depth
= texture
->nr_samples
;
941 /* MSAA only supported for 2D textures */
942 assert(texture
->nr_samples
<= 1);
945 enum mali_texture_dimension type
=
946 panfrost_translate_texture_dimension(so
->base
.target
);
948 if (device
->quirks
& IS_BIFROST
) {
949 unsigned char composed_swizzle
[4];
950 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
952 unsigned size
= panfrost_estimate_texture_payload_size(
953 so
->base
.u
.tex
.first_level
,
954 so
->base
.u
.tex
.last_level
,
955 so
->base
.u
.tex
.first_layer
,
956 so
->base
.u
.tex
.last_layer
,
958 type
, prsrc
->modifier
);
960 so
->bo
= panfrost_bo_create(device
, size
, 0);
962 panfrost_new_texture_bifrost(
963 &so
->bifrost_descriptor
,
964 texture
->width0
, texture
->height0
,
967 type
, prsrc
->modifier
,
968 so
->base
.u
.tex
.first_level
,
969 so
->base
.u
.tex
.last_level
,
970 so
->base
.u
.tex
.first_layer
,
971 so
->base
.u
.tex
.last_layer
,
973 prsrc
->cubemap_stride
,
974 panfrost_translate_swizzle_4(composed_swizzle
),
979 unsigned size
= panfrost_estimate_texture_payload_size(
980 so
->base
.u
.tex
.first_level
,
981 so
->base
.u
.tex
.last_level
,
982 so
->base
.u
.tex
.first_layer
,
983 so
->base
.u
.tex
.last_layer
,
985 type
, prsrc
->modifier
);
986 size
+= MALI_MIDGARD_TEXTURE_LENGTH
;
988 so
->bo
= panfrost_bo_create(device
, size
, 0);
990 panfrost_new_texture(
992 texture
->width0
, texture
->height0
,
995 type
, prsrc
->modifier
,
996 so
->base
.u
.tex
.first_level
,
997 so
->base
.u
.tex
.last_level
,
998 so
->base
.u
.tex
.first_layer
,
999 so
->base
.u
.tex
.last_layer
,
1000 texture
->nr_samples
,
1001 prsrc
->cubemap_stride
,
1002 panfrost_translate_swizzle_4(user_swizzle
),
1008 static struct pipe_sampler_view
*
1009 panfrost_create_sampler_view(
1010 struct pipe_context
*pctx
,
1011 struct pipe_resource
*texture
,
1012 const struct pipe_sampler_view
*template)
1014 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
1016 pipe_reference(NULL
, &texture
->reference
);
1018 so
->base
= *template;
1019 so
->base
.texture
= texture
;
1020 so
->base
.reference
.count
= 1;
1021 so
->base
.context
= pctx
;
1023 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
1025 return (struct pipe_sampler_view
*) so
;
1029 panfrost_set_sampler_views(
1030 struct pipe_context
*pctx
,
1031 enum pipe_shader_type shader
,
1032 unsigned start_slot
, unsigned num_views
,
1033 struct pipe_sampler_view
**views
)
1035 struct panfrost_context
*ctx
= pan_context(pctx
);
1036 unsigned new_nr
= 0;
1039 assert(start_slot
== 0);
1041 for (i
= 0; i
< num_views
; ++i
) {
1044 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1048 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1049 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1052 ctx
->sampler_view_count
[shader
] = new_nr
;
1056 panfrost_sampler_view_destroy(
1057 struct pipe_context
*pctx
,
1058 struct pipe_sampler_view
*pview
)
1060 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1062 pipe_resource_reference(&pview
->texture
, NULL
);
1063 panfrost_bo_unreference(view
->bo
);
1068 panfrost_set_shader_buffers(
1069 struct pipe_context
*pctx
,
1070 enum pipe_shader_type shader
,
1071 unsigned start
, unsigned count
,
1072 const struct pipe_shader_buffer
*buffers
,
1073 unsigned writable_bitmask
)
1075 struct panfrost_context
*ctx
= pan_context(pctx
);
1077 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1078 buffers
, start
, count
);
1082 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1083 const struct pipe_framebuffer_state
*fb
)
1085 struct panfrost_context
*ctx
= pan_context(pctx
);
1087 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1090 /* We may need to generate a new variant if the fragment shader is
1091 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1092 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1094 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1095 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1098 static inline unsigned
1099 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1102 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1103 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1104 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1105 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1106 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1107 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1108 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1109 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1110 default: unreachable("Invalid stencil op");
1115 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1117 pan_pack(out
, STENCIL
, cfg
) {
1118 cfg
.mask
= in
->valuemask
;
1119 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1120 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1121 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1122 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1127 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1128 const struct pipe_depth_stencil_alpha_state
*zsa
)
1130 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1133 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1134 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1136 if (zsa
->stencil
[1].enabled
) {
1137 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1138 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1140 so
->stencil_back
= so
->stencil_front
;
1141 so
->stencil_mask_back
= so
->stencil_mask_front
;
1144 /* Alpha lowered by frontend */
1145 assert(!zsa
->alpha
.enabled
);
1147 /* TODO: Bounds test should be easy */
1148 assert(!zsa
->depth
.bounds_test
);
1154 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1157 struct panfrost_context
*ctx
= pan_context(pipe
);
1158 struct panfrost_zsa_state
*zsa
= cso
;
1159 ctx
->depth_stencil
= zsa
;
1163 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1169 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1170 unsigned sample_mask
)
1172 struct panfrost_context
*ctx
= pan_context(pipe
);
1173 ctx
->sample_mask
= sample_mask
;
1177 panfrost_set_min_samples(struct pipe_context
*pipe
,
1178 unsigned min_samples
)
1180 struct panfrost_context
*ctx
= pan_context(pipe
);
1181 ctx
->min_samples
= min_samples
;
1186 panfrost_set_clip_state(struct pipe_context
*pipe
,
1187 const struct pipe_clip_state
*clip
)
1189 //struct panfrost_context *panfrost = pan_context(pipe);
1193 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1194 unsigned start_slot
,
1195 unsigned num_viewports
,
1196 const struct pipe_viewport_state
*viewports
)
1198 struct panfrost_context
*ctx
= pan_context(pipe
);
1200 assert(start_slot
== 0);
1201 assert(num_viewports
== 1);
1203 ctx
->pipe_viewport
= *viewports
;
1207 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1208 unsigned start_slot
,
1209 unsigned num_scissors
,
1210 const struct pipe_scissor_state
*scissors
)
1212 struct panfrost_context
*ctx
= pan_context(pipe
);
1214 assert(start_slot
== 0);
1215 assert(num_scissors
== 1);
1217 ctx
->scissor
= *scissors
;
1221 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1222 const struct pipe_poly_stipple
*stipple
)
1224 //struct panfrost_context *panfrost = pan_context(pipe);
1228 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1231 struct panfrost_context
*ctx
= pan_context(pipe
);
1232 ctx
->active_queries
= enable
;
1236 panfrost_destroy(struct pipe_context
*pipe
)
1238 struct panfrost_context
*panfrost
= pan_context(pipe
);
1240 if (panfrost
->blitter
)
1241 util_blitter_destroy(panfrost
->blitter
);
1243 if (panfrost
->blitter_wallpaper
)
1244 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1246 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1247 u_upload_destroy(pipe
->stream_uploader
);
1248 u_upload_destroy(panfrost
->state_uploader
);
1253 static struct pipe_query
*
1254 panfrost_create_query(struct pipe_context
*pipe
,
1258 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1263 return (struct pipe_query
*) q
;
1267 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1269 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1272 panfrost_bo_unreference(query
->bo
);
1280 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1282 struct panfrost_context
*ctx
= pan_context(pipe
);
1283 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1285 switch (query
->type
) {
1286 case PIPE_QUERY_OCCLUSION_COUNTER
:
1287 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1288 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1289 /* Allocate a bo for the query results to be stored */
1291 query
->bo
= panfrost_bo_create(
1292 pan_device(ctx
->base
.screen
),
1293 sizeof(unsigned), 0);
1296 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1297 *result
= 0; /* Default to 0 if nothing at all drawn. */
1298 ctx
->occlusion_query
= query
;
1301 /* Geometry statistics are computed in the driver. XXX: geom/tess
1304 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1305 query
->start
= ctx
->prims_generated
;
1307 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1308 query
->start
= ctx
->tf_prims_generated
;
1312 /* TODO: timestamp queries, etc? */
1320 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1322 struct panfrost_context
*ctx
= pan_context(pipe
);
1323 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1325 switch (query
->type
) {
1326 case PIPE_QUERY_OCCLUSION_COUNTER
:
1327 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1328 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1329 ctx
->occlusion_query
= NULL
;
1331 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1332 query
->end
= ctx
->prims_generated
;
1334 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1335 query
->end
= ctx
->tf_prims_generated
;
1343 panfrost_get_query_result(struct pipe_context
*pipe
,
1344 struct pipe_query
*q
,
1346 union pipe_query_result
*vresult
)
1348 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1349 struct panfrost_context
*ctx
= pan_context(pipe
);
1352 switch (query
->type
) {
1353 case PIPE_QUERY_OCCLUSION_COUNTER
:
1354 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1355 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1356 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1357 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1359 /* Read back the query results */
1360 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1361 unsigned passed
= *result
;
1363 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1364 vresult
->u64
= passed
;
1366 vresult
->b
= !!passed
;
1371 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1372 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1373 panfrost_flush_all_batches(ctx
, 0);
1374 vresult
->u64
= query
->end
- query
->start
;
1378 /* TODO: more queries */
1385 static struct pipe_stream_output_target
*
1386 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1387 struct pipe_resource
*prsc
,
1388 unsigned buffer_offset
,
1389 unsigned buffer_size
)
1391 struct pipe_stream_output_target
*target
;
1393 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1398 pipe_reference_init(&target
->reference
, 1);
1399 pipe_resource_reference(&target
->buffer
, prsc
);
1401 target
->context
= pctx
;
1402 target
->buffer_offset
= buffer_offset
;
1403 target
->buffer_size
= buffer_size
;
1409 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1410 struct pipe_stream_output_target
*target
)
1412 pipe_resource_reference(&target
->buffer
, NULL
);
1413 ralloc_free(target
);
1417 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1418 unsigned num_targets
,
1419 struct pipe_stream_output_target
**targets
,
1420 const unsigned *offsets
)
1422 struct panfrost_context
*ctx
= pan_context(pctx
);
1423 struct panfrost_streamout
*so
= &ctx
->streamout
;
1425 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1427 for (unsigned i
= 0; i
< num_targets
; i
++) {
1428 if (offsets
[i
] != -1)
1429 so
->offsets
[i
] = offsets
[i
];
1431 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1434 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1435 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1437 so
->num_targets
= num_targets
;
1440 struct pipe_context
*
1441 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1443 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1444 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1445 struct panfrost_device
*dev
= pan_device(screen
);
1447 gallium
->screen
= screen
;
1449 gallium
->destroy
= panfrost_destroy
;
1451 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1453 gallium
->flush
= panfrost_flush
;
1454 gallium
->clear
= panfrost_clear
;
1455 gallium
->draw_vbo
= panfrost_draw_vbo
;
1456 gallium
->texture_barrier
= panfrost_texture_barrier
;
1458 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1459 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1460 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1462 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1464 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1465 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1466 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1468 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1469 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1470 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1472 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1473 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1474 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1476 gallium
->create_fs_state
= panfrost_create_fs_state
;
1477 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1478 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1480 gallium
->create_vs_state
= panfrost_create_vs_state
;
1481 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1482 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1484 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1485 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1486 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1488 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1489 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1490 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1492 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1493 gallium
->set_min_samples
= panfrost_set_min_samples
;
1495 gallium
->set_clip_state
= panfrost_set_clip_state
;
1496 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1497 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1498 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1499 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1501 gallium
->create_query
= panfrost_create_query
;
1502 gallium
->destroy_query
= panfrost_destroy_query
;
1503 gallium
->begin_query
= panfrost_begin_query
;
1504 gallium
->end_query
= panfrost_end_query
;
1505 gallium
->get_query_result
= panfrost_get_query_result
;
1507 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1508 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1509 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1511 panfrost_resource_context_init(gallium
);
1512 panfrost_blend_context_init(gallium
);
1513 panfrost_compute_context_init(gallium
);
1515 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1516 gallium
->const_uploader
= gallium
->stream_uploader
;
1518 ctx
->state_uploader
= u_upload_create(gallium
, 4096,
1519 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_DYNAMIC
, 0);
1521 /* All of our GPUs support ES mode. Midgard supports additionally
1522 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1524 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1526 if (!(dev
->quirks
& IS_BIFROST
)) {
1527 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1528 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1531 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1533 ctx
->blitter
= util_blitter_create(gallium
);
1534 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1536 assert(ctx
->blitter
);
1537 assert(ctx
->blitter_wallpaper
);
1539 /* Prepare for render! */
1541 panfrost_batch_init(ctx
);
1543 if (!(dev
->quirks
& IS_BIFROST
)) {
1544 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1545 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1548 /* By default mask everything on */
1549 ctx
->sample_mask
= ~0;
1550 ctx
->active_queries
= true;