2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
85 t
.heap_start
= device
->tiler_heap
->gpu
;
86 t
.heap_end
= device
->tiler_heap
->gpu
+ device
->tiler_heap
->size
;
88 struct panfrost_bo
*tiler_dummy
;
90 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
91 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t
.heap_start
= tiler_dummy
->gpu
;
95 t
.heap_end
= t
.heap_start
;
97 /* Use a dummy polygon list */
98 t
.polygon_list
= tiler_dummy
->gpu
;
100 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
104 t
.hierarchy_mask
= MALI_TILER_USER
;
105 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
109 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
113 t
.polygon_list_body
=
114 t
.polygon_list
+ header_size
;
121 struct pipe_context
*pipe
,
123 const struct pipe_scissor_state
*scissor_state
,
124 const union pipe_color_union
*color
,
125 double depth
, unsigned stencil
)
127 struct panfrost_context
*ctx
= pan_context(pipe
);
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
135 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
136 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
140 panfrost_writes_point_size(struct panfrost_context
*ctx
)
142 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
143 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
145 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
148 /* The entire frame is in memory -- send it off to the kernel! */
152 struct pipe_context
*pipe
,
153 struct pipe_fence_handle
**fence
,
156 struct panfrost_context
*ctx
= pan_context(pipe
);
157 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
158 uint32_t syncobj
= 0;
161 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
163 /* Submit all pending jobs */
164 panfrost_flush_all_batches(ctx
, syncobj
);
167 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
168 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
169 *fence
= (struct pipe_fence_handle
*)f
;
172 if (dev
->debug
& PAN_DBG_TRACE
)
173 pandecode_next_frame();
177 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
179 struct panfrost_context
*ctx
= pan_context(pipe
);
180 panfrost_flush_all_batches(ctx
, 0);
183 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
186 pan_draw_mode(enum pipe_prim_type mode
)
191 DEFINE_CASE(LINE_LOOP
);
192 DEFINE_CASE(LINE_STRIP
);
193 DEFINE_CASE(TRIANGLES
);
194 DEFINE_CASE(TRIANGLE_STRIP
);
195 DEFINE_CASE(TRIANGLE_FAN
);
197 DEFINE_CASE(QUAD_STRIP
);
198 DEFINE_CASE(POLYGON
);
201 unreachable("Invalid draw mode");
208 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
210 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
212 /* Check if we're scissoring at all */
214 if (!ctx
->rasterizer
->base
.scissor
)
217 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
220 /* Count generated primitives (when there is no geom/tess shaders) for
221 * transform feedback */
224 panfrost_statistics_record(
225 struct panfrost_context
*ctx
,
226 const struct pipe_draw_info
*info
)
228 if (!ctx
->active_queries
)
231 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
232 ctx
->prims_generated
+= prims
;
234 if (!ctx
->streamout
.num_targets
)
237 ctx
->tf_prims_generated
+= prims
;
241 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
243 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
246 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
248 ctx
->streamout
.offsets
[i
] += count
;
254 struct pipe_context
*pipe
,
255 const struct pipe_draw_info
*info
)
257 struct panfrost_context
*ctx
= pan_context(pipe
);
258 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
260 /* First of all, check the scissor to see if anything is drawn at all.
261 * If it's not, we drop the draw (mostly a conformance issue;
262 * well-behaved apps shouldn't hit this) */
264 if (panfrost_scissor_culls_everything(ctx
))
267 int mode
= info
->mode
;
269 /* Fallback unsupported restart index */
270 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
272 if (info
->primitive_restart
&& info
->index_size
273 && info
->restart_index
!= primitive_index
) {
274 util_draw_vbo_without_prim_restart(pipe
, info
);
278 /* Fallback for unsupported modes */
280 assert(ctx
->rasterizer
!= NULL
);
282 if (!(ctx
->draw_modes
& (1 << mode
))) {
283 if (info
->count
< 4) {
284 /* Degenerate case? */
288 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
289 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
293 /* Now that we have a guaranteed terminating path, find the job. */
295 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
296 panfrost_batch_set_requirements(batch
);
298 /* Take into account a negative bias */
299 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
300 ctx
->instance_count
= info
->instance_count
;
301 ctx
->active_prim
= info
->mode
;
303 struct mali_vertex_tiler_prefix vertex_prefix
= { 0 }, tiler_prefix
= { 0 };
304 struct mali_vertex_tiler_postfix vertex_postfix
= { 0 }, tiler_postfix
= { 0 };
305 union midgard_primitive_size primitive_size
;
306 unsigned vertex_count
;
308 if (device
->quirks
& IS_BIFROST
) {
309 vertex_postfix
.gl_enables
= 0x2;
310 tiler_postfix
.gl_enables
= 0x3;
311 vertex_postfix
.shared_memory
= panfrost_vt_emit_shared_memory(batch
);
313 vertex_postfix
.gl_enables
= 0x6;
314 tiler_postfix
.gl_enables
= 0x7;
315 vertex_postfix
.shared_memory
= panfrost_batch_reserve_framebuffer(batch
);
318 tiler_postfix
.shared_memory
= vertex_postfix
.shared_memory
;
320 if (ctx
->occlusion_query
) {
321 tiler_postfix
.gl_enables
|= MALI_OCCLUSION_QUERY
;
322 tiler_postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
323 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
324 PAN_BO_ACCESS_SHARED
|
326 PAN_BO_ACCESS_FRAGMENT
);
329 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
330 SET_BIT(tiler_postfix
.gl_enables
, MALI_FRONT_CCW_TOP
,
332 SET_BIT(tiler_postfix
.gl_enables
, MALI_CULL_FACE_FRONT
,
333 (rast
->cull_face
& PIPE_FACE_FRONT
));
334 SET_BIT(tiler_postfix
.gl_enables
, MALI_CULL_FACE_BACK
,
335 (rast
->cull_face
& PIPE_FACE_BACK
));
336 SET_BIT(tiler_prefix
.unknown_draw
, MALI_DRAW_FLATSHADE_FIRST
,
337 rast
->flatshade_first
);
339 tiler_prefix
.draw_mode
= pan_draw_mode(mode
);
341 unsigned draw_flags
= 0x3000;
343 if (panfrost_writes_point_size(ctx
))
344 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
346 if (info
->primitive_restart
)
347 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
349 if (info
->index_size
) {
350 unsigned min_index
= 0, max_index
= 0;
352 tiler_prefix
.indices
= panfrost_get_index_buffer_bounded(ctx
,
357 /* Use the corresponding values */
358 vertex_count
= max_index
- min_index
+ 1;
359 tiler_postfix
.offset_start
= vertex_postfix
.offset_start
= min_index
+ info
->index_bias
;
360 tiler_prefix
.offset_bias_correction
= -min_index
;
361 tiler_prefix
.index_count
= MALI_POSITIVE(info
->count
);
362 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
364 vertex_count
= ctx
->vertex_count
;
365 tiler_postfix
.offset_start
= vertex_postfix
.offset_start
= info
->start
;
366 tiler_prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
369 tiler_prefix
.unknown_draw
= draw_flags
;
370 ctx
->offset_start
= vertex_postfix
.offset_start
;
372 /* Encode the padded vertex count */
374 if (info
->instance_count
> 1) {
375 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
377 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
378 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
380 tiler_postfix
.instance_shift
= vertex_postfix
.instance_shift
= shift
;
381 tiler_postfix
.instance_odd
= vertex_postfix
.instance_odd
= k
;
383 ctx
->padded_count
= vertex_count
;
386 panfrost_statistics_record(ctx
, info
);
388 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
389 1, vertex_count
, info
->instance_count
,
392 /* Emit all sort of descriptors. */
393 mali_ptr push_vert
= 0, push_frag
= 0, attribs
= 0;
394 mali_ptr varyings
= 0, vs_vary
= 0, fs_vary
= 0, pos
= 0, psiz
= 0;
396 vertex_postfix
.attribute_meta
= panfrost_emit_vertex_data(batch
, &attribs
);
397 vertex_postfix
.attributes
= attribs
;
398 panfrost_emit_varying_descriptor(batch
,
401 &vs_vary
, &fs_vary
, &varyings
,
403 vertex_postfix
.varyings
= varyings
;
404 tiler_postfix
.varyings
= varyings
;
405 vertex_postfix
.varying_meta
= vs_vary
;
406 tiler_postfix
.varying_meta
= fs_vary
;
407 tiler_postfix
.position_varying
= pos
;
408 vertex_postfix
.sampler_descriptor
= panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_VERTEX
);
409 tiler_postfix
.sampler_descriptor
= panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_FRAGMENT
);
410 vertex_postfix
.textures
= panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_VERTEX
);
411 tiler_postfix
.textures
= panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_FRAGMENT
);
412 vertex_postfix
.uniform_buffers
= panfrost_emit_const_buf(batch
, PIPE_SHADER_VERTEX
, &push_vert
);
413 tiler_postfix
.uniform_buffers
= panfrost_emit_const_buf(batch
, PIPE_SHADER_FRAGMENT
, &push_frag
);
414 vertex_postfix
.uniforms
= push_vert
;
415 tiler_postfix
.uniforms
= push_frag
;
416 tiler_postfix
.viewport
= panfrost_emit_viewport(batch
);
418 vertex_postfix
.shader
= panfrost_emit_compute_shader_meta(batch
, PIPE_SHADER_VERTEX
);
419 tiler_postfix
.shader
= panfrost_emit_frag_shader_meta(batch
);
421 primitive_size
.pointer
= psiz
;
422 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
424 /* Fire off the draw itself */
425 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
426 &tiler_prefix
, &tiler_postfix
,
429 /* Adjust the batch stack size based on the new shader stack sizes. */
430 panfrost_batch_adjust_stack_size(batch
);
432 /* Increment transform feedback offsets */
433 panfrost_update_streamout_offsets(ctx
);
439 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
445 panfrost_create_rasterizer_state(
446 struct pipe_context
*pctx
,
447 const struct pipe_rasterizer_state
*cso
)
449 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
453 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
454 assert(cso
->offset_clamp
== 0.0);
460 panfrost_bind_rasterizer_state(
461 struct pipe_context
*pctx
,
464 struct panfrost_context
*ctx
= pan_context(pctx
);
466 ctx
->rasterizer
= hwcso
;
471 /* Point sprites are emulated */
473 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
475 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
476 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
480 panfrost_create_vertex_elements_state(
481 struct pipe_context
*pctx
,
482 unsigned num_elements
,
483 const struct pipe_vertex_element
*elements
)
485 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
486 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
488 so
->num_elements
= num_elements
;
489 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
491 for (int i
= 0; i
< num_elements
; ++i
) {
492 enum pipe_format fmt
= elements
[i
].src_format
;
493 const struct util_format_description
*desc
= util_format_description(fmt
);
494 unsigned swizzle
= 0;
495 if (dev
->quirks
& HAS_SWIZZLES
)
496 swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
498 swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
500 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
501 so
->formats
[i
] = (hw_format
<< 12) | swizzle
;
505 /* Let's also prepare vertex builtins */
506 if (dev
->quirks
& HAS_SWIZZLES
)
507 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
509 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
511 if (dev
->quirks
& HAS_SWIZZLES
)
512 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
514 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
520 panfrost_bind_vertex_elements_state(
521 struct pipe_context
*pctx
,
524 struct panfrost_context
*ctx
= pan_context(pctx
);
529 panfrost_create_shader_state(
530 struct pipe_context
*pctx
,
531 const struct pipe_shader_state
*cso
,
532 enum pipe_shader_type stage
)
534 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
535 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
538 /* Token deep copy to prevent memory corruption */
540 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
541 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
543 /* Precompile for shader-db if we need to */
544 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
545 struct panfrost_context
*ctx
= pan_context(pctx
);
547 struct panfrost_shader_state state
= { 0 };
548 uint64_t outputs_written
;
550 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
552 tgsi_processor_to_shader_stage(stage
),
553 &state
, &outputs_written
);
560 panfrost_delete_shader_state(
561 struct pipe_context
*pctx
,
564 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
566 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
567 /* TODO: leaks TGSI tokens! */
570 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
571 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
572 panfrost_bo_unreference(shader_state
->bo
);
574 if (shader_state
->upload
.rsrc
)
575 pipe_resource_reference(&shader_state
->upload
.rsrc
, NULL
);
577 shader_state
->bo
= NULL
;
586 panfrost_create_sampler_state(
587 struct pipe_context
*pctx
,
588 const struct pipe_sampler_state
*cso
)
590 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
591 struct panfrost_device
*device
= pan_device(pctx
->screen
);
595 if (device
->quirks
& IS_BIFROST
)
596 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
598 panfrost_sampler_desc_init(cso
, &so
->hw
);
604 panfrost_bind_sampler_states(
605 struct pipe_context
*pctx
,
606 enum pipe_shader_type shader
,
607 unsigned start_slot
, unsigned num_sampler
,
610 assert(start_slot
== 0);
612 struct panfrost_context
*ctx
= pan_context(pctx
);
614 /* XXX: Should upload, not just copy? */
615 ctx
->sampler_count
[shader
] = num_sampler
;
616 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
620 panfrost_variant_matches(
621 struct panfrost_context
*ctx
,
622 struct panfrost_shader_state
*variant
,
623 enum pipe_shader_type type
)
625 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
626 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
628 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
630 if (variant
->outputs_read
) {
631 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
634 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
635 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
637 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
638 fmt
= fb
->cbufs
[i
]->format
;
640 const struct util_format_description
*desc
=
641 util_format_description(fmt
);
643 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
644 fmt
= PIPE_FORMAT_NONE
;
646 if (variant
->rt_formats
[i
] != fmt
)
651 /* Point sprites TODO on bifrost, always pass */
652 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
653 variant
->point_sprite_mask
)
654 && !(dev
->quirks
& IS_BIFROST
)) {
655 /* Ensure the same varyings are turned to point sprites */
656 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
659 /* Ensure the orientation is correct */
661 rasterizer
->sprite_coord_mode
==
662 PIPE_SPRITE_COORD_UPPER_LEFT
;
664 if (variant
->point_sprite_upper_left
!= upper_left
)
668 /* Otherwise, we're good to go */
673 * Fix an uncompiled shader's stream output info, and produce a bitmask
674 * of which VARYING_SLOT_* are captured for stream output.
676 * Core Gallium stores output->register_index as a "slot" number, where
677 * slots are assigned consecutively to all outputs in info->outputs_written.
678 * This naive packing of outputs doesn't work for us - we too have slots,
679 * but the layout is defined by the VUE map, which we won't have until we
680 * compile a specific shader variant. So, we remap these and simply store
681 * VARYING_SLOT_* in our copy's output->register_index fields.
683 * We then produce a bitmask of outputs which are used for SO.
685 * Implementation from iris.
689 update_so_info(struct pipe_stream_output_info
*so_info
,
690 uint64_t outputs_written
)
692 uint64_t so_outputs
= 0;
693 uint8_t reverse_map
[64] = {0};
696 while (outputs_written
)
697 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
699 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
700 struct pipe_stream_output
*output
= &so_info
->output
[i
];
702 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
703 output
->register_index
= reverse_map
[output
->register_index
];
705 so_outputs
|= 1ull << output
->register_index
;
712 panfrost_bind_shader_state(
713 struct pipe_context
*pctx
,
715 enum pipe_shader_type type
)
717 struct panfrost_context
*ctx
= pan_context(pctx
);
718 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
719 ctx
->shader
[type
] = hwcso
;
723 /* Match the appropriate variant */
726 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
728 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
729 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
736 /* No variant matched, so create a new one */
737 variant
= variants
->variant_count
++;
739 if (variants
->variant_count
> variants
->variant_space
) {
740 unsigned old_space
= variants
->variant_space
;
742 variants
->variant_space
*= 2;
743 if (variants
->variant_space
== 0)
744 variants
->variant_space
= 1;
746 /* Arbitrary limit to stop runaway programs from
747 * creating an unbounded number of shader variants. */
748 assert(variants
->variant_space
< 1024);
750 unsigned msize
= sizeof(struct panfrost_shader_state
);
751 variants
->variants
= realloc(variants
->variants
,
752 variants
->variant_space
* msize
);
754 memset(&variants
->variants
[old_space
], 0,
755 (variants
->variant_space
- old_space
) * msize
);
758 struct panfrost_shader_state
*v
=
759 &variants
->variants
[variant
];
761 if (type
== PIPE_SHADER_FRAGMENT
) {
762 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
763 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
764 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
766 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
767 fmt
= fb
->cbufs
[i
]->format
;
769 const struct util_format_description
*desc
=
770 util_format_description(fmt
);
772 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
773 fmt
= PIPE_FORMAT_NONE
;
775 v
->rt_formats
[i
] = fmt
;
778 /* Point sprites are TODO on Bifrost */
779 if (ctx
->rasterizer
&& !(dev
->quirks
& IS_BIFROST
)) {
780 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
781 v
->point_sprite_upper_left
=
782 ctx
->rasterizer
->base
.sprite_coord_mode
==
783 PIPE_SPRITE_COORD_UPPER_LEFT
;
788 /* Select this variant */
789 variants
->active_variant
= variant
;
791 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
792 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
794 /* We finally have a variant, so compile it */
796 if (!shader_state
->compiled
) {
797 uint64_t outputs_written
= 0;
799 panfrost_shader_compile(ctx
, variants
->base
.type
,
800 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
801 variants
->base
.ir
.nir
:
802 variants
->base
.tokens
,
803 tgsi_processor_to_shader_stage(type
),
807 shader_state
->compiled
= true;
809 /* Fixup the stream out information, since what Gallium returns
810 * normally is mildly insane */
812 shader_state
->stream_output
= variants
->base
.stream_output
;
813 shader_state
->so_mask
=
814 update_so_info(&shader_state
->stream_output
, outputs_written
);
819 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
821 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
825 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
827 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
831 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
833 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
837 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
839 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
843 panfrost_set_vertex_buffers(
844 struct pipe_context
*pctx
,
846 unsigned num_buffers
,
847 const struct pipe_vertex_buffer
*buffers
)
849 struct panfrost_context
*ctx
= pan_context(pctx
);
851 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
855 panfrost_set_constant_buffer(
856 struct pipe_context
*pctx
,
857 enum pipe_shader_type shader
, uint index
,
858 const struct pipe_constant_buffer
*buf
)
860 struct panfrost_context
*ctx
= pan_context(pctx
);
861 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
863 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
865 unsigned mask
= (1 << index
);
867 if (unlikely(!buf
)) {
868 pbuf
->enabled_mask
&= ~mask
;
869 pbuf
->dirty_mask
&= ~mask
;
873 pbuf
->enabled_mask
|= mask
;
874 pbuf
->dirty_mask
|= mask
;
878 panfrost_set_stencil_ref(
879 struct pipe_context
*pctx
,
880 const struct pipe_stencil_ref
*ref
)
882 struct panfrost_context
*ctx
= pan_context(pctx
);
883 ctx
->stencil_ref
= *ref
;
887 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
888 struct pipe_context
*pctx
,
889 struct pipe_resource
*texture
)
891 struct panfrost_device
*device
= pan_device(pctx
->screen
);
892 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
893 enum pipe_format format
= so
->base
.format
;
896 /* Format to access the stencil portion of a Z32_S8 texture */
897 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
898 assert(prsrc
->separate_stencil
);
899 texture
= &prsrc
->separate_stencil
->base
;
900 prsrc
= (struct panfrost_resource
*)texture
;
901 format
= texture
->format
;
904 const struct util_format_description
*desc
= util_format_description(format
);
906 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
908 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
910 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
912 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
913 desc
= util_format_description(format
);
916 so
->texture_bo
= prsrc
->bo
->gpu
;
917 so
->modifier
= prsrc
->modifier
;
919 unsigned char user_swizzle
[4] = {
926 /* In the hardware, array_size refers specifically to array textures,
927 * whereas in Gallium, it also covers cubemaps */
929 unsigned array_size
= texture
->array_size
;
930 unsigned depth
= texture
->depth0
;
932 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
933 /* TODO: Cubemap arrays */
934 assert(array_size
== 6);
938 /* MSAA only supported for 2D textures (and 2D texture arrays via an
939 * extension currently unimplemented */
941 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
943 depth
= texture
->nr_samples
;
945 /* MSAA only supported for 2D textures */
946 assert(texture
->nr_samples
<= 1);
949 enum mali_texture_dimension type
=
950 panfrost_translate_texture_dimension(so
->base
.target
);
952 if (device
->quirks
& IS_BIFROST
) {
953 unsigned char composed_swizzle
[4];
954 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
956 unsigned size
= panfrost_estimate_texture_payload_size(
957 so
->base
.u
.tex
.first_level
,
958 so
->base
.u
.tex
.last_level
,
959 so
->base
.u
.tex
.first_layer
,
960 so
->base
.u
.tex
.last_layer
,
962 type
, prsrc
->modifier
);
964 so
->bo
= panfrost_bo_create(device
, size
, 0);
966 panfrost_new_texture_bifrost(
967 &so
->bifrost_descriptor
,
968 texture
->width0
, texture
->height0
,
971 type
, prsrc
->modifier
,
972 so
->base
.u
.tex
.first_level
,
973 so
->base
.u
.tex
.last_level
,
974 so
->base
.u
.tex
.first_layer
,
975 so
->base
.u
.tex
.last_layer
,
977 prsrc
->cubemap_stride
,
978 panfrost_translate_swizzle_4(composed_swizzle
),
983 unsigned size
= panfrost_estimate_texture_payload_size(
984 so
->base
.u
.tex
.first_level
,
985 so
->base
.u
.tex
.last_level
,
986 so
->base
.u
.tex
.first_layer
,
987 so
->base
.u
.tex
.last_layer
,
989 type
, prsrc
->modifier
);
990 size
+= MALI_MIDGARD_TEXTURE_LENGTH
;
992 so
->bo
= panfrost_bo_create(device
, size
, 0);
994 panfrost_new_texture(
996 texture
->width0
, texture
->height0
,
999 type
, prsrc
->modifier
,
1000 so
->base
.u
.tex
.first_level
,
1001 so
->base
.u
.tex
.last_level
,
1002 so
->base
.u
.tex
.first_layer
,
1003 so
->base
.u
.tex
.last_layer
,
1004 texture
->nr_samples
,
1005 prsrc
->cubemap_stride
,
1006 panfrost_translate_swizzle_4(user_swizzle
),
1012 static struct pipe_sampler_view
*
1013 panfrost_create_sampler_view(
1014 struct pipe_context
*pctx
,
1015 struct pipe_resource
*texture
,
1016 const struct pipe_sampler_view
*template)
1018 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
1020 pipe_reference(NULL
, &texture
->reference
);
1022 so
->base
= *template;
1023 so
->base
.texture
= texture
;
1024 so
->base
.reference
.count
= 1;
1025 so
->base
.context
= pctx
;
1027 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
1029 return (struct pipe_sampler_view
*) so
;
1033 panfrost_set_sampler_views(
1034 struct pipe_context
*pctx
,
1035 enum pipe_shader_type shader
,
1036 unsigned start_slot
, unsigned num_views
,
1037 struct pipe_sampler_view
**views
)
1039 struct panfrost_context
*ctx
= pan_context(pctx
);
1040 unsigned new_nr
= 0;
1043 assert(start_slot
== 0);
1045 for (i
= 0; i
< num_views
; ++i
) {
1048 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1052 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1053 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1056 ctx
->sampler_view_count
[shader
] = new_nr
;
1060 panfrost_sampler_view_destroy(
1061 struct pipe_context
*pctx
,
1062 struct pipe_sampler_view
*pview
)
1064 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1066 pipe_resource_reference(&pview
->texture
, NULL
);
1067 panfrost_bo_unreference(view
->bo
);
1072 panfrost_set_shader_buffers(
1073 struct pipe_context
*pctx
,
1074 enum pipe_shader_type shader
,
1075 unsigned start
, unsigned count
,
1076 const struct pipe_shader_buffer
*buffers
,
1077 unsigned writable_bitmask
)
1079 struct panfrost_context
*ctx
= pan_context(pctx
);
1081 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1082 buffers
, start
, count
);
1086 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1087 const struct pipe_framebuffer_state
*fb
)
1089 struct panfrost_context
*ctx
= pan_context(pctx
);
1091 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1094 /* We may need to generate a new variant if the fragment shader is
1095 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1096 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1098 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1099 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1102 static inline unsigned
1103 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1106 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1107 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1108 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1109 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1110 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1111 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1112 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1113 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1114 default: unreachable("Invalid stencil op");
1119 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1121 pan_pack(out
, STENCIL
, cfg
) {
1122 cfg
.mask
= in
->valuemask
;
1123 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1124 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1125 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1126 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1131 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1132 const struct pipe_depth_stencil_alpha_state
*zsa
)
1134 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1137 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1138 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1140 if (zsa
->stencil
[1].enabled
) {
1141 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1142 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1144 so
->stencil_back
= so
->stencil_front
;
1145 so
->stencil_mask_back
= so
->stencil_mask_front
;
1148 /* Alpha lowered by frontend */
1149 assert(!zsa
->alpha
.enabled
);
1151 /* TODO: Bounds test should be easy */
1152 assert(!zsa
->depth
.bounds_test
);
1158 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1161 struct panfrost_context
*ctx
= pan_context(pipe
);
1162 struct panfrost_zsa_state
*zsa
= cso
;
1163 ctx
->depth_stencil
= zsa
;
1167 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1173 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1174 unsigned sample_mask
)
1176 struct panfrost_context
*ctx
= pan_context(pipe
);
1177 ctx
->sample_mask
= sample_mask
;
1181 panfrost_set_min_samples(struct pipe_context
*pipe
,
1182 unsigned min_samples
)
1184 struct panfrost_context
*ctx
= pan_context(pipe
);
1185 ctx
->min_samples
= min_samples
;
1190 panfrost_set_clip_state(struct pipe_context
*pipe
,
1191 const struct pipe_clip_state
*clip
)
1193 //struct panfrost_context *panfrost = pan_context(pipe);
1197 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1198 unsigned start_slot
,
1199 unsigned num_viewports
,
1200 const struct pipe_viewport_state
*viewports
)
1202 struct panfrost_context
*ctx
= pan_context(pipe
);
1204 assert(start_slot
== 0);
1205 assert(num_viewports
== 1);
1207 ctx
->pipe_viewport
= *viewports
;
1211 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1212 unsigned start_slot
,
1213 unsigned num_scissors
,
1214 const struct pipe_scissor_state
*scissors
)
1216 struct panfrost_context
*ctx
= pan_context(pipe
);
1218 assert(start_slot
== 0);
1219 assert(num_scissors
== 1);
1221 ctx
->scissor
= *scissors
;
1225 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1226 const struct pipe_poly_stipple
*stipple
)
1228 //struct panfrost_context *panfrost = pan_context(pipe);
1232 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1235 struct panfrost_context
*ctx
= pan_context(pipe
);
1236 ctx
->active_queries
= enable
;
1240 panfrost_destroy(struct pipe_context
*pipe
)
1242 struct panfrost_context
*panfrost
= pan_context(pipe
);
1244 if (panfrost
->blitter
)
1245 util_blitter_destroy(panfrost
->blitter
);
1247 if (panfrost
->blitter_wallpaper
)
1248 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1250 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1251 u_upload_destroy(pipe
->stream_uploader
);
1252 u_upload_destroy(panfrost
->state_uploader
);
1257 static struct pipe_query
*
1258 panfrost_create_query(struct pipe_context
*pipe
,
1262 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1267 return (struct pipe_query
*) q
;
1271 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1273 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1276 panfrost_bo_unreference(query
->bo
);
1284 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1286 struct panfrost_context
*ctx
= pan_context(pipe
);
1287 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1289 switch (query
->type
) {
1290 case PIPE_QUERY_OCCLUSION_COUNTER
:
1291 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1292 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1293 /* Allocate a bo for the query results to be stored */
1295 query
->bo
= panfrost_bo_create(
1296 pan_device(ctx
->base
.screen
),
1297 sizeof(unsigned), 0);
1300 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1301 *result
= 0; /* Default to 0 if nothing at all drawn. */
1302 ctx
->occlusion_query
= query
;
1305 /* Geometry statistics are computed in the driver. XXX: geom/tess
1308 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1309 query
->start
= ctx
->prims_generated
;
1311 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1312 query
->start
= ctx
->tf_prims_generated
;
1316 /* TODO: timestamp queries, etc? */
1324 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1326 struct panfrost_context
*ctx
= pan_context(pipe
);
1327 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1329 switch (query
->type
) {
1330 case PIPE_QUERY_OCCLUSION_COUNTER
:
1331 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1332 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1333 ctx
->occlusion_query
= NULL
;
1335 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1336 query
->end
= ctx
->prims_generated
;
1338 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1339 query
->end
= ctx
->tf_prims_generated
;
1347 panfrost_get_query_result(struct pipe_context
*pipe
,
1348 struct pipe_query
*q
,
1350 union pipe_query_result
*vresult
)
1352 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1353 struct panfrost_context
*ctx
= pan_context(pipe
);
1356 switch (query
->type
) {
1357 case PIPE_QUERY_OCCLUSION_COUNTER
:
1358 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1359 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1360 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1361 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1363 /* Read back the query results */
1364 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1365 unsigned passed
= *result
;
1367 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1368 vresult
->u64
= passed
;
1370 vresult
->b
= !!passed
;
1375 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1376 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1377 panfrost_flush_all_batches(ctx
, 0);
1378 vresult
->u64
= query
->end
- query
->start
;
1382 /* TODO: more queries */
1389 static struct pipe_stream_output_target
*
1390 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1391 struct pipe_resource
*prsc
,
1392 unsigned buffer_offset
,
1393 unsigned buffer_size
)
1395 struct pipe_stream_output_target
*target
;
1397 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1402 pipe_reference_init(&target
->reference
, 1);
1403 pipe_resource_reference(&target
->buffer
, prsc
);
1405 target
->context
= pctx
;
1406 target
->buffer_offset
= buffer_offset
;
1407 target
->buffer_size
= buffer_size
;
1413 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1414 struct pipe_stream_output_target
*target
)
1416 pipe_resource_reference(&target
->buffer
, NULL
);
1417 ralloc_free(target
);
1421 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1422 unsigned num_targets
,
1423 struct pipe_stream_output_target
**targets
,
1424 const unsigned *offsets
)
1426 struct panfrost_context
*ctx
= pan_context(pctx
);
1427 struct panfrost_streamout
*so
= &ctx
->streamout
;
1429 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1431 for (unsigned i
= 0; i
< num_targets
; i
++) {
1432 if (offsets
[i
] != -1)
1433 so
->offsets
[i
] = offsets
[i
];
1435 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1438 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1439 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1441 so
->num_targets
= num_targets
;
1444 struct pipe_context
*
1445 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1447 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1448 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1449 struct panfrost_device
*dev
= pan_device(screen
);
1451 gallium
->screen
= screen
;
1453 gallium
->destroy
= panfrost_destroy
;
1455 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1457 gallium
->flush
= panfrost_flush
;
1458 gallium
->clear
= panfrost_clear
;
1459 gallium
->draw_vbo
= panfrost_draw_vbo
;
1460 gallium
->texture_barrier
= panfrost_texture_barrier
;
1462 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1463 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1464 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1466 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1468 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1469 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1470 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1472 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1473 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1474 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1476 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1477 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1478 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1480 gallium
->create_fs_state
= panfrost_create_fs_state
;
1481 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1482 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1484 gallium
->create_vs_state
= panfrost_create_vs_state
;
1485 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1486 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1488 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1489 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1490 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1492 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1493 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1494 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1496 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1497 gallium
->set_min_samples
= panfrost_set_min_samples
;
1499 gallium
->set_clip_state
= panfrost_set_clip_state
;
1500 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1501 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1502 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1503 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1505 gallium
->create_query
= panfrost_create_query
;
1506 gallium
->destroy_query
= panfrost_destroy_query
;
1507 gallium
->begin_query
= panfrost_begin_query
;
1508 gallium
->end_query
= panfrost_end_query
;
1509 gallium
->get_query_result
= panfrost_get_query_result
;
1511 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1512 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1513 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1515 panfrost_resource_context_init(gallium
);
1516 panfrost_blend_context_init(gallium
);
1517 panfrost_compute_context_init(gallium
);
1519 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1520 gallium
->const_uploader
= gallium
->stream_uploader
;
1522 ctx
->state_uploader
= u_upload_create(gallium
, 4096,
1523 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_DYNAMIC
, 0);
1525 /* All of our GPUs support ES mode. Midgard supports additionally
1526 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1528 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1530 if (!(dev
->quirks
& IS_BIFROST
)) {
1531 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1532 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1535 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1537 ctx
->blitter
= util_blitter_create(gallium
);
1538 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1540 assert(ctx
->blitter
);
1541 assert(ctx
->blitter_wallpaper
);
1543 /* Prepare for render! */
1545 panfrost_batch_init(ctx
);
1547 if (!(dev
->quirks
& IS_BIFROST
)) {
1548 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1549 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1552 /* By default mask everything on */
1553 ctx
->sample_mask
= ~0;
1554 ctx
->active_queries
= true;