2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
82 struct panfrost_bo
*tiler_heap
;
84 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
85 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
90 /* Allow the entire tiler heap */
91 t
.heap_start
= tiler_heap
->gpu
;
92 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
94 struct panfrost_bo
*tiler_dummy
;
96 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
97 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
99 /* The tiler is disabled, so don't allow the tiler heap */
100 t
.heap_start
= tiler_dummy
->gpu
;
101 t
.heap_end
= t
.heap_start
;
103 /* Use a dummy polygon list */
104 t
.polygon_list
= tiler_dummy
->gpu
;
106 /* Disable the tiler */
108 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
110 t
.hierarchy_mask
= MALI_TILER_USER
;
111 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
113 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
114 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
115 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
119 t
.polygon_list_body
=
120 t
.polygon_list
+ header_size
;
127 struct pipe_context
*pipe
,
129 const struct pipe_scissor_state
*scissor_state
,
130 const union pipe_color_union
*color
,
131 double depth
, unsigned stencil
)
133 struct panfrost_context
*ctx
= pan_context(pipe
);
135 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
136 * the existing batch targeting this FBO has draws. We could probably
137 * avoid that by replacing plain clears by quad-draws with a specific
138 * color/depth/stencil value, thus avoiding the generation of extra
141 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
143 panfrost_batch_add_fbo_bos(batch
);
144 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
147 /* Reset per-frame context, called on context initialisation as well as after
148 * flushing a frame */
151 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
153 /* TODO: When does this need to be handled? */
154 ctx
->active_queries
= true;
158 panfrost_writes_point_size(struct panfrost_context
*ctx
)
160 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
161 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
163 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
166 /* Compute number of UBOs active (more specifically, compute the highest UBO
167 * number addressable -- if there are gaps, include them in the count anyway).
168 * We always include UBO #0 in the count, since we *need* uniforms enabled for
172 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
174 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
175 return 32 - __builtin_clz(mask
);
178 /* The entire frame is in memory -- send it off to the kernel! */
182 struct pipe_context
*pipe
,
183 struct pipe_fence_handle
**fence
,
186 struct panfrost_context
*ctx
= pan_context(pipe
);
187 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
188 uint32_t syncobj
= 0;
191 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
193 /* Submit all pending jobs */
194 panfrost_flush_all_batches(ctx
, syncobj
);
197 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
198 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
199 *fence
= (struct pipe_fence_handle
*)f
;
202 if (dev
->debug
& PAN_DBG_TRACE
)
203 pandecode_next_frame();
207 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
209 struct panfrost_context
*ctx
= pan_context(pipe
);
210 panfrost_flush_all_batches(ctx
, 0);
213 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
216 g2m_draw_mode(enum pipe_prim_type mode
)
221 DEFINE_CASE(LINE_LOOP
);
222 DEFINE_CASE(LINE_STRIP
);
223 DEFINE_CASE(TRIANGLES
);
224 DEFINE_CASE(TRIANGLE_STRIP
);
225 DEFINE_CASE(TRIANGLE_FAN
);
227 DEFINE_CASE(QUAD_STRIP
);
228 DEFINE_CASE(POLYGON
);
231 unreachable("Invalid draw mode");
238 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
240 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
242 /* Check if we're scissoring at all */
244 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
247 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
250 /* Count generated primitives (when there is no geom/tess shaders) for
251 * transform feedback */
254 panfrost_statistics_record(
255 struct panfrost_context
*ctx
,
256 const struct pipe_draw_info
*info
)
258 if (!ctx
->active_queries
)
261 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
262 ctx
->prims_generated
+= prims
;
264 if (!ctx
->streamout
.num_targets
)
267 ctx
->tf_prims_generated
+= prims
;
271 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
273 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
276 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
278 ctx
->streamout
.offsets
[i
] += count
;
284 struct pipe_context
*pipe
,
285 const struct pipe_draw_info
*info
)
287 struct panfrost_context
*ctx
= pan_context(pipe
);
289 /* First of all, check the scissor to see if anything is drawn at all.
290 * If it's not, we drop the draw (mostly a conformance issue;
291 * well-behaved apps shouldn't hit this) */
293 if (panfrost_scissor_culls_everything(ctx
))
296 int mode
= info
->mode
;
298 /* Fallback unsupported restart index */
299 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
301 if (info
->primitive_restart
&& info
->index_size
302 && info
->restart_index
!= primitive_index
) {
303 util_draw_vbo_without_prim_restart(pipe
, info
);
307 /* Fallback for unsupported modes */
309 assert(ctx
->rasterizer
!= NULL
);
311 if (!(ctx
->draw_modes
& (1 << mode
))) {
312 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
313 mode
= PIPE_PRIM_TRIANGLE_FAN
;
315 if (info
->count
< 4) {
316 /* Degenerate case? */
320 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
321 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
326 /* Now that we have a guaranteed terminating path, find the job.
327 * Assignment commented out to prevent unused warning */
329 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
331 panfrost_batch_add_fbo_bos(batch
);
332 panfrost_batch_set_requirements(batch
);
334 /* Take into account a negative bias */
335 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
336 ctx
->instance_count
= info
->instance_count
;
337 ctx
->active_prim
= info
->mode
;
339 struct mali_vertex_tiler_prefix vertex_prefix
, tiler_prefix
;
340 struct mali_vertex_tiler_postfix vertex_postfix
, tiler_postfix
;
341 union midgard_primitive_size primitive_size
;
342 unsigned vertex_count
;
344 panfrost_vt_init(ctx
, PIPE_SHADER_VERTEX
, &vertex_prefix
, &vertex_postfix
);
345 panfrost_vt_init(ctx
, PIPE_SHADER_FRAGMENT
, &tiler_prefix
, &tiler_postfix
);
347 panfrost_vt_set_draw_info(ctx
, info
, g2m_draw_mode(mode
),
348 &vertex_postfix
, &tiler_prefix
,
349 &tiler_postfix
, &vertex_count
,
352 panfrost_statistics_record(ctx
, info
);
354 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
355 * vertex_count, 1) */
357 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
358 1, vertex_count
, info
->instance_count
,
361 /* Emit all sort of descriptors. */
362 panfrost_emit_vertex_data(batch
, &vertex_postfix
);
363 panfrost_emit_varying_descriptor(batch
,
366 &vertex_postfix
, &tiler_postfix
,
368 panfrost_emit_shader_meta(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
369 panfrost_emit_shader_meta(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
370 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
371 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
372 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
373 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
374 panfrost_emit_const_buf(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
375 panfrost_emit_const_buf(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
376 panfrost_emit_viewport(batch
, &tiler_postfix
);
378 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
380 /* Fire off the draw itself */
381 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
382 &tiler_prefix
, &tiler_postfix
,
385 /* Adjust the batch stack size based on the new shader stack sizes. */
386 panfrost_batch_adjust_stack_size(batch
);
388 /* Increment transform feedback offsets */
389 panfrost_update_streamout_offsets(ctx
);
395 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
401 panfrost_create_rasterizer_state(
402 struct pipe_context
*pctx
,
403 const struct pipe_rasterizer_state
*cso
)
405 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
413 panfrost_bind_rasterizer_state(
414 struct pipe_context
*pctx
,
417 struct panfrost_context
*ctx
= pan_context(pctx
);
419 ctx
->rasterizer
= hwcso
;
424 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
425 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
427 /* Point sprites are emulated */
429 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
431 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
432 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
436 panfrost_create_vertex_elements_state(
437 struct pipe_context
*pctx
,
438 unsigned num_elements
,
439 const struct pipe_vertex_element
*elements
)
441 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
442 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
444 so
->num_elements
= num_elements
;
445 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
447 for (int i
= 0; i
< num_elements
; ++i
) {
450 enum pipe_format fmt
= elements
[i
].src_format
;
451 const struct util_format_description
*desc
= util_format_description(fmt
);
452 so
->hw
[i
].unknown1
= 0x2;
454 unsigned swizzle
= 0;
455 if (dev
->quirks
& HAS_SWIZZLES
)
456 swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
458 swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
460 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
461 so
->hw
[i
].format
= (hw_format
<< 12) | swizzle
;
465 /* Let's also prepare vertex builtins */
466 so
->hw
[PAN_VERTEX_ID
].format
= MALI_R32UI
;
467 if (dev
->quirks
& HAS_SWIZZLES
)
468 so
->hw
[PAN_VERTEX_ID
].format
= (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
470 so
->hw
[PAN_VERTEX_ID
].format
= (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
472 if (dev
->quirks
& HAS_SWIZZLES
)
473 so
->hw
[PAN_INSTANCE_ID
].format
= (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
475 so
->hw
[PAN_INSTANCE_ID
].format
= (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
481 panfrost_bind_vertex_elements_state(
482 struct pipe_context
*pctx
,
485 struct panfrost_context
*ctx
= pan_context(pctx
);
490 panfrost_create_shader_state(
491 struct pipe_context
*pctx
,
492 const struct pipe_shader_state
*cso
,
493 enum pipe_shader_type stage
)
495 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
496 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
499 /* Token deep copy to prevent memory corruption */
501 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
502 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
504 /* Precompile for shader-db if we need to */
505 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
506 struct panfrost_context
*ctx
= pan_context(pctx
);
508 struct panfrost_shader_state state
;
509 uint64_t outputs_written
;
511 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
513 tgsi_processor_to_shader_stage(stage
),
514 &state
, &outputs_written
);
521 panfrost_delete_shader_state(
522 struct pipe_context
*pctx
,
525 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
527 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
528 /* TODO: leaks TGSI tokens! */
531 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
532 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
533 panfrost_bo_unreference(shader_state
->bo
);
534 shader_state
->bo
= NULL
;
542 panfrost_create_sampler_state(
543 struct pipe_context
*pctx
,
544 const struct pipe_sampler_state
*cso
)
546 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
547 struct panfrost_device
*device
= pan_device(pctx
->screen
);
551 if (device
->quirks
& IS_BIFROST
)
552 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
554 panfrost_sampler_desc_init(cso
, &so
->hw
);
560 panfrost_bind_sampler_states(
561 struct pipe_context
*pctx
,
562 enum pipe_shader_type shader
,
563 unsigned start_slot
, unsigned num_sampler
,
566 assert(start_slot
== 0);
568 struct panfrost_context
*ctx
= pan_context(pctx
);
570 /* XXX: Should upload, not just copy? */
571 ctx
->sampler_count
[shader
] = num_sampler
;
572 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
576 panfrost_variant_matches(
577 struct panfrost_context
*ctx
,
578 struct panfrost_shader_state
*variant
,
579 enum pipe_shader_type type
)
581 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
582 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
584 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
586 if (variant
->outputs_read
) {
587 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
590 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
591 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
593 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
594 fmt
= fb
->cbufs
[i
]->format
;
596 const struct util_format_description
*desc
=
597 util_format_description(fmt
);
599 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
600 fmt
= PIPE_FORMAT_NONE
;
602 if (variant
->rt_formats
[i
] != fmt
)
607 /* Point sprites TODO on bifrost, always pass */
608 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
609 variant
->point_sprite_mask
)
610 && !(dev
->quirks
& IS_BIFROST
)) {
611 /* Ensure the same varyings are turned to point sprites */
612 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
615 /* Ensure the orientation is correct */
617 rasterizer
->sprite_coord_mode
==
618 PIPE_SPRITE_COORD_UPPER_LEFT
;
620 if (variant
->point_sprite_upper_left
!= upper_left
)
624 /* Otherwise, we're good to go */
629 * Fix an uncompiled shader's stream output info, and produce a bitmask
630 * of which VARYING_SLOT_* are captured for stream output.
632 * Core Gallium stores output->register_index as a "slot" number, where
633 * slots are assigned consecutively to all outputs in info->outputs_written.
634 * This naive packing of outputs doesn't work for us - we too have slots,
635 * but the layout is defined by the VUE map, which we won't have until we
636 * compile a specific shader variant. So, we remap these and simply store
637 * VARYING_SLOT_* in our copy's output->register_index fields.
639 * We then produce a bitmask of outputs which are used for SO.
641 * Implementation from iris.
645 update_so_info(struct pipe_stream_output_info
*so_info
,
646 uint64_t outputs_written
)
648 uint64_t so_outputs
= 0;
649 uint8_t reverse_map
[64] = {0};
652 while (outputs_written
)
653 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
655 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
656 struct pipe_stream_output
*output
= &so_info
->output
[i
];
658 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
659 output
->register_index
= reverse_map
[output
->register_index
];
661 so_outputs
|= 1ull << output
->register_index
;
668 panfrost_bind_shader_state(
669 struct pipe_context
*pctx
,
671 enum pipe_shader_type type
)
673 struct panfrost_context
*ctx
= pan_context(pctx
);
674 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
675 ctx
->shader
[type
] = hwcso
;
679 /* Match the appropriate variant */
682 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
684 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
685 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
692 /* No variant matched, so create a new one */
693 variant
= variants
->variant_count
++;
695 if (variants
->variant_count
> variants
->variant_space
) {
696 unsigned old_space
= variants
->variant_space
;
698 variants
->variant_space
*= 2;
699 if (variants
->variant_space
== 0)
700 variants
->variant_space
= 1;
702 /* Arbitrary limit to stop runaway programs from
703 * creating an unbounded number of shader variants. */
704 assert(variants
->variant_space
< 1024);
706 unsigned msize
= sizeof(struct panfrost_shader_state
);
707 variants
->variants
= realloc(variants
->variants
,
708 variants
->variant_space
* msize
);
710 memset(&variants
->variants
[old_space
], 0,
711 (variants
->variant_space
- old_space
) * msize
);
714 struct panfrost_shader_state
*v
=
715 &variants
->variants
[variant
];
717 if (type
== PIPE_SHADER_FRAGMENT
) {
718 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
719 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
720 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
722 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
723 fmt
= fb
->cbufs
[i
]->format
;
725 const struct util_format_description
*desc
=
726 util_format_description(fmt
);
728 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
729 fmt
= PIPE_FORMAT_NONE
;
731 v
->rt_formats
[i
] = fmt
;
734 /* Point sprites are TODO on Bifrost */
735 if (ctx
->rasterizer
&& !(dev
->quirks
& IS_BIFROST
)) {
736 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
737 v
->point_sprite_upper_left
=
738 ctx
->rasterizer
->base
.sprite_coord_mode
==
739 PIPE_SPRITE_COORD_UPPER_LEFT
;
744 /* Select this variant */
745 variants
->active_variant
= variant
;
747 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
748 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
750 /* We finally have a variant, so compile it */
752 if (!shader_state
->compiled
) {
753 uint64_t outputs_written
= 0;
755 panfrost_shader_compile(ctx
, variants
->base
.type
,
756 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
757 variants
->base
.ir
.nir
:
758 variants
->base
.tokens
,
759 tgsi_processor_to_shader_stage(type
),
763 shader_state
->compiled
= true;
765 /* Fixup the stream out information, since what Gallium returns
766 * normally is mildly insane */
768 shader_state
->stream_output
= variants
->base
.stream_output
;
769 shader_state
->so_mask
=
770 update_so_info(&shader_state
->stream_output
, outputs_written
);
775 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
777 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
781 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
783 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
787 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
789 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
793 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
795 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
799 panfrost_set_vertex_buffers(
800 struct pipe_context
*pctx
,
802 unsigned num_buffers
,
803 const struct pipe_vertex_buffer
*buffers
)
805 struct panfrost_context
*ctx
= pan_context(pctx
);
807 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
811 panfrost_set_constant_buffer(
812 struct pipe_context
*pctx
,
813 enum pipe_shader_type shader
, uint index
,
814 const struct pipe_constant_buffer
*buf
)
816 struct panfrost_context
*ctx
= pan_context(pctx
);
817 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
819 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
821 unsigned mask
= (1 << index
);
823 if (unlikely(!buf
)) {
824 pbuf
->enabled_mask
&= ~mask
;
825 pbuf
->dirty_mask
&= ~mask
;
829 pbuf
->enabled_mask
|= mask
;
830 pbuf
->dirty_mask
|= mask
;
834 panfrost_set_stencil_ref(
835 struct pipe_context
*pctx
,
836 const struct pipe_stencil_ref
*ref
)
838 struct panfrost_context
*ctx
= pan_context(pctx
);
839 ctx
->stencil_ref
= *ref
;
843 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
844 struct pipe_context
*pctx
,
845 struct pipe_resource
*texture
)
847 struct panfrost_device
*device
= pan_device(pctx
->screen
);
848 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
849 enum pipe_format format
= so
->base
.format
;
852 /* Format to access the stencil portion of a Z32_S8 texture */
853 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
854 assert(prsrc
->separate_stencil
);
855 texture
= &prsrc
->separate_stencil
->base
;
856 prsrc
= (struct panfrost_resource
*)texture
;
857 format
= texture
->format
;
860 const struct util_format_description
*desc
= util_format_description(format
);
862 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
864 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
866 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
868 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
869 desc
= util_format_description(format
);
872 so
->texture_bo
= prsrc
->bo
->gpu
;
873 so
->modifier
= prsrc
->modifier
;
875 unsigned char user_swizzle
[4] = {
882 /* In the hardware, array_size refers specifically to array textures,
883 * whereas in Gallium, it also covers cubemaps */
885 unsigned array_size
= texture
->array_size
;
886 unsigned depth
= texture
->depth0
;
888 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
889 /* TODO: Cubemap arrays */
890 assert(array_size
== 6);
894 /* MSAA only supported for 2D textures (and 2D texture arrays via an
895 * extension currently unimplemented */
897 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
899 depth
= texture
->nr_samples
;
901 /* MSAA only supported for 2D textures */
902 assert(texture
->nr_samples
<= 1);
905 enum mali_texture_dimension type
=
906 panfrost_translate_texture_dimension(so
->base
.target
);
908 if (device
->quirks
& IS_BIFROST
) {
909 unsigned char composed_swizzle
[4];
910 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
912 unsigned size
= panfrost_estimate_texture_payload_size(
913 so
->base
.u
.tex
.first_level
,
914 so
->base
.u
.tex
.last_level
,
915 so
->base
.u
.tex
.first_layer
,
916 so
->base
.u
.tex
.last_layer
,
918 type
, prsrc
->modifier
);
920 so
->bo
= panfrost_bo_create(device
, size
, 0);
922 panfrost_new_texture_bifrost(
923 &so
->bifrost_descriptor
,
924 texture
->width0
, texture
->height0
,
927 type
, prsrc
->modifier
,
928 so
->base
.u
.tex
.first_level
,
929 so
->base
.u
.tex
.last_level
,
930 so
->base
.u
.tex
.first_layer
,
931 so
->base
.u
.tex
.last_layer
,
933 prsrc
->cubemap_stride
,
934 panfrost_translate_swizzle_4(composed_swizzle
),
939 unsigned size
= panfrost_estimate_texture_payload_size(
940 so
->base
.u
.tex
.first_level
,
941 so
->base
.u
.tex
.last_level
,
942 so
->base
.u
.tex
.first_layer
,
943 so
->base
.u
.tex
.last_layer
,
945 type
, prsrc
->modifier
);
946 size
+= MALI_MIDGARD_TEXTURE_LENGTH
;
948 so
->bo
= panfrost_bo_create(device
, size
, 0);
950 panfrost_new_texture(
952 texture
->width0
, texture
->height0
,
955 type
, prsrc
->modifier
,
956 so
->base
.u
.tex
.first_level
,
957 so
->base
.u
.tex
.last_level
,
958 so
->base
.u
.tex
.first_layer
,
959 so
->base
.u
.tex
.last_layer
,
961 prsrc
->cubemap_stride
,
962 panfrost_translate_swizzle_4(user_swizzle
),
968 static struct pipe_sampler_view
*
969 panfrost_create_sampler_view(
970 struct pipe_context
*pctx
,
971 struct pipe_resource
*texture
,
972 const struct pipe_sampler_view
*template)
974 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
976 pipe_reference(NULL
, &texture
->reference
);
978 so
->base
= *template;
979 so
->base
.texture
= texture
;
980 so
->base
.reference
.count
= 1;
981 so
->base
.context
= pctx
;
983 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
985 return (struct pipe_sampler_view
*) so
;
989 panfrost_set_sampler_views(
990 struct pipe_context
*pctx
,
991 enum pipe_shader_type shader
,
992 unsigned start_slot
, unsigned num_views
,
993 struct pipe_sampler_view
**views
)
995 struct panfrost_context
*ctx
= pan_context(pctx
);
999 assert(start_slot
== 0);
1001 for (i
= 0; i
< num_views
; ++i
) {
1004 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1008 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1009 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1012 ctx
->sampler_view_count
[shader
] = new_nr
;
1016 panfrost_sampler_view_destroy(
1017 struct pipe_context
*pctx
,
1018 struct pipe_sampler_view
*pview
)
1020 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1022 pipe_resource_reference(&pview
->texture
, NULL
);
1023 panfrost_bo_unreference(view
->bo
);
1028 panfrost_set_shader_buffers(
1029 struct pipe_context
*pctx
,
1030 enum pipe_shader_type shader
,
1031 unsigned start
, unsigned count
,
1032 const struct pipe_shader_buffer
*buffers
,
1033 unsigned writable_bitmask
)
1035 struct panfrost_context
*ctx
= pan_context(pctx
);
1037 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1038 buffers
, start
, count
);
1042 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1043 const struct pipe_framebuffer_state
*fb
)
1045 struct panfrost_context
*ctx
= pan_context(pctx
);
1047 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1049 panfrost_invalidate_frame(ctx
);
1051 /* We may need to generate a new variant if the fragment shader is
1052 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1053 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1055 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1056 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1059 static inline unsigned
1060 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1063 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1064 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1065 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1066 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1067 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1068 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1069 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1070 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1071 default: unreachable("Invalid stencil op");
1076 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1078 pan_pack(out
, STENCIL
, cfg
) {
1079 cfg
.mask
= in
->valuemask
;
1080 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1081 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1082 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1083 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1088 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1089 const struct pipe_depth_stencil_alpha_state
*zsa
)
1091 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1094 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1095 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1097 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1099 if (zsa
->stencil
[1].enabled
)
1100 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1102 so
->stencil_mask_back
= so
->stencil_mask_front
;
1104 /* Alpha lowered by frontend */
1105 assert(!zsa
->alpha
.enabled
);
1107 /* TODO: Bounds test should be easy */
1108 assert(!zsa
->depth
.bounds_test
);
1114 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1117 struct panfrost_context
*ctx
= pan_context(pipe
);
1118 struct panfrost_zsa_state
*zsa
= cso
;
1119 ctx
->depth_stencil
= zsa
;
1123 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1129 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1130 unsigned sample_mask
)
1132 struct panfrost_context
*ctx
= pan_context(pipe
);
1133 ctx
->sample_mask
= sample_mask
;
1137 panfrost_set_min_samples(struct pipe_context
*pipe
,
1138 unsigned min_samples
)
1140 struct panfrost_context
*ctx
= pan_context(pipe
);
1141 ctx
->min_samples
= min_samples
;
1146 panfrost_set_clip_state(struct pipe_context
*pipe
,
1147 const struct pipe_clip_state
*clip
)
1149 //struct panfrost_context *panfrost = pan_context(pipe);
1153 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1154 unsigned start_slot
,
1155 unsigned num_viewports
,
1156 const struct pipe_viewport_state
*viewports
)
1158 struct panfrost_context
*ctx
= pan_context(pipe
);
1160 assert(start_slot
== 0);
1161 assert(num_viewports
== 1);
1163 ctx
->pipe_viewport
= *viewports
;
1167 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1168 unsigned start_slot
,
1169 unsigned num_scissors
,
1170 const struct pipe_scissor_state
*scissors
)
1172 struct panfrost_context
*ctx
= pan_context(pipe
);
1174 assert(start_slot
== 0);
1175 assert(num_scissors
== 1);
1177 ctx
->scissor
= *scissors
;
1181 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1182 const struct pipe_poly_stipple
*stipple
)
1184 //struct panfrost_context *panfrost = pan_context(pipe);
1188 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1191 struct panfrost_context
*ctx
= pan_context(pipe
);
1192 ctx
->active_queries
= enable
;
1196 panfrost_destroy(struct pipe_context
*pipe
)
1198 struct panfrost_context
*panfrost
= pan_context(pipe
);
1200 if (panfrost
->blitter
)
1201 util_blitter_destroy(panfrost
->blitter
);
1203 if (panfrost
->blitter_wallpaper
)
1204 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1206 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1207 u_upload_destroy(pipe
->stream_uploader
);
1212 static struct pipe_query
*
1213 panfrost_create_query(struct pipe_context
*pipe
,
1217 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1222 return (struct pipe_query
*) q
;
1226 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1228 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1231 panfrost_bo_unreference(query
->bo
);
1239 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1241 struct panfrost_context
*ctx
= pan_context(pipe
);
1242 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1244 switch (query
->type
) {
1245 case PIPE_QUERY_OCCLUSION_COUNTER
:
1246 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1247 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1248 /* Allocate a bo for the query results to be stored */
1250 query
->bo
= panfrost_bo_create(
1251 pan_device(ctx
->base
.screen
),
1252 sizeof(unsigned), 0);
1255 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1256 *result
= 0; /* Default to 0 if nothing at all drawn. */
1257 ctx
->occlusion_query
= query
;
1260 /* Geometry statistics are computed in the driver. XXX: geom/tess
1263 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1264 query
->start
= ctx
->prims_generated
;
1266 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1267 query
->start
= ctx
->tf_prims_generated
;
1271 /* TODO: timestamp queries, etc? */
1279 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1281 struct panfrost_context
*ctx
= pan_context(pipe
);
1282 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1284 switch (query
->type
) {
1285 case PIPE_QUERY_OCCLUSION_COUNTER
:
1286 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1287 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1288 ctx
->occlusion_query
= NULL
;
1290 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1291 query
->end
= ctx
->prims_generated
;
1293 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1294 query
->end
= ctx
->tf_prims_generated
;
1302 panfrost_get_query_result(struct pipe_context
*pipe
,
1303 struct pipe_query
*q
,
1305 union pipe_query_result
*vresult
)
1307 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1308 struct panfrost_context
*ctx
= pan_context(pipe
);
1311 switch (query
->type
) {
1312 case PIPE_QUERY_OCCLUSION_COUNTER
:
1313 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1314 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1315 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1316 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1318 /* Read back the query results */
1319 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1320 unsigned passed
= *result
;
1322 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1323 vresult
->u64
= passed
;
1325 vresult
->b
= !!passed
;
1330 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1331 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1332 panfrost_flush_all_batches(ctx
, 0);
1333 vresult
->u64
= query
->end
- query
->start
;
1337 /* TODO: more queries */
1344 static struct pipe_stream_output_target
*
1345 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1346 struct pipe_resource
*prsc
,
1347 unsigned buffer_offset
,
1348 unsigned buffer_size
)
1350 struct pipe_stream_output_target
*target
;
1352 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1357 pipe_reference_init(&target
->reference
, 1);
1358 pipe_resource_reference(&target
->buffer
, prsc
);
1360 target
->context
= pctx
;
1361 target
->buffer_offset
= buffer_offset
;
1362 target
->buffer_size
= buffer_size
;
1368 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1369 struct pipe_stream_output_target
*target
)
1371 pipe_resource_reference(&target
->buffer
, NULL
);
1372 ralloc_free(target
);
1376 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1377 unsigned num_targets
,
1378 struct pipe_stream_output_target
**targets
,
1379 const unsigned *offsets
)
1381 struct panfrost_context
*ctx
= pan_context(pctx
);
1382 struct panfrost_streamout
*so
= &ctx
->streamout
;
1384 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1386 for (unsigned i
= 0; i
< num_targets
; i
++) {
1387 if (offsets
[i
] != -1)
1388 so
->offsets
[i
] = offsets
[i
];
1390 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1393 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1394 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1396 so
->num_targets
= num_targets
;
1399 struct pipe_context
*
1400 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1402 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1403 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1404 struct panfrost_device
*dev
= pan_device(screen
);
1406 gallium
->screen
= screen
;
1408 gallium
->destroy
= panfrost_destroy
;
1410 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1412 gallium
->flush
= panfrost_flush
;
1413 gallium
->clear
= panfrost_clear
;
1414 gallium
->draw_vbo
= panfrost_draw_vbo
;
1415 gallium
->texture_barrier
= panfrost_texture_barrier
;
1417 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1418 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1419 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1421 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1423 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1424 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1425 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1427 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1428 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1429 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1431 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1432 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1433 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1435 gallium
->create_fs_state
= panfrost_create_fs_state
;
1436 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1437 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1439 gallium
->create_vs_state
= panfrost_create_vs_state
;
1440 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1441 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1443 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1444 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1445 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1447 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1448 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1449 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1451 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1452 gallium
->set_min_samples
= panfrost_set_min_samples
;
1454 gallium
->set_clip_state
= panfrost_set_clip_state
;
1455 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1456 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1457 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1458 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1460 gallium
->create_query
= panfrost_create_query
;
1461 gallium
->destroy_query
= panfrost_destroy_query
;
1462 gallium
->begin_query
= panfrost_begin_query
;
1463 gallium
->end_query
= panfrost_end_query
;
1464 gallium
->get_query_result
= panfrost_get_query_result
;
1466 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1467 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1468 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1470 panfrost_resource_context_init(gallium
);
1471 panfrost_blend_context_init(gallium
);
1472 panfrost_compute_context_init(gallium
);
1474 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1475 gallium
->const_uploader
= gallium
->stream_uploader
;
1476 assert(gallium
->stream_uploader
);
1478 /* All of our GPUs support ES mode. Midgard supports additionally
1479 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1481 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1483 if (!(dev
->quirks
& IS_BIFROST
)) {
1484 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1485 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1488 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1490 ctx
->blitter
= util_blitter_create(gallium
);
1491 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1493 assert(ctx
->blitter
);
1494 assert(ctx
->blitter_wallpaper
);
1496 /* Prepare for render! */
1498 panfrost_batch_init(ctx
);
1499 panfrost_invalidate_frame(ctx
);
1501 if (!(dev
->quirks
& IS_BIFROST
)) {
1502 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1503 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1506 /* By default mask everything on */
1507 ctx
->sample_mask
= ~0;