2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
85 t
.heap_start
= device
->tiler_heap
->gpu
;
86 t
.heap_end
= device
->tiler_heap
->gpu
+ device
->tiler_heap
->size
;
88 struct panfrost_bo
*tiler_dummy
;
90 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
91 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t
.heap_start
= tiler_dummy
->gpu
;
95 t
.heap_end
= t
.heap_start
;
97 /* Use a dummy polygon list */
98 t
.polygon_list
= tiler_dummy
->gpu
;
100 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
104 t
.hierarchy_mask
= MALI_TILER_USER
;
105 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
109 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
113 t
.polygon_list_body
=
114 t
.polygon_list
+ header_size
;
121 struct pipe_context
*pipe
,
123 const struct pipe_scissor_state
*scissor_state
,
124 const union pipe_color_union
*color
,
125 double depth
, unsigned stencil
)
127 struct panfrost_context
*ctx
= pan_context(pipe
);
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
135 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
136 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
140 panfrost_writes_point_size(struct panfrost_context
*ctx
)
142 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
143 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
145 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
148 /* The entire frame is in memory -- send it off to the kernel! */
152 struct pipe_context
*pipe
,
153 struct pipe_fence_handle
**fence
,
156 struct panfrost_context
*ctx
= pan_context(pipe
);
157 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
158 uint32_t syncobj
= 0;
161 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
163 /* Submit all pending jobs */
164 panfrost_flush_all_batches(ctx
, syncobj
);
167 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
168 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
169 *fence
= (struct pipe_fence_handle
*)f
;
172 if (dev
->debug
& PAN_DBG_TRACE
)
173 pandecode_next_frame();
177 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
179 struct panfrost_context
*ctx
= pan_context(pipe
);
180 panfrost_flush_all_batches(ctx
, 0);
183 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
186 g2m_draw_mode(enum pipe_prim_type mode
)
191 DEFINE_CASE(LINE_LOOP
);
192 DEFINE_CASE(LINE_STRIP
);
193 DEFINE_CASE(TRIANGLES
);
194 DEFINE_CASE(TRIANGLE_STRIP
);
195 DEFINE_CASE(TRIANGLE_FAN
);
197 DEFINE_CASE(QUAD_STRIP
);
198 DEFINE_CASE(POLYGON
);
201 unreachable("Invalid draw mode");
208 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
210 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
212 /* Check if we're scissoring at all */
214 if (!ctx
->rasterizer
->base
.scissor
)
217 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
220 /* Count generated primitives (when there is no geom/tess shaders) for
221 * transform feedback */
224 panfrost_statistics_record(
225 struct panfrost_context
*ctx
,
226 const struct pipe_draw_info
*info
)
228 if (!ctx
->active_queries
)
231 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
232 ctx
->prims_generated
+= prims
;
234 if (!ctx
->streamout
.num_targets
)
237 ctx
->tf_prims_generated
+= prims
;
241 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
243 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
246 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
248 ctx
->streamout
.offsets
[i
] += count
;
254 struct pipe_context
*pipe
,
255 const struct pipe_draw_info
*info
)
257 struct panfrost_context
*ctx
= pan_context(pipe
);
259 /* First of all, check the scissor to see if anything is drawn at all.
260 * If it's not, we drop the draw (mostly a conformance issue;
261 * well-behaved apps shouldn't hit this) */
263 if (panfrost_scissor_culls_everything(ctx
))
266 int mode
= info
->mode
;
268 /* Fallback unsupported restart index */
269 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
271 if (info
->primitive_restart
&& info
->index_size
272 && info
->restart_index
!= primitive_index
) {
273 util_draw_vbo_without_prim_restart(pipe
, info
);
277 /* Fallback for unsupported modes */
279 assert(ctx
->rasterizer
!= NULL
);
281 if (!(ctx
->draw_modes
& (1 << mode
))) {
282 if (info
->count
< 4) {
283 /* Degenerate case? */
287 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
288 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
292 /* Now that we have a guaranteed terminating path, find the job. */
294 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
295 panfrost_batch_set_requirements(batch
);
297 /* Take into account a negative bias */
298 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
299 ctx
->instance_count
= info
->instance_count
;
300 ctx
->active_prim
= info
->mode
;
302 struct mali_vertex_tiler_prefix vertex_prefix
, tiler_prefix
;
303 struct mali_vertex_tiler_postfix vertex_postfix
, tiler_postfix
;
304 union midgard_primitive_size primitive_size
;
305 unsigned vertex_count
;
307 panfrost_vt_init(ctx
, PIPE_SHADER_VERTEX
, &vertex_prefix
, &vertex_postfix
);
308 panfrost_vt_init(ctx
, PIPE_SHADER_FRAGMENT
, &tiler_prefix
, &tiler_postfix
);
310 panfrost_vt_set_draw_info(ctx
, info
, g2m_draw_mode(mode
),
311 &vertex_postfix
, &tiler_prefix
,
312 &tiler_postfix
, &vertex_count
,
315 panfrost_statistics_record(ctx
, info
);
317 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
318 1, vertex_count
, info
->instance_count
,
321 /* Emit all sort of descriptors. */
322 panfrost_emit_vertex_data(batch
, &vertex_postfix
);
323 panfrost_emit_varying_descriptor(batch
,
326 &vertex_postfix
, &tiler_postfix
,
328 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
329 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
330 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
331 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
332 panfrost_emit_const_buf(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
333 panfrost_emit_const_buf(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
334 panfrost_emit_viewport(batch
, &tiler_postfix
);
336 vertex_postfix
.shader
= panfrost_emit_compute_shader_meta(batch
, PIPE_SHADER_VERTEX
);
337 tiler_postfix
.shader
= panfrost_emit_frag_shader_meta(batch
);
339 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
341 /* Fire off the draw itself */
342 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
343 &tiler_prefix
, &tiler_postfix
,
346 /* Adjust the batch stack size based on the new shader stack sizes. */
347 panfrost_batch_adjust_stack_size(batch
);
349 /* Increment transform feedback offsets */
350 panfrost_update_streamout_offsets(ctx
);
356 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
362 panfrost_create_rasterizer_state(
363 struct pipe_context
*pctx
,
364 const struct pipe_rasterizer_state
*cso
)
366 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
370 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
371 assert(cso
->offset_clamp
== 0.0);
377 panfrost_bind_rasterizer_state(
378 struct pipe_context
*pctx
,
381 struct panfrost_context
*ctx
= pan_context(pctx
);
383 ctx
->rasterizer
= hwcso
;
388 /* Point sprites are emulated */
390 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
392 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
393 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
397 panfrost_create_vertex_elements_state(
398 struct pipe_context
*pctx
,
399 unsigned num_elements
,
400 const struct pipe_vertex_element
*elements
)
402 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
403 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
405 so
->num_elements
= num_elements
;
406 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
408 for (int i
= 0; i
< num_elements
; ++i
) {
409 enum pipe_format fmt
= elements
[i
].src_format
;
410 const struct util_format_description
*desc
= util_format_description(fmt
);
411 unsigned swizzle
= 0;
412 if (dev
->quirks
& HAS_SWIZZLES
)
413 swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
415 swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
417 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
418 so
->formats
[i
] = (hw_format
<< 12) | swizzle
;
422 /* Let's also prepare vertex builtins */
423 if (dev
->quirks
& HAS_SWIZZLES
)
424 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
426 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
428 if (dev
->quirks
& HAS_SWIZZLES
)
429 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
431 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
437 panfrost_bind_vertex_elements_state(
438 struct pipe_context
*pctx
,
441 struct panfrost_context
*ctx
= pan_context(pctx
);
446 panfrost_create_shader_state(
447 struct pipe_context
*pctx
,
448 const struct pipe_shader_state
*cso
,
449 enum pipe_shader_type stage
)
451 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
452 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
455 /* Token deep copy to prevent memory corruption */
457 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
458 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
460 /* Precompile for shader-db if we need to */
461 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
462 struct panfrost_context
*ctx
= pan_context(pctx
);
464 struct panfrost_shader_state state
= { 0 };
465 uint64_t outputs_written
;
467 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
469 tgsi_processor_to_shader_stage(stage
),
470 &state
, &outputs_written
);
477 panfrost_delete_shader_state(
478 struct pipe_context
*pctx
,
481 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
483 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
484 /* TODO: leaks TGSI tokens! */
487 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
488 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
489 panfrost_bo_unreference(shader_state
->bo
);
491 if (shader_state
->upload
.rsrc
)
492 pipe_resource_reference(&shader_state
->upload
.rsrc
, NULL
);
494 shader_state
->bo
= NULL
;
503 panfrost_create_sampler_state(
504 struct pipe_context
*pctx
,
505 const struct pipe_sampler_state
*cso
)
507 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
508 struct panfrost_device
*device
= pan_device(pctx
->screen
);
512 if (device
->quirks
& IS_BIFROST
)
513 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
515 panfrost_sampler_desc_init(cso
, &so
->hw
);
521 panfrost_bind_sampler_states(
522 struct pipe_context
*pctx
,
523 enum pipe_shader_type shader
,
524 unsigned start_slot
, unsigned num_sampler
,
527 assert(start_slot
== 0);
529 struct panfrost_context
*ctx
= pan_context(pctx
);
531 /* XXX: Should upload, not just copy? */
532 ctx
->sampler_count
[shader
] = num_sampler
;
533 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
537 panfrost_variant_matches(
538 struct panfrost_context
*ctx
,
539 struct panfrost_shader_state
*variant
,
540 enum pipe_shader_type type
)
542 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
543 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
545 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
547 if (variant
->outputs_read
) {
548 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
551 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
552 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
554 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
555 fmt
= fb
->cbufs
[i
]->format
;
557 const struct util_format_description
*desc
=
558 util_format_description(fmt
);
560 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
561 fmt
= PIPE_FORMAT_NONE
;
563 if (variant
->rt_formats
[i
] != fmt
)
568 /* Point sprites TODO on bifrost, always pass */
569 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
570 variant
->point_sprite_mask
)
571 && !(dev
->quirks
& IS_BIFROST
)) {
572 /* Ensure the same varyings are turned to point sprites */
573 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
576 /* Ensure the orientation is correct */
578 rasterizer
->sprite_coord_mode
==
579 PIPE_SPRITE_COORD_UPPER_LEFT
;
581 if (variant
->point_sprite_upper_left
!= upper_left
)
585 /* Otherwise, we're good to go */
590 * Fix an uncompiled shader's stream output info, and produce a bitmask
591 * of which VARYING_SLOT_* are captured for stream output.
593 * Core Gallium stores output->register_index as a "slot" number, where
594 * slots are assigned consecutively to all outputs in info->outputs_written.
595 * This naive packing of outputs doesn't work for us - we too have slots,
596 * but the layout is defined by the VUE map, which we won't have until we
597 * compile a specific shader variant. So, we remap these and simply store
598 * VARYING_SLOT_* in our copy's output->register_index fields.
600 * We then produce a bitmask of outputs which are used for SO.
602 * Implementation from iris.
606 update_so_info(struct pipe_stream_output_info
*so_info
,
607 uint64_t outputs_written
)
609 uint64_t so_outputs
= 0;
610 uint8_t reverse_map
[64] = {0};
613 while (outputs_written
)
614 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
616 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
617 struct pipe_stream_output
*output
= &so_info
->output
[i
];
619 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
620 output
->register_index
= reverse_map
[output
->register_index
];
622 so_outputs
|= 1ull << output
->register_index
;
629 panfrost_bind_shader_state(
630 struct pipe_context
*pctx
,
632 enum pipe_shader_type type
)
634 struct panfrost_context
*ctx
= pan_context(pctx
);
635 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
636 ctx
->shader
[type
] = hwcso
;
640 /* Match the appropriate variant */
643 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
645 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
646 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
653 /* No variant matched, so create a new one */
654 variant
= variants
->variant_count
++;
656 if (variants
->variant_count
> variants
->variant_space
) {
657 unsigned old_space
= variants
->variant_space
;
659 variants
->variant_space
*= 2;
660 if (variants
->variant_space
== 0)
661 variants
->variant_space
= 1;
663 /* Arbitrary limit to stop runaway programs from
664 * creating an unbounded number of shader variants. */
665 assert(variants
->variant_space
< 1024);
667 unsigned msize
= sizeof(struct panfrost_shader_state
);
668 variants
->variants
= realloc(variants
->variants
,
669 variants
->variant_space
* msize
);
671 memset(&variants
->variants
[old_space
], 0,
672 (variants
->variant_space
- old_space
) * msize
);
675 struct panfrost_shader_state
*v
=
676 &variants
->variants
[variant
];
678 if (type
== PIPE_SHADER_FRAGMENT
) {
679 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
680 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
681 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
683 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
684 fmt
= fb
->cbufs
[i
]->format
;
686 const struct util_format_description
*desc
=
687 util_format_description(fmt
);
689 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
690 fmt
= PIPE_FORMAT_NONE
;
692 v
->rt_formats
[i
] = fmt
;
695 /* Point sprites are TODO on Bifrost */
696 if (ctx
->rasterizer
&& !(dev
->quirks
& IS_BIFROST
)) {
697 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
698 v
->point_sprite_upper_left
=
699 ctx
->rasterizer
->base
.sprite_coord_mode
==
700 PIPE_SPRITE_COORD_UPPER_LEFT
;
705 /* Select this variant */
706 variants
->active_variant
= variant
;
708 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
709 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
711 /* We finally have a variant, so compile it */
713 if (!shader_state
->compiled
) {
714 uint64_t outputs_written
= 0;
716 panfrost_shader_compile(ctx
, variants
->base
.type
,
717 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
718 variants
->base
.ir
.nir
:
719 variants
->base
.tokens
,
720 tgsi_processor_to_shader_stage(type
),
724 shader_state
->compiled
= true;
726 /* Fixup the stream out information, since what Gallium returns
727 * normally is mildly insane */
729 shader_state
->stream_output
= variants
->base
.stream_output
;
730 shader_state
->so_mask
=
731 update_so_info(&shader_state
->stream_output
, outputs_written
);
736 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
738 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
742 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
744 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
748 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
750 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
754 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
756 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
760 panfrost_set_vertex_buffers(
761 struct pipe_context
*pctx
,
763 unsigned num_buffers
,
764 const struct pipe_vertex_buffer
*buffers
)
766 struct panfrost_context
*ctx
= pan_context(pctx
);
768 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
772 panfrost_set_constant_buffer(
773 struct pipe_context
*pctx
,
774 enum pipe_shader_type shader
, uint index
,
775 const struct pipe_constant_buffer
*buf
)
777 struct panfrost_context
*ctx
= pan_context(pctx
);
778 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
780 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
782 unsigned mask
= (1 << index
);
784 if (unlikely(!buf
)) {
785 pbuf
->enabled_mask
&= ~mask
;
786 pbuf
->dirty_mask
&= ~mask
;
790 pbuf
->enabled_mask
|= mask
;
791 pbuf
->dirty_mask
|= mask
;
795 panfrost_set_stencil_ref(
796 struct pipe_context
*pctx
,
797 const struct pipe_stencil_ref
*ref
)
799 struct panfrost_context
*ctx
= pan_context(pctx
);
800 ctx
->stencil_ref
= *ref
;
804 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
805 struct pipe_context
*pctx
,
806 struct pipe_resource
*texture
)
808 struct panfrost_device
*device
= pan_device(pctx
->screen
);
809 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
810 enum pipe_format format
= so
->base
.format
;
813 /* Format to access the stencil portion of a Z32_S8 texture */
814 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
815 assert(prsrc
->separate_stencil
);
816 texture
= &prsrc
->separate_stencil
->base
;
817 prsrc
= (struct panfrost_resource
*)texture
;
818 format
= texture
->format
;
821 const struct util_format_description
*desc
= util_format_description(format
);
823 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
825 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
827 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
829 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
830 desc
= util_format_description(format
);
833 so
->texture_bo
= prsrc
->bo
->gpu
;
834 so
->modifier
= prsrc
->modifier
;
836 unsigned char user_swizzle
[4] = {
843 /* In the hardware, array_size refers specifically to array textures,
844 * whereas in Gallium, it also covers cubemaps */
846 unsigned array_size
= texture
->array_size
;
847 unsigned depth
= texture
->depth0
;
849 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
850 /* TODO: Cubemap arrays */
851 assert(array_size
== 6);
855 /* MSAA only supported for 2D textures (and 2D texture arrays via an
856 * extension currently unimplemented */
858 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
860 depth
= texture
->nr_samples
;
862 /* MSAA only supported for 2D textures */
863 assert(texture
->nr_samples
<= 1);
866 enum mali_texture_dimension type
=
867 panfrost_translate_texture_dimension(so
->base
.target
);
869 if (device
->quirks
& IS_BIFROST
) {
870 unsigned char composed_swizzle
[4];
871 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
873 unsigned size
= panfrost_estimate_texture_payload_size(
874 so
->base
.u
.tex
.first_level
,
875 so
->base
.u
.tex
.last_level
,
876 so
->base
.u
.tex
.first_layer
,
877 so
->base
.u
.tex
.last_layer
,
879 type
, prsrc
->modifier
);
881 so
->bo
= panfrost_bo_create(device
, size
, 0);
883 panfrost_new_texture_bifrost(
884 &so
->bifrost_descriptor
,
885 texture
->width0
, texture
->height0
,
888 type
, prsrc
->modifier
,
889 so
->base
.u
.tex
.first_level
,
890 so
->base
.u
.tex
.last_level
,
891 so
->base
.u
.tex
.first_layer
,
892 so
->base
.u
.tex
.last_layer
,
894 prsrc
->cubemap_stride
,
895 panfrost_translate_swizzle_4(composed_swizzle
),
900 unsigned size
= panfrost_estimate_texture_payload_size(
901 so
->base
.u
.tex
.first_level
,
902 so
->base
.u
.tex
.last_level
,
903 so
->base
.u
.tex
.first_layer
,
904 so
->base
.u
.tex
.last_layer
,
906 type
, prsrc
->modifier
);
907 size
+= MALI_MIDGARD_TEXTURE_LENGTH
;
909 so
->bo
= panfrost_bo_create(device
, size
, 0);
911 panfrost_new_texture(
913 texture
->width0
, texture
->height0
,
916 type
, prsrc
->modifier
,
917 so
->base
.u
.tex
.first_level
,
918 so
->base
.u
.tex
.last_level
,
919 so
->base
.u
.tex
.first_layer
,
920 so
->base
.u
.tex
.last_layer
,
922 prsrc
->cubemap_stride
,
923 panfrost_translate_swizzle_4(user_swizzle
),
929 static struct pipe_sampler_view
*
930 panfrost_create_sampler_view(
931 struct pipe_context
*pctx
,
932 struct pipe_resource
*texture
,
933 const struct pipe_sampler_view
*template)
935 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
937 pipe_reference(NULL
, &texture
->reference
);
939 so
->base
= *template;
940 so
->base
.texture
= texture
;
941 so
->base
.reference
.count
= 1;
942 so
->base
.context
= pctx
;
944 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
946 return (struct pipe_sampler_view
*) so
;
950 panfrost_set_sampler_views(
951 struct pipe_context
*pctx
,
952 enum pipe_shader_type shader
,
953 unsigned start_slot
, unsigned num_views
,
954 struct pipe_sampler_view
**views
)
956 struct panfrost_context
*ctx
= pan_context(pctx
);
960 assert(start_slot
== 0);
962 for (i
= 0; i
< num_views
; ++i
) {
965 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
969 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
970 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
973 ctx
->sampler_view_count
[shader
] = new_nr
;
977 panfrost_sampler_view_destroy(
978 struct pipe_context
*pctx
,
979 struct pipe_sampler_view
*pview
)
981 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
983 pipe_resource_reference(&pview
->texture
, NULL
);
984 panfrost_bo_unreference(view
->bo
);
989 panfrost_set_shader_buffers(
990 struct pipe_context
*pctx
,
991 enum pipe_shader_type shader
,
992 unsigned start
, unsigned count
,
993 const struct pipe_shader_buffer
*buffers
,
994 unsigned writable_bitmask
)
996 struct panfrost_context
*ctx
= pan_context(pctx
);
998 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
999 buffers
, start
, count
);
1003 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1004 const struct pipe_framebuffer_state
*fb
)
1006 struct panfrost_context
*ctx
= pan_context(pctx
);
1008 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1011 /* We may need to generate a new variant if the fragment shader is
1012 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1013 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1015 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1016 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1019 static inline unsigned
1020 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1023 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1024 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1025 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1026 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1027 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1028 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1029 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1030 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1031 default: unreachable("Invalid stencil op");
1036 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1038 pan_pack(out
, STENCIL
, cfg
) {
1039 cfg
.mask
= in
->valuemask
;
1040 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1041 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1042 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1043 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1048 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1049 const struct pipe_depth_stencil_alpha_state
*zsa
)
1051 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1054 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1055 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1057 if (zsa
->stencil
[1].enabled
) {
1058 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1059 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1061 so
->stencil_back
= so
->stencil_front
;
1062 so
->stencil_mask_back
= so
->stencil_mask_front
;
1065 /* Alpha lowered by frontend */
1066 assert(!zsa
->alpha
.enabled
);
1068 /* TODO: Bounds test should be easy */
1069 assert(!zsa
->depth
.bounds_test
);
1075 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1078 struct panfrost_context
*ctx
= pan_context(pipe
);
1079 struct panfrost_zsa_state
*zsa
= cso
;
1080 ctx
->depth_stencil
= zsa
;
1084 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1090 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1091 unsigned sample_mask
)
1093 struct panfrost_context
*ctx
= pan_context(pipe
);
1094 ctx
->sample_mask
= sample_mask
;
1098 panfrost_set_min_samples(struct pipe_context
*pipe
,
1099 unsigned min_samples
)
1101 struct panfrost_context
*ctx
= pan_context(pipe
);
1102 ctx
->min_samples
= min_samples
;
1107 panfrost_set_clip_state(struct pipe_context
*pipe
,
1108 const struct pipe_clip_state
*clip
)
1110 //struct panfrost_context *panfrost = pan_context(pipe);
1114 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1115 unsigned start_slot
,
1116 unsigned num_viewports
,
1117 const struct pipe_viewport_state
*viewports
)
1119 struct panfrost_context
*ctx
= pan_context(pipe
);
1121 assert(start_slot
== 0);
1122 assert(num_viewports
== 1);
1124 ctx
->pipe_viewport
= *viewports
;
1128 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1129 unsigned start_slot
,
1130 unsigned num_scissors
,
1131 const struct pipe_scissor_state
*scissors
)
1133 struct panfrost_context
*ctx
= pan_context(pipe
);
1135 assert(start_slot
== 0);
1136 assert(num_scissors
== 1);
1138 ctx
->scissor
= *scissors
;
1142 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1143 const struct pipe_poly_stipple
*stipple
)
1145 //struct panfrost_context *panfrost = pan_context(pipe);
1149 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1152 struct panfrost_context
*ctx
= pan_context(pipe
);
1153 ctx
->active_queries
= enable
;
1157 panfrost_destroy(struct pipe_context
*pipe
)
1159 struct panfrost_context
*panfrost
= pan_context(pipe
);
1161 if (panfrost
->blitter
)
1162 util_blitter_destroy(panfrost
->blitter
);
1164 if (panfrost
->blitter_wallpaper
)
1165 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1167 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1168 u_upload_destroy(pipe
->stream_uploader
);
1169 u_upload_destroy(panfrost
->state_uploader
);
1174 static struct pipe_query
*
1175 panfrost_create_query(struct pipe_context
*pipe
,
1179 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1184 return (struct pipe_query
*) q
;
1188 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1190 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1193 panfrost_bo_unreference(query
->bo
);
1201 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1203 struct panfrost_context
*ctx
= pan_context(pipe
);
1204 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1206 switch (query
->type
) {
1207 case PIPE_QUERY_OCCLUSION_COUNTER
:
1208 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1209 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1210 /* Allocate a bo for the query results to be stored */
1212 query
->bo
= panfrost_bo_create(
1213 pan_device(ctx
->base
.screen
),
1214 sizeof(unsigned), 0);
1217 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1218 *result
= 0; /* Default to 0 if nothing at all drawn. */
1219 ctx
->occlusion_query
= query
;
1222 /* Geometry statistics are computed in the driver. XXX: geom/tess
1225 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1226 query
->start
= ctx
->prims_generated
;
1228 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1229 query
->start
= ctx
->tf_prims_generated
;
1233 /* TODO: timestamp queries, etc? */
1241 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1243 struct panfrost_context
*ctx
= pan_context(pipe
);
1244 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1246 switch (query
->type
) {
1247 case PIPE_QUERY_OCCLUSION_COUNTER
:
1248 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1249 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1250 ctx
->occlusion_query
= NULL
;
1252 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1253 query
->end
= ctx
->prims_generated
;
1255 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1256 query
->end
= ctx
->tf_prims_generated
;
1264 panfrost_get_query_result(struct pipe_context
*pipe
,
1265 struct pipe_query
*q
,
1267 union pipe_query_result
*vresult
)
1269 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1270 struct panfrost_context
*ctx
= pan_context(pipe
);
1273 switch (query
->type
) {
1274 case PIPE_QUERY_OCCLUSION_COUNTER
:
1275 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1276 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1277 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1278 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1280 /* Read back the query results */
1281 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1282 unsigned passed
= *result
;
1284 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1285 vresult
->u64
= passed
;
1287 vresult
->b
= !!passed
;
1292 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1293 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1294 panfrost_flush_all_batches(ctx
, 0);
1295 vresult
->u64
= query
->end
- query
->start
;
1299 /* TODO: more queries */
1306 static struct pipe_stream_output_target
*
1307 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1308 struct pipe_resource
*prsc
,
1309 unsigned buffer_offset
,
1310 unsigned buffer_size
)
1312 struct pipe_stream_output_target
*target
;
1314 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1319 pipe_reference_init(&target
->reference
, 1);
1320 pipe_resource_reference(&target
->buffer
, prsc
);
1322 target
->context
= pctx
;
1323 target
->buffer_offset
= buffer_offset
;
1324 target
->buffer_size
= buffer_size
;
1330 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1331 struct pipe_stream_output_target
*target
)
1333 pipe_resource_reference(&target
->buffer
, NULL
);
1334 ralloc_free(target
);
1338 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1339 unsigned num_targets
,
1340 struct pipe_stream_output_target
**targets
,
1341 const unsigned *offsets
)
1343 struct panfrost_context
*ctx
= pan_context(pctx
);
1344 struct panfrost_streamout
*so
= &ctx
->streamout
;
1346 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1348 for (unsigned i
= 0; i
< num_targets
; i
++) {
1349 if (offsets
[i
] != -1)
1350 so
->offsets
[i
] = offsets
[i
];
1352 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1355 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1356 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1358 so
->num_targets
= num_targets
;
1361 struct pipe_context
*
1362 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1364 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1365 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1366 struct panfrost_device
*dev
= pan_device(screen
);
1368 gallium
->screen
= screen
;
1370 gallium
->destroy
= panfrost_destroy
;
1372 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1374 gallium
->flush
= panfrost_flush
;
1375 gallium
->clear
= panfrost_clear
;
1376 gallium
->draw_vbo
= panfrost_draw_vbo
;
1377 gallium
->texture_barrier
= panfrost_texture_barrier
;
1379 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1380 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1381 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1383 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1385 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1386 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1387 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1389 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1390 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1391 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1393 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1394 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1395 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1397 gallium
->create_fs_state
= panfrost_create_fs_state
;
1398 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1399 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1401 gallium
->create_vs_state
= panfrost_create_vs_state
;
1402 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1403 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1405 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1406 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1407 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1409 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1410 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1411 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1413 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1414 gallium
->set_min_samples
= panfrost_set_min_samples
;
1416 gallium
->set_clip_state
= panfrost_set_clip_state
;
1417 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1418 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1419 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1420 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1422 gallium
->create_query
= panfrost_create_query
;
1423 gallium
->destroy_query
= panfrost_destroy_query
;
1424 gallium
->begin_query
= panfrost_begin_query
;
1425 gallium
->end_query
= panfrost_end_query
;
1426 gallium
->get_query_result
= panfrost_get_query_result
;
1428 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1429 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1430 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1432 panfrost_resource_context_init(gallium
);
1433 panfrost_blend_context_init(gallium
);
1434 panfrost_compute_context_init(gallium
);
1436 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1437 gallium
->const_uploader
= gallium
->stream_uploader
;
1439 ctx
->state_uploader
= u_upload_create(gallium
, 4096,
1440 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_DYNAMIC
, 0);
1442 /* All of our GPUs support ES mode. Midgard supports additionally
1443 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1445 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1447 if (!(dev
->quirks
& IS_BIFROST
)) {
1448 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1449 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1452 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1454 ctx
->blitter
= util_blitter_create(gallium
);
1455 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1457 assert(ctx
->blitter
);
1458 assert(ctx
->blitter_wallpaper
);
1460 /* Prepare for render! */
1462 panfrost_batch_init(ctx
);
1464 if (!(dev
->quirks
& IS_BIFROST
)) {
1465 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1466 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1469 /* By default mask everything on */
1470 ctx
->sample_mask
= ~0;
1471 ctx
->active_queries
= true;