2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
85 t
.heap_start
= device
->tiler_heap
->gpu
;
86 t
.heap_end
= device
->tiler_heap
->gpu
+ device
->tiler_heap
->size
;
88 struct panfrost_bo
*tiler_dummy
;
90 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
91 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t
.heap_start
= tiler_dummy
->gpu
;
95 t
.heap_end
= t
.heap_start
;
97 /* Use a dummy polygon list */
98 t
.polygon_list
= tiler_dummy
->gpu
;
100 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
104 t
.hierarchy_mask
= MALI_TILER_USER
;
105 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
109 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
113 t
.polygon_list_body
=
114 t
.polygon_list
+ header_size
;
121 struct pipe_context
*pipe
,
123 const struct pipe_scissor_state
*scissor_state
,
124 const union pipe_color_union
*color
,
125 double depth
, unsigned stencil
)
127 struct panfrost_context
*ctx
= pan_context(pipe
);
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
135 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
136 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
140 panfrost_writes_point_size(struct panfrost_context
*ctx
)
142 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
143 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
145 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
148 /* The entire frame is in memory -- send it off to the kernel! */
152 struct pipe_context
*pipe
,
153 struct pipe_fence_handle
**fence
,
156 struct panfrost_context
*ctx
= pan_context(pipe
);
157 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
158 uint32_t syncobj
= 0;
161 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
163 /* Submit all pending jobs */
164 panfrost_flush_all_batches(ctx
, syncobj
);
167 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
168 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
169 *fence
= (struct pipe_fence_handle
*)f
;
172 if (dev
->debug
& PAN_DBG_TRACE
)
173 pandecode_next_frame();
177 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
179 struct panfrost_context
*ctx
= pan_context(pipe
);
180 panfrost_flush_all_batches(ctx
, 0);
183 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
186 g2m_draw_mode(enum pipe_prim_type mode
)
191 DEFINE_CASE(LINE_LOOP
);
192 DEFINE_CASE(LINE_STRIP
);
193 DEFINE_CASE(TRIANGLES
);
194 DEFINE_CASE(TRIANGLE_STRIP
);
195 DEFINE_CASE(TRIANGLE_FAN
);
197 DEFINE_CASE(QUAD_STRIP
);
198 DEFINE_CASE(POLYGON
);
201 unreachable("Invalid draw mode");
208 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
210 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
212 /* Check if we're scissoring at all */
214 if (!ctx
->rasterizer
->base
.scissor
)
217 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
220 /* Count generated primitives (when there is no geom/tess shaders) for
221 * transform feedback */
224 panfrost_statistics_record(
225 struct panfrost_context
*ctx
,
226 const struct pipe_draw_info
*info
)
228 if (!ctx
->active_queries
)
231 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
232 ctx
->prims_generated
+= prims
;
234 if (!ctx
->streamout
.num_targets
)
237 ctx
->tf_prims_generated
+= prims
;
241 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
243 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
246 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
248 ctx
->streamout
.offsets
[i
] += count
;
254 struct pipe_context
*pipe
,
255 const struct pipe_draw_info
*info
)
257 struct panfrost_context
*ctx
= pan_context(pipe
);
258 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
260 /* First of all, check the scissor to see if anything is drawn at all.
261 * If it's not, we drop the draw (mostly a conformance issue;
262 * well-behaved apps shouldn't hit this) */
264 if (panfrost_scissor_culls_everything(ctx
))
267 int mode
= info
->mode
;
269 /* Fallback unsupported restart index */
270 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
272 if (info
->primitive_restart
&& info
->index_size
273 && info
->restart_index
!= primitive_index
) {
274 util_draw_vbo_without_prim_restart(pipe
, info
);
278 /* Fallback for unsupported modes */
280 assert(ctx
->rasterizer
!= NULL
);
282 if (!(ctx
->draw_modes
& (1 << mode
))) {
283 if (info
->count
< 4) {
284 /* Degenerate case? */
288 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
289 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
293 /* Now that we have a guaranteed terminating path, find the job. */
295 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
296 panfrost_batch_set_requirements(batch
);
298 /* Take into account a negative bias */
299 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
300 ctx
->instance_count
= info
->instance_count
;
301 ctx
->active_prim
= info
->mode
;
303 struct mali_vertex_tiler_prefix vertex_prefix
= { 0 }, tiler_prefix
= { 0 };
304 struct mali_vertex_tiler_postfix vertex_postfix
= { 0 }, tiler_postfix
= { 0 };
305 union midgard_primitive_size primitive_size
;
306 unsigned vertex_count
;
308 if (device
->quirks
& IS_BIFROST
) {
309 vertex_postfix
.gl_enables
= 0x2;
310 tiler_postfix
.gl_enables
= 0x3;
311 vertex_postfix
.shared_memory
= panfrost_vt_emit_shared_memory(batch
);
313 vertex_postfix
.gl_enables
= 0x6;
314 tiler_postfix
.gl_enables
= 0x7;
315 vertex_postfix
.shared_memory
= panfrost_batch_reserve_framebuffer(batch
);
318 tiler_postfix
.shared_memory
= vertex_postfix
.shared_memory
;
320 if (ctx
->occlusion_query
) {
321 tiler_postfix
.gl_enables
|= MALI_OCCLUSION_QUERY
;
322 tiler_postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
323 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
324 PAN_BO_ACCESS_SHARED
|
326 PAN_BO_ACCESS_FRAGMENT
);
329 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
330 SET_BIT(tiler_postfix
.gl_enables
, MALI_FRONT_CCW_TOP
,
332 SET_BIT(tiler_postfix
.gl_enables
, MALI_CULL_FACE_FRONT
,
333 (rast
->cull_face
& PIPE_FACE_FRONT
));
334 SET_BIT(tiler_postfix
.gl_enables
, MALI_CULL_FACE_BACK
,
335 (rast
->cull_face
& PIPE_FACE_BACK
));
336 SET_BIT(tiler_prefix
.unknown_draw
, MALI_DRAW_FLATSHADE_FIRST
,
337 rast
->flatshade_first
);
339 panfrost_vt_set_draw_info(ctx
, info
, g2m_draw_mode(mode
),
340 &vertex_postfix
, &tiler_prefix
,
341 &tiler_postfix
, &vertex_count
,
344 panfrost_statistics_record(ctx
, info
);
346 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
347 1, vertex_count
, info
->instance_count
,
350 /* Emit all sort of descriptors. */
351 mali_ptr push_vert
= 0, push_frag
= 0, attribs
= 0;
353 vertex_postfix
.attribute_meta
= panfrost_emit_vertex_data(batch
, &attribs
);
354 vertex_postfix
.attributes
= attribs
;
355 panfrost_emit_varying_descriptor(batch
,
358 &vertex_postfix
, &tiler_postfix
,
360 vertex_postfix
.sampler_descriptor
= panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_VERTEX
);
361 tiler_postfix
.sampler_descriptor
= panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_FRAGMENT
);
362 vertex_postfix
.textures
= panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_VERTEX
);
363 tiler_postfix
.textures
= panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_FRAGMENT
);
364 vertex_postfix
.uniform_buffers
= panfrost_emit_const_buf(batch
, PIPE_SHADER_VERTEX
, &push_vert
);
365 tiler_postfix
.uniform_buffers
= panfrost_emit_const_buf(batch
, PIPE_SHADER_FRAGMENT
, &push_frag
);
366 vertex_postfix
.uniforms
= push_vert
;
367 tiler_postfix
.uniforms
= push_frag
;
368 tiler_postfix
.viewport
= panfrost_emit_viewport(batch
);
370 vertex_postfix
.shader
= panfrost_emit_compute_shader_meta(batch
, PIPE_SHADER_VERTEX
);
371 tiler_postfix
.shader
= panfrost_emit_frag_shader_meta(batch
);
373 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
375 /* Fire off the draw itself */
376 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
377 &tiler_prefix
, &tiler_postfix
,
380 /* Adjust the batch stack size based on the new shader stack sizes. */
381 panfrost_batch_adjust_stack_size(batch
);
383 /* Increment transform feedback offsets */
384 panfrost_update_streamout_offsets(ctx
);
390 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
396 panfrost_create_rasterizer_state(
397 struct pipe_context
*pctx
,
398 const struct pipe_rasterizer_state
*cso
)
400 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
404 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
405 assert(cso
->offset_clamp
== 0.0);
411 panfrost_bind_rasterizer_state(
412 struct pipe_context
*pctx
,
415 struct panfrost_context
*ctx
= pan_context(pctx
);
417 ctx
->rasterizer
= hwcso
;
422 /* Point sprites are emulated */
424 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
426 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
427 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
431 panfrost_create_vertex_elements_state(
432 struct pipe_context
*pctx
,
433 unsigned num_elements
,
434 const struct pipe_vertex_element
*elements
)
436 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
437 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
439 so
->num_elements
= num_elements
;
440 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
442 for (int i
= 0; i
< num_elements
; ++i
) {
443 enum pipe_format fmt
= elements
[i
].src_format
;
444 const struct util_format_description
*desc
= util_format_description(fmt
);
445 unsigned swizzle
= 0;
446 if (dev
->quirks
& HAS_SWIZZLES
)
447 swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
449 swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
451 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
452 so
->formats
[i
] = (hw_format
<< 12) | swizzle
;
456 /* Let's also prepare vertex builtins */
457 if (dev
->quirks
& HAS_SWIZZLES
)
458 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
460 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
462 if (dev
->quirks
& HAS_SWIZZLES
)
463 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
465 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
471 panfrost_bind_vertex_elements_state(
472 struct pipe_context
*pctx
,
475 struct panfrost_context
*ctx
= pan_context(pctx
);
480 panfrost_create_shader_state(
481 struct pipe_context
*pctx
,
482 const struct pipe_shader_state
*cso
,
483 enum pipe_shader_type stage
)
485 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
486 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
489 /* Token deep copy to prevent memory corruption */
491 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
492 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
494 /* Precompile for shader-db if we need to */
495 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
496 struct panfrost_context
*ctx
= pan_context(pctx
);
498 struct panfrost_shader_state state
= { 0 };
499 uint64_t outputs_written
;
501 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
503 tgsi_processor_to_shader_stage(stage
),
504 &state
, &outputs_written
);
511 panfrost_delete_shader_state(
512 struct pipe_context
*pctx
,
515 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
517 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
518 /* TODO: leaks TGSI tokens! */
521 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
522 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
523 panfrost_bo_unreference(shader_state
->bo
);
525 if (shader_state
->upload
.rsrc
)
526 pipe_resource_reference(&shader_state
->upload
.rsrc
, NULL
);
528 shader_state
->bo
= NULL
;
537 panfrost_create_sampler_state(
538 struct pipe_context
*pctx
,
539 const struct pipe_sampler_state
*cso
)
541 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
542 struct panfrost_device
*device
= pan_device(pctx
->screen
);
546 if (device
->quirks
& IS_BIFROST
)
547 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
549 panfrost_sampler_desc_init(cso
, &so
->hw
);
555 panfrost_bind_sampler_states(
556 struct pipe_context
*pctx
,
557 enum pipe_shader_type shader
,
558 unsigned start_slot
, unsigned num_sampler
,
561 assert(start_slot
== 0);
563 struct panfrost_context
*ctx
= pan_context(pctx
);
565 /* XXX: Should upload, not just copy? */
566 ctx
->sampler_count
[shader
] = num_sampler
;
567 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
571 panfrost_variant_matches(
572 struct panfrost_context
*ctx
,
573 struct panfrost_shader_state
*variant
,
574 enum pipe_shader_type type
)
576 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
577 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
579 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
581 if (variant
->outputs_read
) {
582 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
585 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
586 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
588 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
589 fmt
= fb
->cbufs
[i
]->format
;
591 const struct util_format_description
*desc
=
592 util_format_description(fmt
);
594 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
595 fmt
= PIPE_FORMAT_NONE
;
597 if (variant
->rt_formats
[i
] != fmt
)
602 /* Point sprites TODO on bifrost, always pass */
603 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
604 variant
->point_sprite_mask
)
605 && !(dev
->quirks
& IS_BIFROST
)) {
606 /* Ensure the same varyings are turned to point sprites */
607 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
610 /* Ensure the orientation is correct */
612 rasterizer
->sprite_coord_mode
==
613 PIPE_SPRITE_COORD_UPPER_LEFT
;
615 if (variant
->point_sprite_upper_left
!= upper_left
)
619 /* Otherwise, we're good to go */
624 * Fix an uncompiled shader's stream output info, and produce a bitmask
625 * of which VARYING_SLOT_* are captured for stream output.
627 * Core Gallium stores output->register_index as a "slot" number, where
628 * slots are assigned consecutively to all outputs in info->outputs_written.
629 * This naive packing of outputs doesn't work for us - we too have slots,
630 * but the layout is defined by the VUE map, which we won't have until we
631 * compile a specific shader variant. So, we remap these and simply store
632 * VARYING_SLOT_* in our copy's output->register_index fields.
634 * We then produce a bitmask of outputs which are used for SO.
636 * Implementation from iris.
640 update_so_info(struct pipe_stream_output_info
*so_info
,
641 uint64_t outputs_written
)
643 uint64_t so_outputs
= 0;
644 uint8_t reverse_map
[64] = {0};
647 while (outputs_written
)
648 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
650 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
651 struct pipe_stream_output
*output
= &so_info
->output
[i
];
653 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
654 output
->register_index
= reverse_map
[output
->register_index
];
656 so_outputs
|= 1ull << output
->register_index
;
663 panfrost_bind_shader_state(
664 struct pipe_context
*pctx
,
666 enum pipe_shader_type type
)
668 struct panfrost_context
*ctx
= pan_context(pctx
);
669 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
670 ctx
->shader
[type
] = hwcso
;
674 /* Match the appropriate variant */
677 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
679 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
680 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
687 /* No variant matched, so create a new one */
688 variant
= variants
->variant_count
++;
690 if (variants
->variant_count
> variants
->variant_space
) {
691 unsigned old_space
= variants
->variant_space
;
693 variants
->variant_space
*= 2;
694 if (variants
->variant_space
== 0)
695 variants
->variant_space
= 1;
697 /* Arbitrary limit to stop runaway programs from
698 * creating an unbounded number of shader variants. */
699 assert(variants
->variant_space
< 1024);
701 unsigned msize
= sizeof(struct panfrost_shader_state
);
702 variants
->variants
= realloc(variants
->variants
,
703 variants
->variant_space
* msize
);
705 memset(&variants
->variants
[old_space
], 0,
706 (variants
->variant_space
- old_space
) * msize
);
709 struct panfrost_shader_state
*v
=
710 &variants
->variants
[variant
];
712 if (type
== PIPE_SHADER_FRAGMENT
) {
713 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
714 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
715 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
717 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
718 fmt
= fb
->cbufs
[i
]->format
;
720 const struct util_format_description
*desc
=
721 util_format_description(fmt
);
723 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
724 fmt
= PIPE_FORMAT_NONE
;
726 v
->rt_formats
[i
] = fmt
;
729 /* Point sprites are TODO on Bifrost */
730 if (ctx
->rasterizer
&& !(dev
->quirks
& IS_BIFROST
)) {
731 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
732 v
->point_sprite_upper_left
=
733 ctx
->rasterizer
->base
.sprite_coord_mode
==
734 PIPE_SPRITE_COORD_UPPER_LEFT
;
739 /* Select this variant */
740 variants
->active_variant
= variant
;
742 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
743 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
745 /* We finally have a variant, so compile it */
747 if (!shader_state
->compiled
) {
748 uint64_t outputs_written
= 0;
750 panfrost_shader_compile(ctx
, variants
->base
.type
,
751 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
752 variants
->base
.ir
.nir
:
753 variants
->base
.tokens
,
754 tgsi_processor_to_shader_stage(type
),
758 shader_state
->compiled
= true;
760 /* Fixup the stream out information, since what Gallium returns
761 * normally is mildly insane */
763 shader_state
->stream_output
= variants
->base
.stream_output
;
764 shader_state
->so_mask
=
765 update_so_info(&shader_state
->stream_output
, outputs_written
);
770 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
772 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
776 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
778 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
782 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
784 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
788 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
790 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
794 panfrost_set_vertex_buffers(
795 struct pipe_context
*pctx
,
797 unsigned num_buffers
,
798 const struct pipe_vertex_buffer
*buffers
)
800 struct panfrost_context
*ctx
= pan_context(pctx
);
802 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
806 panfrost_set_constant_buffer(
807 struct pipe_context
*pctx
,
808 enum pipe_shader_type shader
, uint index
,
809 const struct pipe_constant_buffer
*buf
)
811 struct panfrost_context
*ctx
= pan_context(pctx
);
812 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
814 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
816 unsigned mask
= (1 << index
);
818 if (unlikely(!buf
)) {
819 pbuf
->enabled_mask
&= ~mask
;
820 pbuf
->dirty_mask
&= ~mask
;
824 pbuf
->enabled_mask
|= mask
;
825 pbuf
->dirty_mask
|= mask
;
829 panfrost_set_stencil_ref(
830 struct pipe_context
*pctx
,
831 const struct pipe_stencil_ref
*ref
)
833 struct panfrost_context
*ctx
= pan_context(pctx
);
834 ctx
->stencil_ref
= *ref
;
838 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
839 struct pipe_context
*pctx
,
840 struct pipe_resource
*texture
)
842 struct panfrost_device
*device
= pan_device(pctx
->screen
);
843 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
844 enum pipe_format format
= so
->base
.format
;
847 /* Format to access the stencil portion of a Z32_S8 texture */
848 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
849 assert(prsrc
->separate_stencil
);
850 texture
= &prsrc
->separate_stencil
->base
;
851 prsrc
= (struct panfrost_resource
*)texture
;
852 format
= texture
->format
;
855 const struct util_format_description
*desc
= util_format_description(format
);
857 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
859 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
861 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
863 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
864 desc
= util_format_description(format
);
867 so
->texture_bo
= prsrc
->bo
->gpu
;
868 so
->modifier
= prsrc
->modifier
;
870 unsigned char user_swizzle
[4] = {
877 /* In the hardware, array_size refers specifically to array textures,
878 * whereas in Gallium, it also covers cubemaps */
880 unsigned array_size
= texture
->array_size
;
881 unsigned depth
= texture
->depth0
;
883 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
884 /* TODO: Cubemap arrays */
885 assert(array_size
== 6);
889 /* MSAA only supported for 2D textures (and 2D texture arrays via an
890 * extension currently unimplemented */
892 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
894 depth
= texture
->nr_samples
;
896 /* MSAA only supported for 2D textures */
897 assert(texture
->nr_samples
<= 1);
900 enum mali_texture_dimension type
=
901 panfrost_translate_texture_dimension(so
->base
.target
);
903 if (device
->quirks
& IS_BIFROST
) {
904 unsigned char composed_swizzle
[4];
905 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
907 unsigned size
= panfrost_estimate_texture_payload_size(
908 so
->base
.u
.tex
.first_level
,
909 so
->base
.u
.tex
.last_level
,
910 so
->base
.u
.tex
.first_layer
,
911 so
->base
.u
.tex
.last_layer
,
913 type
, prsrc
->modifier
);
915 so
->bo
= panfrost_bo_create(device
, size
, 0);
917 panfrost_new_texture_bifrost(
918 &so
->bifrost_descriptor
,
919 texture
->width0
, texture
->height0
,
922 type
, prsrc
->modifier
,
923 so
->base
.u
.tex
.first_level
,
924 so
->base
.u
.tex
.last_level
,
925 so
->base
.u
.tex
.first_layer
,
926 so
->base
.u
.tex
.last_layer
,
928 prsrc
->cubemap_stride
,
929 panfrost_translate_swizzle_4(composed_swizzle
),
934 unsigned size
= panfrost_estimate_texture_payload_size(
935 so
->base
.u
.tex
.first_level
,
936 so
->base
.u
.tex
.last_level
,
937 so
->base
.u
.tex
.first_layer
,
938 so
->base
.u
.tex
.last_layer
,
940 type
, prsrc
->modifier
);
941 size
+= MALI_MIDGARD_TEXTURE_LENGTH
;
943 so
->bo
= panfrost_bo_create(device
, size
, 0);
945 panfrost_new_texture(
947 texture
->width0
, texture
->height0
,
950 type
, prsrc
->modifier
,
951 so
->base
.u
.tex
.first_level
,
952 so
->base
.u
.tex
.last_level
,
953 so
->base
.u
.tex
.first_layer
,
954 so
->base
.u
.tex
.last_layer
,
956 prsrc
->cubemap_stride
,
957 panfrost_translate_swizzle_4(user_swizzle
),
963 static struct pipe_sampler_view
*
964 panfrost_create_sampler_view(
965 struct pipe_context
*pctx
,
966 struct pipe_resource
*texture
,
967 const struct pipe_sampler_view
*template)
969 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
971 pipe_reference(NULL
, &texture
->reference
);
973 so
->base
= *template;
974 so
->base
.texture
= texture
;
975 so
->base
.reference
.count
= 1;
976 so
->base
.context
= pctx
;
978 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
980 return (struct pipe_sampler_view
*) so
;
984 panfrost_set_sampler_views(
985 struct pipe_context
*pctx
,
986 enum pipe_shader_type shader
,
987 unsigned start_slot
, unsigned num_views
,
988 struct pipe_sampler_view
**views
)
990 struct panfrost_context
*ctx
= pan_context(pctx
);
994 assert(start_slot
== 0);
996 for (i
= 0; i
< num_views
; ++i
) {
999 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1003 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1004 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1007 ctx
->sampler_view_count
[shader
] = new_nr
;
1011 panfrost_sampler_view_destroy(
1012 struct pipe_context
*pctx
,
1013 struct pipe_sampler_view
*pview
)
1015 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1017 pipe_resource_reference(&pview
->texture
, NULL
);
1018 panfrost_bo_unreference(view
->bo
);
1023 panfrost_set_shader_buffers(
1024 struct pipe_context
*pctx
,
1025 enum pipe_shader_type shader
,
1026 unsigned start
, unsigned count
,
1027 const struct pipe_shader_buffer
*buffers
,
1028 unsigned writable_bitmask
)
1030 struct panfrost_context
*ctx
= pan_context(pctx
);
1032 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1033 buffers
, start
, count
);
1037 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1038 const struct pipe_framebuffer_state
*fb
)
1040 struct panfrost_context
*ctx
= pan_context(pctx
);
1042 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1045 /* We may need to generate a new variant if the fragment shader is
1046 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1047 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1049 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1050 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1053 static inline unsigned
1054 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1057 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1058 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1059 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1060 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1061 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1062 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1063 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1064 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1065 default: unreachable("Invalid stencil op");
1070 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1072 pan_pack(out
, STENCIL
, cfg
) {
1073 cfg
.mask
= in
->valuemask
;
1074 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1075 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1076 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1077 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1082 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1083 const struct pipe_depth_stencil_alpha_state
*zsa
)
1085 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1088 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1089 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1091 if (zsa
->stencil
[1].enabled
) {
1092 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1093 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1095 so
->stencil_back
= so
->stencil_front
;
1096 so
->stencil_mask_back
= so
->stencil_mask_front
;
1099 /* Alpha lowered by frontend */
1100 assert(!zsa
->alpha
.enabled
);
1102 /* TODO: Bounds test should be easy */
1103 assert(!zsa
->depth
.bounds_test
);
1109 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1112 struct panfrost_context
*ctx
= pan_context(pipe
);
1113 struct panfrost_zsa_state
*zsa
= cso
;
1114 ctx
->depth_stencil
= zsa
;
1118 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1124 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1125 unsigned sample_mask
)
1127 struct panfrost_context
*ctx
= pan_context(pipe
);
1128 ctx
->sample_mask
= sample_mask
;
1132 panfrost_set_min_samples(struct pipe_context
*pipe
,
1133 unsigned min_samples
)
1135 struct panfrost_context
*ctx
= pan_context(pipe
);
1136 ctx
->min_samples
= min_samples
;
1141 panfrost_set_clip_state(struct pipe_context
*pipe
,
1142 const struct pipe_clip_state
*clip
)
1144 //struct panfrost_context *panfrost = pan_context(pipe);
1148 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1149 unsigned start_slot
,
1150 unsigned num_viewports
,
1151 const struct pipe_viewport_state
*viewports
)
1153 struct panfrost_context
*ctx
= pan_context(pipe
);
1155 assert(start_slot
== 0);
1156 assert(num_viewports
== 1);
1158 ctx
->pipe_viewport
= *viewports
;
1162 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1163 unsigned start_slot
,
1164 unsigned num_scissors
,
1165 const struct pipe_scissor_state
*scissors
)
1167 struct panfrost_context
*ctx
= pan_context(pipe
);
1169 assert(start_slot
== 0);
1170 assert(num_scissors
== 1);
1172 ctx
->scissor
= *scissors
;
1176 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1177 const struct pipe_poly_stipple
*stipple
)
1179 //struct panfrost_context *panfrost = pan_context(pipe);
1183 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1186 struct panfrost_context
*ctx
= pan_context(pipe
);
1187 ctx
->active_queries
= enable
;
1191 panfrost_destroy(struct pipe_context
*pipe
)
1193 struct panfrost_context
*panfrost
= pan_context(pipe
);
1195 if (panfrost
->blitter
)
1196 util_blitter_destroy(panfrost
->blitter
);
1198 if (panfrost
->blitter_wallpaper
)
1199 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1201 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1202 u_upload_destroy(pipe
->stream_uploader
);
1203 u_upload_destroy(panfrost
->state_uploader
);
1208 static struct pipe_query
*
1209 panfrost_create_query(struct pipe_context
*pipe
,
1213 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1218 return (struct pipe_query
*) q
;
1222 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1224 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1227 panfrost_bo_unreference(query
->bo
);
1235 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1237 struct panfrost_context
*ctx
= pan_context(pipe
);
1238 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1240 switch (query
->type
) {
1241 case PIPE_QUERY_OCCLUSION_COUNTER
:
1242 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1243 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1244 /* Allocate a bo for the query results to be stored */
1246 query
->bo
= panfrost_bo_create(
1247 pan_device(ctx
->base
.screen
),
1248 sizeof(unsigned), 0);
1251 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1252 *result
= 0; /* Default to 0 if nothing at all drawn. */
1253 ctx
->occlusion_query
= query
;
1256 /* Geometry statistics are computed in the driver. XXX: geom/tess
1259 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1260 query
->start
= ctx
->prims_generated
;
1262 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1263 query
->start
= ctx
->tf_prims_generated
;
1267 /* TODO: timestamp queries, etc? */
1275 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1277 struct panfrost_context
*ctx
= pan_context(pipe
);
1278 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1280 switch (query
->type
) {
1281 case PIPE_QUERY_OCCLUSION_COUNTER
:
1282 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1283 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1284 ctx
->occlusion_query
= NULL
;
1286 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1287 query
->end
= ctx
->prims_generated
;
1289 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1290 query
->end
= ctx
->tf_prims_generated
;
1298 panfrost_get_query_result(struct pipe_context
*pipe
,
1299 struct pipe_query
*q
,
1301 union pipe_query_result
*vresult
)
1303 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1304 struct panfrost_context
*ctx
= pan_context(pipe
);
1307 switch (query
->type
) {
1308 case PIPE_QUERY_OCCLUSION_COUNTER
:
1309 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1310 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1311 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1312 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1314 /* Read back the query results */
1315 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1316 unsigned passed
= *result
;
1318 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1319 vresult
->u64
= passed
;
1321 vresult
->b
= !!passed
;
1326 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1327 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1328 panfrost_flush_all_batches(ctx
, 0);
1329 vresult
->u64
= query
->end
- query
->start
;
1333 /* TODO: more queries */
1340 static struct pipe_stream_output_target
*
1341 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1342 struct pipe_resource
*prsc
,
1343 unsigned buffer_offset
,
1344 unsigned buffer_size
)
1346 struct pipe_stream_output_target
*target
;
1348 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1353 pipe_reference_init(&target
->reference
, 1);
1354 pipe_resource_reference(&target
->buffer
, prsc
);
1356 target
->context
= pctx
;
1357 target
->buffer_offset
= buffer_offset
;
1358 target
->buffer_size
= buffer_size
;
1364 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1365 struct pipe_stream_output_target
*target
)
1367 pipe_resource_reference(&target
->buffer
, NULL
);
1368 ralloc_free(target
);
1372 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1373 unsigned num_targets
,
1374 struct pipe_stream_output_target
**targets
,
1375 const unsigned *offsets
)
1377 struct panfrost_context
*ctx
= pan_context(pctx
);
1378 struct panfrost_streamout
*so
= &ctx
->streamout
;
1380 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1382 for (unsigned i
= 0; i
< num_targets
; i
++) {
1383 if (offsets
[i
] != -1)
1384 so
->offsets
[i
] = offsets
[i
];
1386 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1389 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1390 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1392 so
->num_targets
= num_targets
;
1395 struct pipe_context
*
1396 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1398 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1399 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1400 struct panfrost_device
*dev
= pan_device(screen
);
1402 gallium
->screen
= screen
;
1404 gallium
->destroy
= panfrost_destroy
;
1406 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1408 gallium
->flush
= panfrost_flush
;
1409 gallium
->clear
= panfrost_clear
;
1410 gallium
->draw_vbo
= panfrost_draw_vbo
;
1411 gallium
->texture_barrier
= panfrost_texture_barrier
;
1413 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1414 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1415 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1417 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1419 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1420 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1421 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1423 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1424 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1425 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1427 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1428 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1429 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1431 gallium
->create_fs_state
= panfrost_create_fs_state
;
1432 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1433 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1435 gallium
->create_vs_state
= panfrost_create_vs_state
;
1436 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1437 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1439 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1440 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1441 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1443 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1444 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1445 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1447 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1448 gallium
->set_min_samples
= panfrost_set_min_samples
;
1450 gallium
->set_clip_state
= panfrost_set_clip_state
;
1451 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1452 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1453 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1454 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1456 gallium
->create_query
= panfrost_create_query
;
1457 gallium
->destroy_query
= panfrost_destroy_query
;
1458 gallium
->begin_query
= panfrost_begin_query
;
1459 gallium
->end_query
= panfrost_end_query
;
1460 gallium
->get_query_result
= panfrost_get_query_result
;
1462 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1463 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1464 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1466 panfrost_resource_context_init(gallium
);
1467 panfrost_blend_context_init(gallium
);
1468 panfrost_compute_context_init(gallium
);
1470 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1471 gallium
->const_uploader
= gallium
->stream_uploader
;
1473 ctx
->state_uploader
= u_upload_create(gallium
, 4096,
1474 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_DYNAMIC
, 0);
1476 /* All of our GPUs support ES mode. Midgard supports additionally
1477 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1479 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1481 if (!(dev
->quirks
& IS_BIFROST
)) {
1482 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1483 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1486 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1488 ctx
->blitter
= util_blitter_create(gallium
);
1489 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1491 assert(ctx
->blitter
);
1492 assert(ctx
->blitter_wallpaper
);
1494 /* Prepare for render! */
1496 panfrost_batch_init(ctx
);
1498 if (!(dev
->quirks
& IS_BIFROST
)) {
1499 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1500 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1503 /* By default mask everything on */
1504 ctx
->sample_mask
= ~0;
1505 ctx
->active_queries
= true;