panfrost: Drop panfrost_invalidate_frame
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27 #include <sys/poll.h>
28 #include <errno.h>
29
30 #include "pan_bo.h"
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
34
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
50
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
55 #include "pan_util.h"
56 #include "decode.h"
57 #include "util/pan_lower_framebuffer.h"
58
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
61 {
62 struct panfrost_device *device = pan_device(batch->ctx->base.screen);
63 bool hierarchy = !(device->quirks & MIDGARD_NO_HIER_TILING);
64 struct midgard_tiler_descriptor t = {0};
65 unsigned height = batch->key.height;
66 unsigned width = batch->key.width;
67
68 t.hierarchy_mask =
69 panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
70
71 /* Compute the polygon header size and use that to offset the body */
72
73 unsigned header_size = panfrost_tiler_header_size(
74 width, height, t.hierarchy_mask, hierarchy);
75
76 t.polygon_list_size = panfrost_tiler_full_size(
77 width, height, t.hierarchy_mask, hierarchy);
78
79 /* Sanity check */
80
81 if (vertex_count) {
82 struct panfrost_bo *tiler_heap;
83
84 tiler_heap = panfrost_batch_get_tiler_heap(batch);
85 t.polygon_list = panfrost_batch_get_polygon_list(batch,
86 header_size +
87 t.polygon_list_size);
88
89
90 /* Allow the entire tiler heap */
91 t.heap_start = tiler_heap->gpu;
92 t.heap_end = tiler_heap->gpu + tiler_heap->size;
93 } else {
94 struct panfrost_bo *tiler_dummy;
95
96 tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
97 header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
98
99 /* The tiler is disabled, so don't allow the tiler heap */
100 t.heap_start = tiler_dummy->gpu;
101 t.heap_end = t.heap_start;
102
103 /* Use a dummy polygon list */
104 t.polygon_list = tiler_dummy->gpu;
105
106 /* Disable the tiler */
107 if (hierarchy)
108 t.hierarchy_mask |= MALI_TILER_DISABLED;
109 else {
110 t.hierarchy_mask = MALI_TILER_USER;
111 t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
112
113 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
114 uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
115 polygon_list_body[0] = 0xa0000000; /* TODO: Just that? */
116 }
117 }
118
119 t.polygon_list_body =
120 t.polygon_list + header_size;
121
122 return t;
123 }
124
125 static void
126 panfrost_clear(
127 struct pipe_context *pipe,
128 unsigned buffers,
129 const struct pipe_scissor_state *scissor_state,
130 const union pipe_color_union *color,
131 double depth, unsigned stencil)
132 {
133 struct panfrost_context *ctx = pan_context(pipe);
134
135 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
136 * the existing batch targeting this FBO has draws. We could probably
137 * avoid that by replacing plain clears by quad-draws with a specific
138 * color/depth/stencil value, thus avoiding the generation of extra
139 * fragment jobs.
140 */
141 struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx);
142
143 panfrost_batch_add_fbo_bos(batch);
144 panfrost_batch_clear(batch, buffers, color, depth, stencil);
145 }
146
147 bool
148 panfrost_writes_point_size(struct panfrost_context *ctx)
149 {
150 assert(ctx->shader[PIPE_SHADER_VERTEX]);
151 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
152
153 return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
154 }
155
156 /* Compute number of UBOs active (more specifically, compute the highest UBO
157 * number addressable -- if there are gaps, include them in the count anyway).
158 * We always include UBO #0 in the count, since we *need* uniforms enabled for
159 * sysvals. */
160
161 unsigned
162 panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
163 {
164 unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
165 return 32 - __builtin_clz(mask);
166 }
167
168 /* The entire frame is in memory -- send it off to the kernel! */
169
170 void
171 panfrost_flush(
172 struct pipe_context *pipe,
173 struct pipe_fence_handle **fence,
174 unsigned flags)
175 {
176 struct panfrost_context *ctx = pan_context(pipe);
177 struct panfrost_device *dev = pan_device(pipe->screen);
178 uint32_t syncobj = 0;
179
180 if (fence)
181 drmSyncobjCreate(dev->fd, 0, &syncobj);
182
183 /* Submit all pending jobs */
184 panfrost_flush_all_batches(ctx, syncobj);
185
186 if (fence) {
187 struct panfrost_fence *f = panfrost_fence_create(ctx, syncobj);
188 pipe->screen->fence_reference(pipe->screen, fence, NULL);
189 *fence = (struct pipe_fence_handle *)f;
190 }
191
192 if (dev->debug & PAN_DBG_TRACE)
193 pandecode_next_frame();
194 }
195
196 static void
197 panfrost_texture_barrier(struct pipe_context *pipe, unsigned flags)
198 {
199 struct panfrost_context *ctx = pan_context(pipe);
200 panfrost_flush_all_batches(ctx, 0);
201 }
202
203 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
204
205 static int
206 g2m_draw_mode(enum pipe_prim_type mode)
207 {
208 switch (mode) {
209 DEFINE_CASE(POINTS);
210 DEFINE_CASE(LINES);
211 DEFINE_CASE(LINE_LOOP);
212 DEFINE_CASE(LINE_STRIP);
213 DEFINE_CASE(TRIANGLES);
214 DEFINE_CASE(TRIANGLE_STRIP);
215 DEFINE_CASE(TRIANGLE_FAN);
216 DEFINE_CASE(QUADS);
217 DEFINE_CASE(QUAD_STRIP);
218 DEFINE_CASE(POLYGON);
219
220 default:
221 unreachable("Invalid draw mode");
222 }
223 }
224
225 #undef DEFINE_CASE
226
227 static bool
228 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
229 {
230 const struct pipe_scissor_state *ss = &ctx->scissor;
231
232 /* Check if we're scissoring at all */
233
234 if (!ctx->rasterizer->base.scissor)
235 return false;
236
237 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
238 }
239
240 /* Count generated primitives (when there is no geom/tess shaders) for
241 * transform feedback */
242
243 static void
244 panfrost_statistics_record(
245 struct panfrost_context *ctx,
246 const struct pipe_draw_info *info)
247 {
248 if (!ctx->active_queries)
249 return;
250
251 uint32_t prims = u_prims_for_vertices(info->mode, info->count);
252 ctx->prims_generated += prims;
253
254 if (!ctx->streamout.num_targets)
255 return;
256
257 ctx->tf_prims_generated += prims;
258 }
259
260 static void
261 panfrost_update_streamout_offsets(struct panfrost_context *ctx)
262 {
263 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
264 unsigned count;
265
266 count = u_stream_outputs_for_vertices(ctx->active_prim,
267 ctx->vertex_count);
268 ctx->streamout.offsets[i] += count;
269 }
270 }
271
272 static void
273 panfrost_draw_vbo(
274 struct pipe_context *pipe,
275 const struct pipe_draw_info *info)
276 {
277 struct panfrost_context *ctx = pan_context(pipe);
278
279 /* First of all, check the scissor to see if anything is drawn at all.
280 * If it's not, we drop the draw (mostly a conformance issue;
281 * well-behaved apps shouldn't hit this) */
282
283 if (panfrost_scissor_culls_everything(ctx))
284 return;
285
286 int mode = info->mode;
287
288 /* Fallback unsupported restart index */
289 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
290
291 if (info->primitive_restart && info->index_size
292 && info->restart_index != primitive_index) {
293 util_draw_vbo_without_prim_restart(pipe, info);
294 return;
295 }
296
297 /* Fallback for unsupported modes */
298
299 assert(ctx->rasterizer != NULL);
300
301 if (!(ctx->draw_modes & (1 << mode))) {
302 if (mode == PIPE_PRIM_QUADS && info->count == 4 && !ctx->rasterizer->base.flatshade) {
303 mode = PIPE_PRIM_TRIANGLE_FAN;
304 } else {
305 if (info->count < 4) {
306 /* Degenerate case? */
307 return;
308 }
309
310 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
311 util_primconvert_draw_vbo(ctx->primconvert, info);
312 return;
313 }
314 }
315
316 /* Now that we have a guaranteed terminating path, find the job.
317 * Assignment commented out to prevent unused warning */
318
319 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
320
321 panfrost_batch_add_fbo_bos(batch);
322 panfrost_batch_set_requirements(batch);
323
324 /* Take into account a negative bias */
325 ctx->vertex_count = info->count + abs(info->index_bias);
326 ctx->instance_count = info->instance_count;
327 ctx->active_prim = info->mode;
328
329 struct mali_vertex_tiler_prefix vertex_prefix, tiler_prefix;
330 struct mali_vertex_tiler_postfix vertex_postfix, tiler_postfix;
331 union midgard_primitive_size primitive_size;
332 unsigned vertex_count;
333
334 panfrost_vt_init(ctx, PIPE_SHADER_VERTEX, &vertex_prefix, &vertex_postfix);
335 panfrost_vt_init(ctx, PIPE_SHADER_FRAGMENT, &tiler_prefix, &tiler_postfix);
336
337 panfrost_vt_set_draw_info(ctx, info, g2m_draw_mode(mode),
338 &vertex_postfix, &tiler_prefix,
339 &tiler_postfix, &vertex_count,
340 &ctx->padded_count);
341
342 panfrost_statistics_record(ctx, info);
343
344 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
345 * vertex_count, 1) */
346
347 panfrost_pack_work_groups_fused(&vertex_prefix, &tiler_prefix,
348 1, vertex_count, info->instance_count,
349 1, 1, 1);
350
351 /* Emit all sort of descriptors. */
352 panfrost_emit_vertex_data(batch, &vertex_postfix);
353 panfrost_emit_varying_descriptor(batch,
354 ctx->padded_count *
355 ctx->instance_count,
356 &vertex_postfix, &tiler_postfix,
357 &primitive_size);
358 panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
359 panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
360 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
361 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
362 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
363 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
364 panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
365 panfrost_emit_const_buf(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
366 panfrost_emit_viewport(batch, &tiler_postfix);
367
368 panfrost_vt_update_primitive_size(ctx, &tiler_prefix, &primitive_size);
369
370 /* Fire off the draw itself */
371 panfrost_emit_vertex_tiler_jobs(batch, &vertex_prefix, &vertex_postfix,
372 &tiler_prefix, &tiler_postfix,
373 &primitive_size);
374
375 /* Adjust the batch stack size based on the new shader stack sizes. */
376 panfrost_batch_adjust_stack_size(batch);
377
378 /* Increment transform feedback offsets */
379 panfrost_update_streamout_offsets(ctx);
380 }
381
382 /* CSO state */
383
384 static void
385 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
386 {
387 free(hwcso);
388 }
389
390 static void *
391 panfrost_create_rasterizer_state(
392 struct pipe_context *pctx,
393 const struct pipe_rasterizer_state *cso)
394 {
395 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
396
397 so->base = *cso;
398
399 return so;
400 }
401
402 static void
403 panfrost_bind_rasterizer_state(
404 struct pipe_context *pctx,
405 void *hwcso)
406 {
407 struct panfrost_context *ctx = pan_context(pctx);
408
409 ctx->rasterizer = hwcso;
410
411 if (!hwcso)
412 return;
413
414 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
415 assert(ctx->rasterizer->base.offset_clamp == 0.0);
416
417 /* Point sprites are emulated */
418
419 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
420
421 if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
422 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
423 }
424
425 static void *
426 panfrost_create_vertex_elements_state(
427 struct pipe_context *pctx,
428 unsigned num_elements,
429 const struct pipe_vertex_element *elements)
430 {
431 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
432 struct panfrost_device *dev = pan_device(pctx->screen);
433
434 so->num_elements = num_elements;
435 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
436
437 for (int i = 0; i < num_elements; ++i) {
438 enum pipe_format fmt = elements[i].src_format;
439 const struct util_format_description *desc = util_format_description(fmt);
440 unsigned swizzle = 0;
441 if (dev->quirks & HAS_SWIZZLES)
442 swizzle = panfrost_translate_swizzle_4(desc->swizzle);
443 else
444 swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
445
446 enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
447 so->formats[i] = (hw_format << 12) | swizzle;
448 assert(hw_format);
449 }
450
451 /* Let's also prepare vertex builtins */
452 if (dev->quirks & HAS_SWIZZLES)
453 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
454 else
455 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
456
457 if (dev->quirks & HAS_SWIZZLES)
458 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
459 else
460 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
461
462 return so;
463 }
464
465 static void
466 panfrost_bind_vertex_elements_state(
467 struct pipe_context *pctx,
468 void *hwcso)
469 {
470 struct panfrost_context *ctx = pan_context(pctx);
471 ctx->vertex = hwcso;
472 }
473
474 static void *
475 panfrost_create_shader_state(
476 struct pipe_context *pctx,
477 const struct pipe_shader_state *cso,
478 enum pipe_shader_type stage)
479 {
480 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
481 struct panfrost_device *dev = pan_device(pctx->screen);
482 so->base = *cso;
483
484 /* Token deep copy to prevent memory corruption */
485
486 if (cso->type == PIPE_SHADER_IR_TGSI)
487 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
488
489 /* Precompile for shader-db if we need to */
490 if (unlikely((dev->debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
491 struct panfrost_context *ctx = pan_context(pctx);
492
493 struct panfrost_shader_state state;
494 uint64_t outputs_written;
495
496 panfrost_shader_compile(ctx, PIPE_SHADER_IR_NIR,
497 so->base.ir.nir,
498 tgsi_processor_to_shader_stage(stage),
499 &state, &outputs_written);
500 }
501
502 return so;
503 }
504
505 static void
506 panfrost_delete_shader_state(
507 struct pipe_context *pctx,
508 void *so)
509 {
510 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
511
512 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
513 /* TODO: leaks TGSI tokens! */
514 }
515
516 for (unsigned i = 0; i < cso->variant_count; ++i) {
517 struct panfrost_shader_state *shader_state = &cso->variants[i];
518 panfrost_bo_unreference(shader_state->bo);
519 shader_state->bo = NULL;
520 }
521 free(cso->variants);
522
523 free(so);
524 }
525
526 static void *
527 panfrost_create_sampler_state(
528 struct pipe_context *pctx,
529 const struct pipe_sampler_state *cso)
530 {
531 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
532 struct panfrost_device *device = pan_device(pctx->screen);
533
534 so->base = *cso;
535
536 if (device->quirks & IS_BIFROST)
537 panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw);
538 else
539 panfrost_sampler_desc_init(cso, &so->hw);
540
541 return so;
542 }
543
544 static void
545 panfrost_bind_sampler_states(
546 struct pipe_context *pctx,
547 enum pipe_shader_type shader,
548 unsigned start_slot, unsigned num_sampler,
549 void **sampler)
550 {
551 assert(start_slot == 0);
552
553 struct panfrost_context *ctx = pan_context(pctx);
554
555 /* XXX: Should upload, not just copy? */
556 ctx->sampler_count[shader] = num_sampler;
557 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
558 }
559
560 static bool
561 panfrost_variant_matches(
562 struct panfrost_context *ctx,
563 struct panfrost_shader_state *variant,
564 enum pipe_shader_type type)
565 {
566 struct panfrost_device *dev = pan_device(ctx->base.screen);
567 struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
568
569 bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
570
571 if (variant->outputs_read) {
572 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
573
574 unsigned i;
575 BITSET_FOREACH_SET(i, &variant->outputs_read, 8) {
576 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
577
578 if ((fb->nr_cbufs > i) && fb->cbufs[i])
579 fmt = fb->cbufs[i]->format;
580
581 const struct util_format_description *desc =
582 util_format_description(fmt);
583
584 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
585 fmt = PIPE_FORMAT_NONE;
586
587 if (variant->rt_formats[i] != fmt)
588 return false;
589 }
590 }
591
592 /* Point sprites TODO on bifrost, always pass */
593 if (is_fragment && rasterizer && (rasterizer->sprite_coord_enable |
594 variant->point_sprite_mask)
595 && !(dev->quirks & IS_BIFROST)) {
596 /* Ensure the same varyings are turned to point sprites */
597 if (rasterizer->sprite_coord_enable != variant->point_sprite_mask)
598 return false;
599
600 /* Ensure the orientation is correct */
601 bool upper_left =
602 rasterizer->sprite_coord_mode ==
603 PIPE_SPRITE_COORD_UPPER_LEFT;
604
605 if (variant->point_sprite_upper_left != upper_left)
606 return false;
607 }
608
609 /* Otherwise, we're good to go */
610 return true;
611 }
612
613 /**
614 * Fix an uncompiled shader's stream output info, and produce a bitmask
615 * of which VARYING_SLOT_* are captured for stream output.
616 *
617 * Core Gallium stores output->register_index as a "slot" number, where
618 * slots are assigned consecutively to all outputs in info->outputs_written.
619 * This naive packing of outputs doesn't work for us - we too have slots,
620 * but the layout is defined by the VUE map, which we won't have until we
621 * compile a specific shader variant. So, we remap these and simply store
622 * VARYING_SLOT_* in our copy's output->register_index fields.
623 *
624 * We then produce a bitmask of outputs which are used for SO.
625 *
626 * Implementation from iris.
627 */
628
629 static uint64_t
630 update_so_info(struct pipe_stream_output_info *so_info,
631 uint64_t outputs_written)
632 {
633 uint64_t so_outputs = 0;
634 uint8_t reverse_map[64] = {0};
635 unsigned slot = 0;
636
637 while (outputs_written)
638 reverse_map[slot++] = u_bit_scan64(&outputs_written);
639
640 for (unsigned i = 0; i < so_info->num_outputs; i++) {
641 struct pipe_stream_output *output = &so_info->output[i];
642
643 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
644 output->register_index = reverse_map[output->register_index];
645
646 so_outputs |= 1ull << output->register_index;
647 }
648
649 return so_outputs;
650 }
651
652 static void
653 panfrost_bind_shader_state(
654 struct pipe_context *pctx,
655 void *hwcso,
656 enum pipe_shader_type type)
657 {
658 struct panfrost_context *ctx = pan_context(pctx);
659 struct panfrost_device *dev = pan_device(ctx->base.screen);
660 ctx->shader[type] = hwcso;
661
662 if (!hwcso) return;
663
664 /* Match the appropriate variant */
665
666 signed variant = -1;
667 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
668
669 for (unsigned i = 0; i < variants->variant_count; ++i) {
670 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
671 variant = i;
672 break;
673 }
674 }
675
676 if (variant == -1) {
677 /* No variant matched, so create a new one */
678 variant = variants->variant_count++;
679
680 if (variants->variant_count > variants->variant_space) {
681 unsigned old_space = variants->variant_space;
682
683 variants->variant_space *= 2;
684 if (variants->variant_space == 0)
685 variants->variant_space = 1;
686
687 /* Arbitrary limit to stop runaway programs from
688 * creating an unbounded number of shader variants. */
689 assert(variants->variant_space < 1024);
690
691 unsigned msize = sizeof(struct panfrost_shader_state);
692 variants->variants = realloc(variants->variants,
693 variants->variant_space * msize);
694
695 memset(&variants->variants[old_space], 0,
696 (variants->variant_space - old_space) * msize);
697 }
698
699 struct panfrost_shader_state *v =
700 &variants->variants[variant];
701
702 if (type == PIPE_SHADER_FRAGMENT) {
703 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
704 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
705 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
706
707 if ((fb->nr_cbufs > i) && fb->cbufs[i])
708 fmt = fb->cbufs[i]->format;
709
710 const struct util_format_description *desc =
711 util_format_description(fmt);
712
713 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
714 fmt = PIPE_FORMAT_NONE;
715
716 v->rt_formats[i] = fmt;
717 }
718
719 /* Point sprites are TODO on Bifrost */
720 if (ctx->rasterizer && !(dev->quirks & IS_BIFROST)) {
721 v->point_sprite_mask = ctx->rasterizer->base.sprite_coord_enable;
722 v->point_sprite_upper_left =
723 ctx->rasterizer->base.sprite_coord_mode ==
724 PIPE_SPRITE_COORD_UPPER_LEFT;
725 }
726 }
727 }
728
729 /* Select this variant */
730 variants->active_variant = variant;
731
732 struct panfrost_shader_state *shader_state = &variants->variants[variant];
733 assert(panfrost_variant_matches(ctx, shader_state, type));
734
735 /* We finally have a variant, so compile it */
736
737 if (!shader_state->compiled) {
738 uint64_t outputs_written = 0;
739
740 panfrost_shader_compile(ctx, variants->base.type,
741 variants->base.type == PIPE_SHADER_IR_NIR ?
742 variants->base.ir.nir :
743 variants->base.tokens,
744 tgsi_processor_to_shader_stage(type),
745 shader_state,
746 &outputs_written);
747
748 shader_state->compiled = true;
749
750 /* Fixup the stream out information, since what Gallium returns
751 * normally is mildly insane */
752
753 shader_state->stream_output = variants->base.stream_output;
754 shader_state->so_mask =
755 update_so_info(&shader_state->stream_output, outputs_written);
756 }
757 }
758
759 static void *
760 panfrost_create_vs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
761 {
762 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
763 }
764
765 static void *
766 panfrost_create_fs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
767 {
768 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
769 }
770
771 static void
772 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
773 {
774 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
775 }
776
777 static void
778 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
779 {
780 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
781 }
782
783 static void
784 panfrost_set_vertex_buffers(
785 struct pipe_context *pctx,
786 unsigned start_slot,
787 unsigned num_buffers,
788 const struct pipe_vertex_buffer *buffers)
789 {
790 struct panfrost_context *ctx = pan_context(pctx);
791
792 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
793 }
794
795 static void
796 panfrost_set_constant_buffer(
797 struct pipe_context *pctx,
798 enum pipe_shader_type shader, uint index,
799 const struct pipe_constant_buffer *buf)
800 {
801 struct panfrost_context *ctx = pan_context(pctx);
802 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
803
804 util_copy_constant_buffer(&pbuf->cb[index], buf);
805
806 unsigned mask = (1 << index);
807
808 if (unlikely(!buf)) {
809 pbuf->enabled_mask &= ~mask;
810 pbuf->dirty_mask &= ~mask;
811 return;
812 }
813
814 pbuf->enabled_mask |= mask;
815 pbuf->dirty_mask |= mask;
816 }
817
818 static void
819 panfrost_set_stencil_ref(
820 struct pipe_context *pctx,
821 const struct pipe_stencil_ref *ref)
822 {
823 struct panfrost_context *ctx = pan_context(pctx);
824 ctx->stencil_ref = *ref;
825 }
826
827 void
828 panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
829 struct pipe_context *pctx,
830 struct pipe_resource *texture)
831 {
832 struct panfrost_device *device = pan_device(pctx->screen);
833 struct panfrost_resource *prsrc = (struct panfrost_resource *)texture;
834 enum pipe_format format = so->base.format;
835 assert(prsrc->bo);
836
837 /* Format to access the stencil portion of a Z32_S8 texture */
838 if (format == PIPE_FORMAT_X32_S8X24_UINT) {
839 assert(prsrc->separate_stencil);
840 texture = &prsrc->separate_stencil->base;
841 prsrc = (struct panfrost_resource *)texture;
842 format = texture->format;
843 }
844
845 const struct util_format_description *desc = util_format_description(format);
846
847 bool fake_rgtc = !panfrost_supports_compressed_format(device, MALI_BC4_UNORM);
848
849 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC && fake_rgtc) {
850 if (desc->is_snorm)
851 format = PIPE_FORMAT_R8G8B8A8_SNORM;
852 else
853 format = PIPE_FORMAT_R8G8B8A8_UNORM;
854 desc = util_format_description(format);
855 }
856
857 so->texture_bo = prsrc->bo->gpu;
858 so->modifier = prsrc->modifier;
859
860 unsigned char user_swizzle[4] = {
861 so->base.swizzle_r,
862 so->base.swizzle_g,
863 so->base.swizzle_b,
864 so->base.swizzle_a
865 };
866
867 /* In the hardware, array_size refers specifically to array textures,
868 * whereas in Gallium, it also covers cubemaps */
869
870 unsigned array_size = texture->array_size;
871 unsigned depth = texture->depth0;
872
873 if (so->base.target == PIPE_TEXTURE_CUBE) {
874 /* TODO: Cubemap arrays */
875 assert(array_size == 6);
876 array_size /= 6;
877 }
878
879 /* MSAA only supported for 2D textures (and 2D texture arrays via an
880 * extension currently unimplemented */
881
882 if (so->base.target == PIPE_TEXTURE_2D) {
883 assert(depth == 1);
884 depth = texture->nr_samples;
885 } else {
886 /* MSAA only supported for 2D textures */
887 assert(texture->nr_samples <= 1);
888 }
889
890 enum mali_texture_dimension type =
891 panfrost_translate_texture_dimension(so->base.target);
892
893 if (device->quirks & IS_BIFROST) {
894 unsigned char composed_swizzle[4];
895 util_format_compose_swizzles(desc->swizzle, user_swizzle, composed_swizzle);
896
897 unsigned size = panfrost_estimate_texture_payload_size(
898 so->base.u.tex.first_level,
899 so->base.u.tex.last_level,
900 so->base.u.tex.first_layer,
901 so->base.u.tex.last_layer,
902 texture->nr_samples,
903 type, prsrc->modifier);
904
905 so->bo = panfrost_bo_create(device, size, 0);
906
907 panfrost_new_texture_bifrost(
908 &so->bifrost_descriptor,
909 texture->width0, texture->height0,
910 depth, array_size,
911 format,
912 type, prsrc->modifier,
913 so->base.u.tex.first_level,
914 so->base.u.tex.last_level,
915 so->base.u.tex.first_layer,
916 so->base.u.tex.last_layer,
917 texture->nr_samples,
918 prsrc->cubemap_stride,
919 panfrost_translate_swizzle_4(composed_swizzle),
920 prsrc->bo->gpu,
921 prsrc->slices,
922 so->bo);
923 } else {
924 unsigned size = panfrost_estimate_texture_payload_size(
925 so->base.u.tex.first_level,
926 so->base.u.tex.last_level,
927 so->base.u.tex.first_layer,
928 so->base.u.tex.last_layer,
929 texture->nr_samples,
930 type, prsrc->modifier);
931 size += MALI_MIDGARD_TEXTURE_LENGTH;
932
933 so->bo = panfrost_bo_create(device, size, 0);
934
935 panfrost_new_texture(
936 so->bo->cpu,
937 texture->width0, texture->height0,
938 depth, array_size,
939 format,
940 type, prsrc->modifier,
941 so->base.u.tex.first_level,
942 so->base.u.tex.last_level,
943 so->base.u.tex.first_layer,
944 so->base.u.tex.last_layer,
945 texture->nr_samples,
946 prsrc->cubemap_stride,
947 panfrost_translate_swizzle_4(user_swizzle),
948 prsrc->bo->gpu,
949 prsrc->slices);
950 }
951 }
952
953 static struct pipe_sampler_view *
954 panfrost_create_sampler_view(
955 struct pipe_context *pctx,
956 struct pipe_resource *texture,
957 const struct pipe_sampler_view *template)
958 {
959 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
960
961 pipe_reference(NULL, &texture->reference);
962
963 so->base = *template;
964 so->base.texture = texture;
965 so->base.reference.count = 1;
966 so->base.context = pctx;
967
968 panfrost_create_sampler_view_bo(so, pctx, texture);
969
970 return (struct pipe_sampler_view *) so;
971 }
972
973 static void
974 panfrost_set_sampler_views(
975 struct pipe_context *pctx,
976 enum pipe_shader_type shader,
977 unsigned start_slot, unsigned num_views,
978 struct pipe_sampler_view **views)
979 {
980 struct panfrost_context *ctx = pan_context(pctx);
981 unsigned new_nr = 0;
982 unsigned i;
983
984 assert(start_slot == 0);
985
986 for (i = 0; i < num_views; ++i) {
987 if (views[i])
988 new_nr = i + 1;
989 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
990 views[i]);
991 }
992
993 for (; i < ctx->sampler_view_count[shader]; i++) {
994 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
995 NULL);
996 }
997 ctx->sampler_view_count[shader] = new_nr;
998 }
999
1000 static void
1001 panfrost_sampler_view_destroy(
1002 struct pipe_context *pctx,
1003 struct pipe_sampler_view *pview)
1004 {
1005 struct panfrost_sampler_view *view = (struct panfrost_sampler_view *) pview;
1006
1007 pipe_resource_reference(&pview->texture, NULL);
1008 panfrost_bo_unreference(view->bo);
1009 ralloc_free(view);
1010 }
1011
1012 static void
1013 panfrost_set_shader_buffers(
1014 struct pipe_context *pctx,
1015 enum pipe_shader_type shader,
1016 unsigned start, unsigned count,
1017 const struct pipe_shader_buffer *buffers,
1018 unsigned writable_bitmask)
1019 {
1020 struct panfrost_context *ctx = pan_context(pctx);
1021
1022 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
1023 buffers, start, count);
1024 }
1025
1026 static void
1027 panfrost_set_framebuffer_state(struct pipe_context *pctx,
1028 const struct pipe_framebuffer_state *fb)
1029 {
1030 struct panfrost_context *ctx = pan_context(pctx);
1031
1032 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
1033 ctx->batch = NULL;
1034
1035 /* We may need to generate a new variant if the fragment shader is
1036 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1037 struct panfrost_shader_variants *fs = ctx->shader[PIPE_SHADER_FRAGMENT];
1038
1039 if (fs && fs->variant_count && fs->variants[fs->active_variant].outputs_read)
1040 ctx->base.bind_fs_state(&ctx->base, fs);
1041 }
1042
1043 static inline unsigned
1044 pan_pipe_to_stencil_op(enum pipe_stencil_op in)
1045 {
1046 switch (in) {
1047 case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
1048 case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
1049 case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
1050 case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
1051 case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
1052 case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
1053 case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
1054 case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
1055 default: unreachable("Invalid stencil op");
1056 }
1057 }
1058
1059 static inline void
1060 pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
1061 {
1062 pan_pack(out, STENCIL, cfg) {
1063 cfg.mask = in->valuemask;
1064 cfg.compare_function = panfrost_translate_compare_func(in->func);
1065 cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
1066 cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
1067 cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
1068 }
1069 }
1070
1071 static void *
1072 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
1073 const struct pipe_depth_stencil_alpha_state *zsa)
1074 {
1075 struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
1076 so->base = *zsa;
1077
1078 pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
1079 pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
1080
1081 so->stencil_mask_front = zsa->stencil[0].writemask;
1082
1083 if (zsa->stencil[1].enabled)
1084 so->stencil_mask_back = zsa->stencil[1].writemask;
1085 else
1086 so->stencil_mask_back = so->stencil_mask_front;
1087
1088 /* Alpha lowered by frontend */
1089 assert(!zsa->alpha.enabled);
1090
1091 /* TODO: Bounds test should be easy */
1092 assert(!zsa->depth.bounds_test);
1093
1094 return so;
1095 }
1096
1097 static void
1098 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
1099 void *cso)
1100 {
1101 struct panfrost_context *ctx = pan_context(pipe);
1102 struct panfrost_zsa_state *zsa = cso;
1103 ctx->depth_stencil = zsa;
1104 }
1105
1106 static void
1107 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
1108 {
1109 free( depth );
1110 }
1111
1112 static void
1113 panfrost_set_sample_mask(struct pipe_context *pipe,
1114 unsigned sample_mask)
1115 {
1116 struct panfrost_context *ctx = pan_context(pipe);
1117 ctx->sample_mask = sample_mask;
1118 }
1119
1120 static void
1121 panfrost_set_min_samples(struct pipe_context *pipe,
1122 unsigned min_samples)
1123 {
1124 struct panfrost_context *ctx = pan_context(pipe);
1125 ctx->min_samples = min_samples;
1126 }
1127
1128
1129 static void
1130 panfrost_set_clip_state(struct pipe_context *pipe,
1131 const struct pipe_clip_state *clip)
1132 {
1133 //struct panfrost_context *panfrost = pan_context(pipe);
1134 }
1135
1136 static void
1137 panfrost_set_viewport_states(struct pipe_context *pipe,
1138 unsigned start_slot,
1139 unsigned num_viewports,
1140 const struct pipe_viewport_state *viewports)
1141 {
1142 struct panfrost_context *ctx = pan_context(pipe);
1143
1144 assert(start_slot == 0);
1145 assert(num_viewports == 1);
1146
1147 ctx->pipe_viewport = *viewports;
1148 }
1149
1150 static void
1151 panfrost_set_scissor_states(struct pipe_context *pipe,
1152 unsigned start_slot,
1153 unsigned num_scissors,
1154 const struct pipe_scissor_state *scissors)
1155 {
1156 struct panfrost_context *ctx = pan_context(pipe);
1157
1158 assert(start_slot == 0);
1159 assert(num_scissors == 1);
1160
1161 ctx->scissor = *scissors;
1162 }
1163
1164 static void
1165 panfrost_set_polygon_stipple(struct pipe_context *pipe,
1166 const struct pipe_poly_stipple *stipple)
1167 {
1168 //struct panfrost_context *panfrost = pan_context(pipe);
1169 }
1170
1171 static void
1172 panfrost_set_active_query_state(struct pipe_context *pipe,
1173 bool enable)
1174 {
1175 struct panfrost_context *ctx = pan_context(pipe);
1176 ctx->active_queries = enable;
1177 }
1178
1179 static void
1180 panfrost_destroy(struct pipe_context *pipe)
1181 {
1182 struct panfrost_context *panfrost = pan_context(pipe);
1183
1184 if (panfrost->blitter)
1185 util_blitter_destroy(panfrost->blitter);
1186
1187 if (panfrost->blitter_wallpaper)
1188 util_blitter_destroy(panfrost->blitter_wallpaper);
1189
1190 util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
1191 u_upload_destroy(pipe->stream_uploader);
1192
1193 ralloc_free(pipe);
1194 }
1195
1196 static struct pipe_query *
1197 panfrost_create_query(struct pipe_context *pipe,
1198 unsigned type,
1199 unsigned index)
1200 {
1201 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
1202
1203 q->type = type;
1204 q->index = index;
1205
1206 return (struct pipe_query *) q;
1207 }
1208
1209 static void
1210 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
1211 {
1212 struct panfrost_query *query = (struct panfrost_query *) q;
1213
1214 if (query->bo) {
1215 panfrost_bo_unreference(query->bo);
1216 query->bo = NULL;
1217 }
1218
1219 ralloc_free(q);
1220 }
1221
1222 static bool
1223 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
1224 {
1225 struct panfrost_context *ctx = pan_context(pipe);
1226 struct panfrost_query *query = (struct panfrost_query *) q;
1227
1228 switch (query->type) {
1229 case PIPE_QUERY_OCCLUSION_COUNTER:
1230 case PIPE_QUERY_OCCLUSION_PREDICATE:
1231 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1232 /* Allocate a bo for the query results to be stored */
1233 if (!query->bo) {
1234 query->bo = panfrost_bo_create(
1235 pan_device(ctx->base.screen),
1236 sizeof(unsigned), 0);
1237 }
1238
1239 unsigned *result = (unsigned *)query->bo->cpu;
1240 *result = 0; /* Default to 0 if nothing at all drawn. */
1241 ctx->occlusion_query = query;
1242 break;
1243
1244 /* Geometry statistics are computed in the driver. XXX: geom/tess
1245 * shaders.. */
1246
1247 case PIPE_QUERY_PRIMITIVES_GENERATED:
1248 query->start = ctx->prims_generated;
1249 break;
1250 case PIPE_QUERY_PRIMITIVES_EMITTED:
1251 query->start = ctx->tf_prims_generated;
1252 break;
1253
1254 default:
1255 /* TODO: timestamp queries, etc? */
1256 break;
1257 }
1258
1259 return true;
1260 }
1261
1262 static bool
1263 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
1264 {
1265 struct panfrost_context *ctx = pan_context(pipe);
1266 struct panfrost_query *query = (struct panfrost_query *) q;
1267
1268 switch (query->type) {
1269 case PIPE_QUERY_OCCLUSION_COUNTER:
1270 case PIPE_QUERY_OCCLUSION_PREDICATE:
1271 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1272 ctx->occlusion_query = NULL;
1273 break;
1274 case PIPE_QUERY_PRIMITIVES_GENERATED:
1275 query->end = ctx->prims_generated;
1276 break;
1277 case PIPE_QUERY_PRIMITIVES_EMITTED:
1278 query->end = ctx->tf_prims_generated;
1279 break;
1280 }
1281
1282 return true;
1283 }
1284
1285 static bool
1286 panfrost_get_query_result(struct pipe_context *pipe,
1287 struct pipe_query *q,
1288 bool wait,
1289 union pipe_query_result *vresult)
1290 {
1291 struct panfrost_query *query = (struct panfrost_query *) q;
1292 struct panfrost_context *ctx = pan_context(pipe);
1293
1294
1295 switch (query->type) {
1296 case PIPE_QUERY_OCCLUSION_COUNTER:
1297 case PIPE_QUERY_OCCLUSION_PREDICATE:
1298 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1299 panfrost_flush_batches_accessing_bo(ctx, query->bo, false);
1300 panfrost_bo_wait(query->bo, INT64_MAX, false);
1301
1302 /* Read back the query results */
1303 unsigned *result = (unsigned *) query->bo->cpu;
1304 unsigned passed = *result;
1305
1306 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1307 vresult->u64 = passed;
1308 } else {
1309 vresult->b = !!passed;
1310 }
1311
1312 break;
1313
1314 case PIPE_QUERY_PRIMITIVES_GENERATED:
1315 case PIPE_QUERY_PRIMITIVES_EMITTED:
1316 panfrost_flush_all_batches(ctx, 0);
1317 vresult->u64 = query->end - query->start;
1318 break;
1319
1320 default:
1321 /* TODO: more queries */
1322 break;
1323 }
1324
1325 return true;
1326 }
1327
1328 static struct pipe_stream_output_target *
1329 panfrost_create_stream_output_target(struct pipe_context *pctx,
1330 struct pipe_resource *prsc,
1331 unsigned buffer_offset,
1332 unsigned buffer_size)
1333 {
1334 struct pipe_stream_output_target *target;
1335
1336 target = rzalloc(pctx, struct pipe_stream_output_target);
1337
1338 if (!target)
1339 return NULL;
1340
1341 pipe_reference_init(&target->reference, 1);
1342 pipe_resource_reference(&target->buffer, prsc);
1343
1344 target->context = pctx;
1345 target->buffer_offset = buffer_offset;
1346 target->buffer_size = buffer_size;
1347
1348 return target;
1349 }
1350
1351 static void
1352 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
1353 struct pipe_stream_output_target *target)
1354 {
1355 pipe_resource_reference(&target->buffer, NULL);
1356 ralloc_free(target);
1357 }
1358
1359 static void
1360 panfrost_set_stream_output_targets(struct pipe_context *pctx,
1361 unsigned num_targets,
1362 struct pipe_stream_output_target **targets,
1363 const unsigned *offsets)
1364 {
1365 struct panfrost_context *ctx = pan_context(pctx);
1366 struct panfrost_streamout *so = &ctx->streamout;
1367
1368 assert(num_targets <= ARRAY_SIZE(so->targets));
1369
1370 for (unsigned i = 0; i < num_targets; i++) {
1371 if (offsets[i] != -1)
1372 so->offsets[i] = offsets[i];
1373
1374 pipe_so_target_reference(&so->targets[i], targets[i]);
1375 }
1376
1377 for (unsigned i = 0; i < so->num_targets; i++)
1378 pipe_so_target_reference(&so->targets[i], NULL);
1379
1380 so->num_targets = num_targets;
1381 }
1382
1383 struct pipe_context *
1384 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
1385 {
1386 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
1387 struct pipe_context *gallium = (struct pipe_context *) ctx;
1388 struct panfrost_device *dev = pan_device(screen);
1389
1390 gallium->screen = screen;
1391
1392 gallium->destroy = panfrost_destroy;
1393
1394 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
1395
1396 gallium->flush = panfrost_flush;
1397 gallium->clear = panfrost_clear;
1398 gallium->draw_vbo = panfrost_draw_vbo;
1399 gallium->texture_barrier = panfrost_texture_barrier;
1400
1401 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
1402 gallium->set_constant_buffer = panfrost_set_constant_buffer;
1403 gallium->set_shader_buffers = panfrost_set_shader_buffers;
1404
1405 gallium->set_stencil_ref = panfrost_set_stencil_ref;
1406
1407 gallium->create_sampler_view = panfrost_create_sampler_view;
1408 gallium->set_sampler_views = panfrost_set_sampler_views;
1409 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
1410
1411 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
1412 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
1413 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
1414
1415 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
1416 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
1417 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
1418
1419 gallium->create_fs_state = panfrost_create_fs_state;
1420 gallium->delete_fs_state = panfrost_delete_shader_state;
1421 gallium->bind_fs_state = panfrost_bind_fs_state;
1422
1423 gallium->create_vs_state = panfrost_create_vs_state;
1424 gallium->delete_vs_state = panfrost_delete_shader_state;
1425 gallium->bind_vs_state = panfrost_bind_vs_state;
1426
1427 gallium->create_sampler_state = panfrost_create_sampler_state;
1428 gallium->delete_sampler_state = panfrost_generic_cso_delete;
1429 gallium->bind_sampler_states = panfrost_bind_sampler_states;
1430
1431 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
1432 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
1433 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
1434
1435 gallium->set_sample_mask = panfrost_set_sample_mask;
1436 gallium->set_min_samples = panfrost_set_min_samples;
1437
1438 gallium->set_clip_state = panfrost_set_clip_state;
1439 gallium->set_viewport_states = panfrost_set_viewport_states;
1440 gallium->set_scissor_states = panfrost_set_scissor_states;
1441 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
1442 gallium->set_active_query_state = panfrost_set_active_query_state;
1443
1444 gallium->create_query = panfrost_create_query;
1445 gallium->destroy_query = panfrost_destroy_query;
1446 gallium->begin_query = panfrost_begin_query;
1447 gallium->end_query = panfrost_end_query;
1448 gallium->get_query_result = panfrost_get_query_result;
1449
1450 gallium->create_stream_output_target = panfrost_create_stream_output_target;
1451 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
1452 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
1453
1454 panfrost_resource_context_init(gallium);
1455 panfrost_blend_context_init(gallium);
1456 panfrost_compute_context_init(gallium);
1457
1458 gallium->stream_uploader = u_upload_create_default(gallium);
1459 gallium->const_uploader = gallium->stream_uploader;
1460 assert(gallium->stream_uploader);
1461
1462 /* All of our GPUs support ES mode. Midgard supports additionally
1463 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1464
1465 ctx->draw_modes = (1 << (PIPE_PRIM_QUADS + 1)) - 1;
1466
1467 if (!(dev->quirks & IS_BIFROST)) {
1468 ctx->draw_modes |= (1 << PIPE_PRIM_QUAD_STRIP);
1469 ctx->draw_modes |= (1 << PIPE_PRIM_POLYGON);
1470 }
1471
1472 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
1473
1474 ctx->blitter = util_blitter_create(gallium);
1475 ctx->blitter_wallpaper = util_blitter_create(gallium);
1476
1477 assert(ctx->blitter);
1478 assert(ctx->blitter_wallpaper);
1479
1480 /* Prepare for render! */
1481
1482 panfrost_batch_init(ctx);
1483
1484 if (!(dev->quirks & IS_BIFROST)) {
1485 for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c)
1486 ctx->blit_blend.rt[c].shaders = _mesa_hash_table_u64_create(ctx);
1487 }
1488
1489 /* By default mask everything on */
1490 ctx->sample_mask = ~0;
1491 ctx->active_queries = true;
1492
1493 return gallium;
1494 }