2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
85 t
.heap_start
= device
->tiler_heap
->gpu
;
86 t
.heap_end
= device
->tiler_heap
->gpu
+ device
->tiler_heap
->size
;
88 struct panfrost_bo
*tiler_dummy
;
90 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
91 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t
.heap_start
= tiler_dummy
->gpu
;
95 t
.heap_end
= t
.heap_start
;
97 /* Use a dummy polygon list */
98 t
.polygon_list
= tiler_dummy
->gpu
;
100 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
104 t
.hierarchy_mask
= MALI_TILER_USER
;
105 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
109 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
113 t
.polygon_list_body
=
114 t
.polygon_list
+ header_size
;
121 struct pipe_context
*pipe
,
123 const struct pipe_scissor_state
*scissor_state
,
124 const union pipe_color_union
*color
,
125 double depth
, unsigned stencil
)
127 struct panfrost_context
*ctx
= pan_context(pipe
);
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
135 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
136 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
140 panfrost_writes_point_size(struct panfrost_context
*ctx
)
142 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
143 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
145 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
148 /* The entire frame is in memory -- send it off to the kernel! */
152 struct pipe_context
*pipe
,
153 struct pipe_fence_handle
**fence
,
156 struct panfrost_context
*ctx
= pan_context(pipe
);
157 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
158 uint32_t syncobj
= 0;
161 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
163 /* Submit all pending jobs */
164 panfrost_flush_all_batches(ctx
, syncobj
);
167 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
168 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
169 *fence
= (struct pipe_fence_handle
*)f
;
172 if (dev
->debug
& PAN_DBG_TRACE
)
173 pandecode_next_frame();
177 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
179 struct panfrost_context
*ctx
= pan_context(pipe
);
180 panfrost_flush_all_batches(ctx
, 0);
183 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
186 pan_draw_mode(enum pipe_prim_type mode
)
191 DEFINE_CASE(LINE_LOOP
);
192 DEFINE_CASE(LINE_STRIP
);
193 DEFINE_CASE(TRIANGLES
);
194 DEFINE_CASE(TRIANGLE_STRIP
);
195 DEFINE_CASE(TRIANGLE_FAN
);
197 DEFINE_CASE(QUAD_STRIP
);
198 DEFINE_CASE(POLYGON
);
201 unreachable("Invalid draw mode");
208 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
210 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
212 /* Check if we're scissoring at all */
214 if (!ctx
->rasterizer
->base
.scissor
)
217 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
220 /* Count generated primitives (when there is no geom/tess shaders) for
221 * transform feedback */
224 panfrost_statistics_record(
225 struct panfrost_context
*ctx
,
226 const struct pipe_draw_info
*info
)
228 if (!ctx
->active_queries
)
231 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
232 ctx
->prims_generated
+= prims
;
234 if (!ctx
->streamout
.num_targets
)
237 ctx
->tf_prims_generated
+= prims
;
241 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
243 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
246 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
248 ctx
->streamout
.offsets
[i
] += count
;
253 pan_emit_draw_descs(struct panfrost_batch
*batch
,
254 struct MALI_DRAW
*d
, enum pipe_shader_type st
)
256 d
->offset_start
= batch
->ctx
->offset_start
;
257 d
->instances
= batch
->ctx
->instance_count
> 1 ?
258 batch
->ctx
->padded_count
: 1;
260 d
->uniform_buffers
= panfrost_emit_const_buf(batch
, st
, &d
->push_uniforms
);
261 d
->textures
= panfrost_emit_texture_descriptors(batch
, st
);
262 d
->samplers
= panfrost_emit_sampler_descriptors(batch
, st
);
267 struct pipe_context
*pipe
,
268 const struct pipe_draw_info
*info
)
270 struct panfrost_context
*ctx
= pan_context(pipe
);
271 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
273 /* First of all, check the scissor to see if anything is drawn at all.
274 * If it's not, we drop the draw (mostly a conformance issue;
275 * well-behaved apps shouldn't hit this) */
277 if (panfrost_scissor_culls_everything(ctx
))
280 int mode
= info
->mode
;
282 /* Fallback unsupported restart index */
283 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
285 if (info
->primitive_restart
&& info
->index_size
286 && info
->restart_index
!= primitive_index
) {
287 util_draw_vbo_without_prim_restart(pipe
, info
);
291 /* Fallback for unsupported modes */
293 assert(ctx
->rasterizer
!= NULL
);
295 if (!(ctx
->draw_modes
& (1 << mode
))) {
296 if (info
->count
< 4) {
297 /* Degenerate case? */
301 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
302 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
306 /* Now that we have a guaranteed terminating path, find the job. */
308 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
309 panfrost_batch_set_requirements(batch
);
311 /* Take into account a negative bias */
312 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
313 ctx
->instance_count
= info
->instance_count
;
314 ctx
->active_prim
= info
->mode
;
316 struct mali_vertex_tiler_prefix vertex_prefix
= { 0 }, tiler_prefix
= { 0 };
317 struct mali_draw_packed vertex_postfix
, tiler_postfix
;
318 union midgard_primitive_size primitive_size
;
319 unsigned vertex_count
;
321 mali_ptr shared_mem
= (device
->quirks
& IS_BIFROST
) ?
322 panfrost_vt_emit_shared_memory(batch
) :
323 panfrost_batch_reserve_framebuffer(batch
);
325 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
326 SET_BIT(tiler_prefix
.unknown_draw
, MALI_DRAW_FLATSHADE_FIRST
,
327 rast
->flatshade_first
);
329 tiler_prefix
.draw_mode
= pan_draw_mode(mode
);
331 unsigned draw_flags
= 0x3000;
333 if (panfrost_writes_point_size(ctx
))
334 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
336 if (info
->primitive_restart
)
337 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
339 if (info
->index_size
) {
340 unsigned min_index
= 0, max_index
= 0;
342 tiler_prefix
.indices
= panfrost_get_index_buffer_bounded(ctx
,
347 /* Use the corresponding values */
348 vertex_count
= max_index
- min_index
+ 1;
349 ctx
->offset_start
= min_index
+ info
->index_bias
;
350 tiler_prefix
.offset_bias_correction
= -min_index
;
351 tiler_prefix
.index_count
= MALI_POSITIVE(info
->count
);
352 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
354 vertex_count
= ctx
->vertex_count
;
355 ctx
->offset_start
= info
->start
;
356 tiler_prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
359 tiler_prefix
.unknown_draw
= draw_flags
;
361 /* Encode the padded vertex count */
363 if (info
->instance_count
> 1)
364 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
366 ctx
->padded_count
= vertex_count
;
368 panfrost_statistics_record(ctx
, info
);
370 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
371 1, vertex_count
, info
->instance_count
,
374 /* Emit all sort of descriptors. */
375 mali_ptr varyings
= 0, vs_vary
= 0, fs_vary
= 0, pos
= 0, psiz
= 0;
377 panfrost_emit_varying_descriptor(batch
,
380 &vs_vary
, &fs_vary
, &varyings
,
383 pan_pack(&vertex_postfix
, DRAW
, cfg
) {
384 cfg
.unknown_1
= (device
->quirks
& IS_BIFROST
) ? 0x2 : 0x6;
385 cfg
.state
= panfrost_emit_compute_shader_meta(batch
, PIPE_SHADER_VERTEX
);
386 cfg
.attributes
= panfrost_emit_vertex_data(batch
, &cfg
.attribute_buffers
);
387 cfg
.varyings
= vs_vary
;
388 cfg
.varying_buffers
= varyings
;
389 cfg
.shared
= shared_mem
;
390 pan_emit_draw_descs(batch
, &cfg
, PIPE_SHADER_VERTEX
);
393 pan_pack(&tiler_postfix
, DRAW
, cfg
) {
394 cfg
.unknown_1
= (device
->quirks
& IS_BIFROST
) ? 0x3 : 0x7;
395 cfg
.front_face_ccw
= rast
->front_ccw
;
396 cfg
.cull_front_face
= rast
->cull_face
& PIPE_FACE_FRONT
;
397 cfg
.cull_back_face
= rast
->cull_face
& PIPE_FACE_BACK
;
399 cfg
.state
= panfrost_emit_frag_shader_meta(batch
);
400 cfg
.viewport
= panfrost_emit_viewport(batch
);
401 cfg
.varyings
= fs_vary
;
402 cfg
.varying_buffers
= varyings
;
403 cfg
.shared
= shared_mem
;
405 pan_emit_draw_descs(batch
, &cfg
, PIPE_SHADER_FRAGMENT
);
407 if (ctx
->occlusion_query
) {
408 cfg
.occlusion_query
= MALI_OCCLUSION_MODE_PREDICATE
;
409 cfg
.occlusion
= ctx
->occlusion_query
->bo
->gpu
;
410 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
411 PAN_BO_ACCESS_SHARED
|
413 PAN_BO_ACCESS_FRAGMENT
);
417 primitive_size
.pointer
= psiz
;
418 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
420 /* Fire off the draw itself */
421 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
422 &tiler_prefix
, &tiler_postfix
,
425 /* Adjust the batch stack size based on the new shader stack sizes. */
426 panfrost_batch_adjust_stack_size(batch
);
428 /* Increment transform feedback offsets */
429 panfrost_update_streamout_offsets(ctx
);
435 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
441 panfrost_create_rasterizer_state(
442 struct pipe_context
*pctx
,
443 const struct pipe_rasterizer_state
*cso
)
445 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
449 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
450 assert(cso
->offset_clamp
== 0.0);
456 panfrost_bind_rasterizer_state(
457 struct pipe_context
*pctx
,
460 struct panfrost_context
*ctx
= pan_context(pctx
);
461 ctx
->rasterizer
= hwcso
;
465 panfrost_create_vertex_elements_state(
466 struct pipe_context
*pctx
,
467 unsigned num_elements
,
468 const struct pipe_vertex_element
*elements
)
470 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
471 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
473 so
->num_elements
= num_elements
;
474 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
476 for (int i
= 0; i
< num_elements
; ++i
) {
477 enum pipe_format fmt
= elements
[i
].src_format
;
478 const struct util_format_description
*desc
= util_format_description(fmt
);
479 unsigned swizzle
= 0;
480 if (dev
->quirks
& HAS_SWIZZLES
)
481 swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
483 swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
485 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
486 so
->formats
[i
] = (hw_format
<< 12) | swizzle
;
490 /* Let's also prepare vertex builtins */
491 if (dev
->quirks
& HAS_SWIZZLES
)
492 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
494 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
496 if (dev
->quirks
& HAS_SWIZZLES
)
497 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
499 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
505 panfrost_bind_vertex_elements_state(
506 struct pipe_context
*pctx
,
509 struct panfrost_context
*ctx
= pan_context(pctx
);
514 panfrost_create_shader_state(
515 struct pipe_context
*pctx
,
516 const struct pipe_shader_state
*cso
,
517 enum pipe_shader_type stage
)
519 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
520 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
523 /* Token deep copy to prevent memory corruption */
525 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
526 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
528 /* Precompile for shader-db if we need to */
529 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
530 struct panfrost_context
*ctx
= pan_context(pctx
);
532 struct panfrost_shader_state state
= { 0 };
533 uint64_t outputs_written
;
535 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
537 tgsi_processor_to_shader_stage(stage
),
538 &state
, &outputs_written
);
545 panfrost_delete_shader_state(
546 struct pipe_context
*pctx
,
549 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
551 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
552 /* TODO: leaks TGSI tokens! */
555 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
556 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
557 panfrost_bo_unreference(shader_state
->bo
);
559 if (shader_state
->upload
.rsrc
)
560 pipe_resource_reference(&shader_state
->upload
.rsrc
, NULL
);
562 shader_state
->bo
= NULL
;
571 panfrost_create_sampler_state(
572 struct pipe_context
*pctx
,
573 const struct pipe_sampler_state
*cso
)
575 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
576 struct panfrost_device
*device
= pan_device(pctx
->screen
);
580 if (device
->quirks
& IS_BIFROST
)
581 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
583 panfrost_sampler_desc_init(cso
, &so
->hw
);
589 panfrost_bind_sampler_states(
590 struct pipe_context
*pctx
,
591 enum pipe_shader_type shader
,
592 unsigned start_slot
, unsigned num_sampler
,
595 assert(start_slot
== 0);
597 struct panfrost_context
*ctx
= pan_context(pctx
);
599 /* XXX: Should upload, not just copy? */
600 ctx
->sampler_count
[shader
] = num_sampler
;
601 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
605 panfrost_variant_matches(
606 struct panfrost_context
*ctx
,
607 struct panfrost_shader_state
*variant
,
608 enum pipe_shader_type type
)
610 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
612 if (variant
->outputs_read
) {
613 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
616 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
617 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
619 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
620 fmt
= fb
->cbufs
[i
]->format
;
622 const struct util_format_description
*desc
=
623 util_format_description(fmt
);
625 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
626 fmt
= PIPE_FORMAT_NONE
;
628 if (variant
->rt_formats
[i
] != fmt
)
633 /* Otherwise, we're good to go */
638 * Fix an uncompiled shader's stream output info, and produce a bitmask
639 * of which VARYING_SLOT_* are captured for stream output.
641 * Core Gallium stores output->register_index as a "slot" number, where
642 * slots are assigned consecutively to all outputs in info->outputs_written.
643 * This naive packing of outputs doesn't work for us - we too have slots,
644 * but the layout is defined by the VUE map, which we won't have until we
645 * compile a specific shader variant. So, we remap these and simply store
646 * VARYING_SLOT_* in our copy's output->register_index fields.
648 * We then produce a bitmask of outputs which are used for SO.
650 * Implementation from iris.
654 update_so_info(struct pipe_stream_output_info
*so_info
,
655 uint64_t outputs_written
)
657 uint64_t so_outputs
= 0;
658 uint8_t reverse_map
[64] = {0};
661 while (outputs_written
)
662 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
664 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
665 struct pipe_stream_output
*output
= &so_info
->output
[i
];
667 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
668 output
->register_index
= reverse_map
[output
->register_index
];
670 so_outputs
|= 1ull << output
->register_index
;
677 panfrost_bind_shader_state(
678 struct pipe_context
*pctx
,
680 enum pipe_shader_type type
)
682 struct panfrost_context
*ctx
= pan_context(pctx
);
683 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
684 ctx
->shader
[type
] = hwcso
;
688 /* Match the appropriate variant */
691 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
693 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
694 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
701 /* No variant matched, so create a new one */
702 variant
= variants
->variant_count
++;
704 if (variants
->variant_count
> variants
->variant_space
) {
705 unsigned old_space
= variants
->variant_space
;
707 variants
->variant_space
*= 2;
708 if (variants
->variant_space
== 0)
709 variants
->variant_space
= 1;
711 /* Arbitrary limit to stop runaway programs from
712 * creating an unbounded number of shader variants. */
713 assert(variants
->variant_space
< 1024);
715 unsigned msize
= sizeof(struct panfrost_shader_state
);
716 variants
->variants
= realloc(variants
->variants
,
717 variants
->variant_space
* msize
);
719 memset(&variants
->variants
[old_space
], 0,
720 (variants
->variant_space
- old_space
) * msize
);
723 struct panfrost_shader_state
*v
=
724 &variants
->variants
[variant
];
726 if (type
== PIPE_SHADER_FRAGMENT
) {
727 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
728 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
729 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
731 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
732 fmt
= fb
->cbufs
[i
]->format
;
734 const struct util_format_description
*desc
=
735 util_format_description(fmt
);
737 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
738 fmt
= PIPE_FORMAT_NONE
;
740 v
->rt_formats
[i
] = fmt
;
745 /* Select this variant */
746 variants
->active_variant
= variant
;
748 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
749 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
751 /* We finally have a variant, so compile it */
753 if (!shader_state
->compiled
) {
754 uint64_t outputs_written
= 0;
756 panfrost_shader_compile(ctx
, variants
->base
.type
,
757 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
758 variants
->base
.ir
.nir
:
759 variants
->base
.tokens
,
760 tgsi_processor_to_shader_stage(type
),
764 shader_state
->compiled
= true;
766 /* Fixup the stream out information, since what Gallium returns
767 * normally is mildly insane */
769 shader_state
->stream_output
= variants
->base
.stream_output
;
770 shader_state
->so_mask
=
771 update_so_info(&shader_state
->stream_output
, outputs_written
);
776 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
778 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
782 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
784 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
788 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
790 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
794 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
796 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
800 panfrost_set_vertex_buffers(
801 struct pipe_context
*pctx
,
803 unsigned num_buffers
,
804 const struct pipe_vertex_buffer
*buffers
)
806 struct panfrost_context
*ctx
= pan_context(pctx
);
808 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
812 panfrost_set_constant_buffer(
813 struct pipe_context
*pctx
,
814 enum pipe_shader_type shader
, uint index
,
815 const struct pipe_constant_buffer
*buf
)
817 struct panfrost_context
*ctx
= pan_context(pctx
);
818 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
820 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
822 unsigned mask
= (1 << index
);
824 if (unlikely(!buf
)) {
825 pbuf
->enabled_mask
&= ~mask
;
826 pbuf
->dirty_mask
&= ~mask
;
830 pbuf
->enabled_mask
|= mask
;
831 pbuf
->dirty_mask
|= mask
;
835 panfrost_set_stencil_ref(
836 struct pipe_context
*pctx
,
837 const struct pipe_stencil_ref
*ref
)
839 struct panfrost_context
*ctx
= pan_context(pctx
);
840 ctx
->stencil_ref
= *ref
;
844 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
845 struct pipe_context
*pctx
,
846 struct pipe_resource
*texture
)
848 struct panfrost_device
*device
= pan_device(pctx
->screen
);
849 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
850 enum pipe_format format
= so
->base
.format
;
853 /* Format to access the stencil portion of a Z32_S8 texture */
854 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
855 assert(prsrc
->separate_stencil
);
856 texture
= &prsrc
->separate_stencil
->base
;
857 prsrc
= (struct panfrost_resource
*)texture
;
858 format
= texture
->format
;
861 const struct util_format_description
*desc
= util_format_description(format
);
863 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
865 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
867 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
869 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
870 desc
= util_format_description(format
);
873 so
->texture_bo
= prsrc
->bo
->gpu
;
874 so
->modifier
= prsrc
->modifier
;
876 unsigned char user_swizzle
[4] = {
883 /* In the hardware, array_size refers specifically to array textures,
884 * whereas in Gallium, it also covers cubemaps */
886 unsigned array_size
= texture
->array_size
;
887 unsigned depth
= texture
->depth0
;
889 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
890 /* TODO: Cubemap arrays */
891 assert(array_size
== 6);
895 /* MSAA only supported for 2D textures (and 2D texture arrays via an
896 * extension currently unimplemented */
898 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
900 depth
= texture
->nr_samples
;
902 /* MSAA only supported for 2D textures */
903 assert(texture
->nr_samples
<= 1);
906 enum mali_texture_dimension type
=
907 panfrost_translate_texture_dimension(so
->base
.target
);
909 if (device
->quirks
& IS_BIFROST
) {
910 unsigned char composed_swizzle
[4];
911 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
913 unsigned size
= panfrost_estimate_texture_payload_size(
914 so
->base
.u
.tex
.first_level
,
915 so
->base
.u
.tex
.last_level
,
916 so
->base
.u
.tex
.first_layer
,
917 so
->base
.u
.tex
.last_layer
,
919 type
, prsrc
->modifier
);
921 so
->bo
= panfrost_bo_create(device
, size
, 0);
923 panfrost_new_texture_bifrost(
924 &so
->bifrost_descriptor
,
925 texture
->width0
, texture
->height0
,
928 type
, prsrc
->modifier
,
929 so
->base
.u
.tex
.first_level
,
930 so
->base
.u
.tex
.last_level
,
931 so
->base
.u
.tex
.first_layer
,
932 so
->base
.u
.tex
.last_layer
,
934 prsrc
->cubemap_stride
,
935 panfrost_translate_swizzle_4(composed_swizzle
),
940 unsigned size
= panfrost_estimate_texture_payload_size(
941 so
->base
.u
.tex
.first_level
,
942 so
->base
.u
.tex
.last_level
,
943 so
->base
.u
.tex
.first_layer
,
944 so
->base
.u
.tex
.last_layer
,
946 type
, prsrc
->modifier
);
947 size
+= MALI_MIDGARD_TEXTURE_LENGTH
;
949 so
->bo
= panfrost_bo_create(device
, size
, 0);
951 panfrost_new_texture(
953 texture
->width0
, texture
->height0
,
956 type
, prsrc
->modifier
,
957 so
->base
.u
.tex
.first_level
,
958 so
->base
.u
.tex
.last_level
,
959 so
->base
.u
.tex
.first_layer
,
960 so
->base
.u
.tex
.last_layer
,
962 prsrc
->cubemap_stride
,
963 panfrost_translate_swizzle_4(user_swizzle
),
969 static struct pipe_sampler_view
*
970 panfrost_create_sampler_view(
971 struct pipe_context
*pctx
,
972 struct pipe_resource
*texture
,
973 const struct pipe_sampler_view
*template)
975 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
977 pipe_reference(NULL
, &texture
->reference
);
979 so
->base
= *template;
980 so
->base
.texture
= texture
;
981 so
->base
.reference
.count
= 1;
982 so
->base
.context
= pctx
;
984 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
986 return (struct pipe_sampler_view
*) so
;
990 panfrost_set_sampler_views(
991 struct pipe_context
*pctx
,
992 enum pipe_shader_type shader
,
993 unsigned start_slot
, unsigned num_views
,
994 struct pipe_sampler_view
**views
)
996 struct panfrost_context
*ctx
= pan_context(pctx
);
1000 assert(start_slot
== 0);
1002 for (i
= 0; i
< num_views
; ++i
) {
1005 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1009 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1010 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1013 ctx
->sampler_view_count
[shader
] = new_nr
;
1017 panfrost_sampler_view_destroy(
1018 struct pipe_context
*pctx
,
1019 struct pipe_sampler_view
*pview
)
1021 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1023 pipe_resource_reference(&pview
->texture
, NULL
);
1024 panfrost_bo_unreference(view
->bo
);
1029 panfrost_set_shader_buffers(
1030 struct pipe_context
*pctx
,
1031 enum pipe_shader_type shader
,
1032 unsigned start
, unsigned count
,
1033 const struct pipe_shader_buffer
*buffers
,
1034 unsigned writable_bitmask
)
1036 struct panfrost_context
*ctx
= pan_context(pctx
);
1038 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1039 buffers
, start
, count
);
1043 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1044 const struct pipe_framebuffer_state
*fb
)
1046 struct panfrost_context
*ctx
= pan_context(pctx
);
1048 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1051 /* We may need to generate a new variant if the fragment shader is
1052 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1053 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1055 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1056 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1059 static inline unsigned
1060 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1063 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1064 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1065 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1066 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1067 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1068 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1069 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1070 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1071 default: unreachable("Invalid stencil op");
1076 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1078 pan_pack(out
, STENCIL
, cfg
) {
1079 cfg
.mask
= in
->valuemask
;
1080 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1081 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1082 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1083 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1088 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1089 const struct pipe_depth_stencil_alpha_state
*zsa
)
1091 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1094 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1095 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1097 if (zsa
->stencil
[1].enabled
) {
1098 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1099 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1101 so
->stencil_back
= so
->stencil_front
;
1102 so
->stencil_mask_back
= so
->stencil_mask_front
;
1105 /* Alpha lowered by frontend */
1106 assert(!zsa
->alpha
.enabled
);
1108 /* TODO: Bounds test should be easy */
1109 assert(!zsa
->depth
.bounds_test
);
1115 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1118 struct panfrost_context
*ctx
= pan_context(pipe
);
1119 ctx
->depth_stencil
= cso
;
1123 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1129 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1130 unsigned sample_mask
)
1132 struct panfrost_context
*ctx
= pan_context(pipe
);
1133 ctx
->sample_mask
= sample_mask
;
1137 panfrost_set_min_samples(struct pipe_context
*pipe
,
1138 unsigned min_samples
)
1140 struct panfrost_context
*ctx
= pan_context(pipe
);
1141 ctx
->min_samples
= min_samples
;
1146 panfrost_set_clip_state(struct pipe_context
*pipe
,
1147 const struct pipe_clip_state
*clip
)
1149 //struct panfrost_context *panfrost = pan_context(pipe);
1153 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1154 unsigned start_slot
,
1155 unsigned num_viewports
,
1156 const struct pipe_viewport_state
*viewports
)
1158 struct panfrost_context
*ctx
= pan_context(pipe
);
1160 assert(start_slot
== 0);
1161 assert(num_viewports
== 1);
1163 ctx
->pipe_viewport
= *viewports
;
1167 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1168 unsigned start_slot
,
1169 unsigned num_scissors
,
1170 const struct pipe_scissor_state
*scissors
)
1172 struct panfrost_context
*ctx
= pan_context(pipe
);
1174 assert(start_slot
== 0);
1175 assert(num_scissors
== 1);
1177 ctx
->scissor
= *scissors
;
1181 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1182 const struct pipe_poly_stipple
*stipple
)
1184 //struct panfrost_context *panfrost = pan_context(pipe);
1188 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1191 struct panfrost_context
*ctx
= pan_context(pipe
);
1192 ctx
->active_queries
= enable
;
1196 panfrost_destroy(struct pipe_context
*pipe
)
1198 struct panfrost_context
*panfrost
= pan_context(pipe
);
1200 if (panfrost
->blitter
)
1201 util_blitter_destroy(panfrost
->blitter
);
1203 if (panfrost
->blitter_wallpaper
)
1204 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1206 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1207 u_upload_destroy(pipe
->stream_uploader
);
1208 u_upload_destroy(panfrost
->state_uploader
);
1213 static struct pipe_query
*
1214 panfrost_create_query(struct pipe_context
*pipe
,
1218 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1223 return (struct pipe_query
*) q
;
1227 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1229 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1232 panfrost_bo_unreference(query
->bo
);
1240 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1242 struct panfrost_context
*ctx
= pan_context(pipe
);
1243 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1245 switch (query
->type
) {
1246 case PIPE_QUERY_OCCLUSION_COUNTER
:
1247 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1248 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1249 /* Allocate a bo for the query results to be stored */
1251 query
->bo
= panfrost_bo_create(
1252 pan_device(ctx
->base
.screen
),
1253 sizeof(unsigned), 0);
1256 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1257 *result
= 0; /* Default to 0 if nothing at all drawn. */
1258 ctx
->occlusion_query
= query
;
1261 /* Geometry statistics are computed in the driver. XXX: geom/tess
1264 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1265 query
->start
= ctx
->prims_generated
;
1267 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1268 query
->start
= ctx
->tf_prims_generated
;
1272 /* TODO: timestamp queries, etc? */
1280 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1282 struct panfrost_context
*ctx
= pan_context(pipe
);
1283 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1285 switch (query
->type
) {
1286 case PIPE_QUERY_OCCLUSION_COUNTER
:
1287 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1288 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1289 ctx
->occlusion_query
= NULL
;
1291 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1292 query
->end
= ctx
->prims_generated
;
1294 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1295 query
->end
= ctx
->tf_prims_generated
;
1303 panfrost_get_query_result(struct pipe_context
*pipe
,
1304 struct pipe_query
*q
,
1306 union pipe_query_result
*vresult
)
1308 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1309 struct panfrost_context
*ctx
= pan_context(pipe
);
1312 switch (query
->type
) {
1313 case PIPE_QUERY_OCCLUSION_COUNTER
:
1314 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1315 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1316 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1317 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1319 /* Read back the query results */
1320 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1321 unsigned passed
= *result
;
1323 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1324 vresult
->u64
= passed
;
1326 vresult
->b
= !!passed
;
1331 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1332 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1333 panfrost_flush_all_batches(ctx
, 0);
1334 vresult
->u64
= query
->end
- query
->start
;
1338 /* TODO: more queries */
1345 static struct pipe_stream_output_target
*
1346 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1347 struct pipe_resource
*prsc
,
1348 unsigned buffer_offset
,
1349 unsigned buffer_size
)
1351 struct pipe_stream_output_target
*target
;
1353 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1358 pipe_reference_init(&target
->reference
, 1);
1359 pipe_resource_reference(&target
->buffer
, prsc
);
1361 target
->context
= pctx
;
1362 target
->buffer_offset
= buffer_offset
;
1363 target
->buffer_size
= buffer_size
;
1369 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1370 struct pipe_stream_output_target
*target
)
1372 pipe_resource_reference(&target
->buffer
, NULL
);
1373 ralloc_free(target
);
1377 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1378 unsigned num_targets
,
1379 struct pipe_stream_output_target
**targets
,
1380 const unsigned *offsets
)
1382 struct panfrost_context
*ctx
= pan_context(pctx
);
1383 struct panfrost_streamout
*so
= &ctx
->streamout
;
1385 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1387 for (unsigned i
= 0; i
< num_targets
; i
++) {
1388 if (offsets
[i
] != -1)
1389 so
->offsets
[i
] = offsets
[i
];
1391 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1394 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1395 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1397 so
->num_targets
= num_targets
;
1400 struct pipe_context
*
1401 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1403 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1404 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1405 struct panfrost_device
*dev
= pan_device(screen
);
1407 gallium
->screen
= screen
;
1409 gallium
->destroy
= panfrost_destroy
;
1411 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1413 gallium
->flush
= panfrost_flush
;
1414 gallium
->clear
= panfrost_clear
;
1415 gallium
->draw_vbo
= panfrost_draw_vbo
;
1416 gallium
->texture_barrier
= panfrost_texture_barrier
;
1418 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1419 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1420 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1422 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1424 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1425 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1426 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1428 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1429 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1430 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1432 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1433 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1434 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1436 gallium
->create_fs_state
= panfrost_create_fs_state
;
1437 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1438 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1440 gallium
->create_vs_state
= panfrost_create_vs_state
;
1441 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1442 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1444 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1445 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1446 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1448 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1449 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1450 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1452 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1453 gallium
->set_min_samples
= panfrost_set_min_samples
;
1455 gallium
->set_clip_state
= panfrost_set_clip_state
;
1456 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1457 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1458 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1459 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1461 gallium
->create_query
= panfrost_create_query
;
1462 gallium
->destroy_query
= panfrost_destroy_query
;
1463 gallium
->begin_query
= panfrost_begin_query
;
1464 gallium
->end_query
= panfrost_end_query
;
1465 gallium
->get_query_result
= panfrost_get_query_result
;
1467 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1468 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1469 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1471 panfrost_resource_context_init(gallium
);
1472 panfrost_blend_context_init(gallium
);
1473 panfrost_compute_context_init(gallium
);
1475 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1476 gallium
->const_uploader
= gallium
->stream_uploader
;
1478 ctx
->state_uploader
= u_upload_create(gallium
, 4096,
1479 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_DYNAMIC
, 0);
1481 /* All of our GPUs support ES mode. Midgard supports additionally
1482 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1484 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1486 if (!(dev
->quirks
& IS_BIFROST
)) {
1487 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1488 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1491 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1493 ctx
->blitter
= util_blitter_create(gallium
);
1494 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1496 assert(ctx
->blitter
);
1497 assert(ctx
->blitter_wallpaper
);
1499 /* Prepare for render! */
1501 panfrost_batch_init(ctx
);
1503 if (!(dev
->quirks
& IS_BIFROST
)) {
1504 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1505 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1508 /* By default mask everything on */
1509 ctx
->sample_mask
= ~0;
1510 ctx
->active_queries
= true;