panfrost: Hoist add_fbo_bo call
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27 #include <sys/poll.h>
28 #include <errno.h>
29
30 #include "pan_bo.h"
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
34
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
50
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
55 #include "pan_util.h"
56 #include "decode.h"
57 #include "util/pan_lower_framebuffer.h"
58
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
61 {
62 struct panfrost_device *device = pan_device(batch->ctx->base.screen);
63 bool hierarchy = !(device->quirks & MIDGARD_NO_HIER_TILING);
64 struct midgard_tiler_descriptor t = {0};
65 unsigned height = batch->key.height;
66 unsigned width = batch->key.width;
67
68 t.hierarchy_mask =
69 panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
70
71 /* Compute the polygon header size and use that to offset the body */
72
73 unsigned header_size = panfrost_tiler_header_size(
74 width, height, t.hierarchy_mask, hierarchy);
75
76 t.polygon_list_size = panfrost_tiler_full_size(
77 width, height, t.hierarchy_mask, hierarchy);
78
79 /* Sanity check */
80
81 if (vertex_count) {
82 struct panfrost_bo *tiler_heap;
83
84 tiler_heap = panfrost_batch_get_tiler_heap(batch);
85 t.polygon_list = panfrost_batch_get_polygon_list(batch,
86 header_size +
87 t.polygon_list_size);
88
89
90 /* Allow the entire tiler heap */
91 t.heap_start = tiler_heap->gpu;
92 t.heap_end = tiler_heap->gpu + tiler_heap->size;
93 } else {
94 struct panfrost_bo *tiler_dummy;
95
96 tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
97 header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
98
99 /* The tiler is disabled, so don't allow the tiler heap */
100 t.heap_start = tiler_dummy->gpu;
101 t.heap_end = t.heap_start;
102
103 /* Use a dummy polygon list */
104 t.polygon_list = tiler_dummy->gpu;
105
106 /* Disable the tiler */
107 if (hierarchy)
108 t.hierarchy_mask |= MALI_TILER_DISABLED;
109 else {
110 t.hierarchy_mask = MALI_TILER_USER;
111 t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
112
113 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
114 uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
115 polygon_list_body[0] = 0xa0000000; /* TODO: Just that? */
116 }
117 }
118
119 t.polygon_list_body =
120 t.polygon_list + header_size;
121
122 return t;
123 }
124
125 static void
126 panfrost_clear(
127 struct pipe_context *pipe,
128 unsigned buffers,
129 const struct pipe_scissor_state *scissor_state,
130 const union pipe_color_union *color,
131 double depth, unsigned stencil)
132 {
133 struct panfrost_context *ctx = pan_context(pipe);
134
135 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
136 * the existing batch targeting this FBO has draws. We could probably
137 * avoid that by replacing plain clears by quad-draws with a specific
138 * color/depth/stencil value, thus avoiding the generation of extra
139 * fragment jobs.
140 */
141 struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx);
142 panfrost_batch_clear(batch, buffers, color, depth, stencil);
143 }
144
145 bool
146 panfrost_writes_point_size(struct panfrost_context *ctx)
147 {
148 assert(ctx->shader[PIPE_SHADER_VERTEX]);
149 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
150
151 return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
152 }
153
154 /* Compute number of UBOs active (more specifically, compute the highest UBO
155 * number addressable -- if there are gaps, include them in the count anyway).
156 * We always include UBO #0 in the count, since we *need* uniforms enabled for
157 * sysvals. */
158
159 unsigned
160 panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
161 {
162 unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
163 return 32 - __builtin_clz(mask);
164 }
165
166 /* The entire frame is in memory -- send it off to the kernel! */
167
168 void
169 panfrost_flush(
170 struct pipe_context *pipe,
171 struct pipe_fence_handle **fence,
172 unsigned flags)
173 {
174 struct panfrost_context *ctx = pan_context(pipe);
175 struct panfrost_device *dev = pan_device(pipe->screen);
176 uint32_t syncobj = 0;
177
178 if (fence)
179 drmSyncobjCreate(dev->fd, 0, &syncobj);
180
181 /* Submit all pending jobs */
182 panfrost_flush_all_batches(ctx, syncobj);
183
184 if (fence) {
185 struct panfrost_fence *f = panfrost_fence_create(ctx, syncobj);
186 pipe->screen->fence_reference(pipe->screen, fence, NULL);
187 *fence = (struct pipe_fence_handle *)f;
188 }
189
190 if (dev->debug & PAN_DBG_TRACE)
191 pandecode_next_frame();
192 }
193
194 static void
195 panfrost_texture_barrier(struct pipe_context *pipe, unsigned flags)
196 {
197 struct panfrost_context *ctx = pan_context(pipe);
198 panfrost_flush_all_batches(ctx, 0);
199 }
200
201 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
202
203 static int
204 g2m_draw_mode(enum pipe_prim_type mode)
205 {
206 switch (mode) {
207 DEFINE_CASE(POINTS);
208 DEFINE_CASE(LINES);
209 DEFINE_CASE(LINE_LOOP);
210 DEFINE_CASE(LINE_STRIP);
211 DEFINE_CASE(TRIANGLES);
212 DEFINE_CASE(TRIANGLE_STRIP);
213 DEFINE_CASE(TRIANGLE_FAN);
214 DEFINE_CASE(QUADS);
215 DEFINE_CASE(QUAD_STRIP);
216 DEFINE_CASE(POLYGON);
217
218 default:
219 unreachable("Invalid draw mode");
220 }
221 }
222
223 #undef DEFINE_CASE
224
225 static bool
226 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
227 {
228 const struct pipe_scissor_state *ss = &ctx->scissor;
229
230 /* Check if we're scissoring at all */
231
232 if (!ctx->rasterizer->base.scissor)
233 return false;
234
235 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
236 }
237
238 /* Count generated primitives (when there is no geom/tess shaders) for
239 * transform feedback */
240
241 static void
242 panfrost_statistics_record(
243 struct panfrost_context *ctx,
244 const struct pipe_draw_info *info)
245 {
246 if (!ctx->active_queries)
247 return;
248
249 uint32_t prims = u_prims_for_vertices(info->mode, info->count);
250 ctx->prims_generated += prims;
251
252 if (!ctx->streamout.num_targets)
253 return;
254
255 ctx->tf_prims_generated += prims;
256 }
257
258 static void
259 panfrost_update_streamout_offsets(struct panfrost_context *ctx)
260 {
261 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
262 unsigned count;
263
264 count = u_stream_outputs_for_vertices(ctx->active_prim,
265 ctx->vertex_count);
266 ctx->streamout.offsets[i] += count;
267 }
268 }
269
270 static void
271 panfrost_draw_vbo(
272 struct pipe_context *pipe,
273 const struct pipe_draw_info *info)
274 {
275 struct panfrost_context *ctx = pan_context(pipe);
276
277 /* First of all, check the scissor to see if anything is drawn at all.
278 * If it's not, we drop the draw (mostly a conformance issue;
279 * well-behaved apps shouldn't hit this) */
280
281 if (panfrost_scissor_culls_everything(ctx))
282 return;
283
284 int mode = info->mode;
285
286 /* Fallback unsupported restart index */
287 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
288
289 if (info->primitive_restart && info->index_size
290 && info->restart_index != primitive_index) {
291 util_draw_vbo_without_prim_restart(pipe, info);
292 return;
293 }
294
295 /* Fallback for unsupported modes */
296
297 assert(ctx->rasterizer != NULL);
298
299 if (!(ctx->draw_modes & (1 << mode))) {
300 if (info->count < 4) {
301 /* Degenerate case? */
302 return;
303 }
304
305 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
306 util_primconvert_draw_vbo(ctx->primconvert, info);
307 return;
308 }
309
310 /* Now that we have a guaranteed terminating path, find the job. */
311
312 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
313 panfrost_batch_set_requirements(batch);
314
315 /* Take into account a negative bias */
316 ctx->vertex_count = info->count + abs(info->index_bias);
317 ctx->instance_count = info->instance_count;
318 ctx->active_prim = info->mode;
319
320 struct mali_vertex_tiler_prefix vertex_prefix, tiler_prefix;
321 struct mali_vertex_tiler_postfix vertex_postfix, tiler_postfix;
322 union midgard_primitive_size primitive_size;
323 unsigned vertex_count;
324
325 panfrost_vt_init(ctx, PIPE_SHADER_VERTEX, &vertex_prefix, &vertex_postfix);
326 panfrost_vt_init(ctx, PIPE_SHADER_FRAGMENT, &tiler_prefix, &tiler_postfix);
327
328 panfrost_vt_set_draw_info(ctx, info, g2m_draw_mode(mode),
329 &vertex_postfix, &tiler_prefix,
330 &tiler_postfix, &vertex_count,
331 &ctx->padded_count);
332
333 panfrost_statistics_record(ctx, info);
334
335 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
336 * vertex_count, 1) */
337
338 panfrost_pack_work_groups_fused(&vertex_prefix, &tiler_prefix,
339 1, vertex_count, info->instance_count,
340 1, 1, 1);
341
342 /* Emit all sort of descriptors. */
343 panfrost_emit_vertex_data(batch, &vertex_postfix);
344 panfrost_emit_varying_descriptor(batch,
345 ctx->padded_count *
346 ctx->instance_count,
347 &vertex_postfix, &tiler_postfix,
348 &primitive_size);
349 panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
350 panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
351 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
352 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
353 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
354 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
355 panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
356 panfrost_emit_const_buf(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
357 panfrost_emit_viewport(batch, &tiler_postfix);
358
359 panfrost_vt_update_primitive_size(ctx, &tiler_prefix, &primitive_size);
360
361 /* Fire off the draw itself */
362 panfrost_emit_vertex_tiler_jobs(batch, &vertex_prefix, &vertex_postfix,
363 &tiler_prefix, &tiler_postfix,
364 &primitive_size);
365
366 /* Adjust the batch stack size based on the new shader stack sizes. */
367 panfrost_batch_adjust_stack_size(batch);
368
369 /* Increment transform feedback offsets */
370 panfrost_update_streamout_offsets(ctx);
371 }
372
373 /* CSO state */
374
375 static void
376 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
377 {
378 free(hwcso);
379 }
380
381 static void *
382 panfrost_create_rasterizer_state(
383 struct pipe_context *pctx,
384 const struct pipe_rasterizer_state *cso)
385 {
386 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
387
388 so->base = *cso;
389
390 return so;
391 }
392
393 static void
394 panfrost_bind_rasterizer_state(
395 struct pipe_context *pctx,
396 void *hwcso)
397 {
398 struct panfrost_context *ctx = pan_context(pctx);
399
400 ctx->rasterizer = hwcso;
401
402 if (!hwcso)
403 return;
404
405 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
406 assert(ctx->rasterizer->base.offset_clamp == 0.0);
407
408 /* Point sprites are emulated */
409
410 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
411
412 if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
413 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
414 }
415
416 static void *
417 panfrost_create_vertex_elements_state(
418 struct pipe_context *pctx,
419 unsigned num_elements,
420 const struct pipe_vertex_element *elements)
421 {
422 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
423 struct panfrost_device *dev = pan_device(pctx->screen);
424
425 so->num_elements = num_elements;
426 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
427
428 for (int i = 0; i < num_elements; ++i) {
429 enum pipe_format fmt = elements[i].src_format;
430 const struct util_format_description *desc = util_format_description(fmt);
431 unsigned swizzle = 0;
432 if (dev->quirks & HAS_SWIZZLES)
433 swizzle = panfrost_translate_swizzle_4(desc->swizzle);
434 else
435 swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
436
437 enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
438 so->formats[i] = (hw_format << 12) | swizzle;
439 assert(hw_format);
440 }
441
442 /* Let's also prepare vertex builtins */
443 if (dev->quirks & HAS_SWIZZLES)
444 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
445 else
446 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
447
448 if (dev->quirks & HAS_SWIZZLES)
449 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
450 else
451 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
452
453 return so;
454 }
455
456 static void
457 panfrost_bind_vertex_elements_state(
458 struct pipe_context *pctx,
459 void *hwcso)
460 {
461 struct panfrost_context *ctx = pan_context(pctx);
462 ctx->vertex = hwcso;
463 }
464
465 static void *
466 panfrost_create_shader_state(
467 struct pipe_context *pctx,
468 const struct pipe_shader_state *cso,
469 enum pipe_shader_type stage)
470 {
471 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
472 struct panfrost_device *dev = pan_device(pctx->screen);
473 so->base = *cso;
474
475 /* Token deep copy to prevent memory corruption */
476
477 if (cso->type == PIPE_SHADER_IR_TGSI)
478 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
479
480 /* Precompile for shader-db if we need to */
481 if (unlikely((dev->debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
482 struct panfrost_context *ctx = pan_context(pctx);
483
484 struct panfrost_shader_state state;
485 uint64_t outputs_written;
486
487 panfrost_shader_compile(ctx, PIPE_SHADER_IR_NIR,
488 so->base.ir.nir,
489 tgsi_processor_to_shader_stage(stage),
490 &state, &outputs_written);
491 }
492
493 return so;
494 }
495
496 static void
497 panfrost_delete_shader_state(
498 struct pipe_context *pctx,
499 void *so)
500 {
501 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
502
503 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
504 /* TODO: leaks TGSI tokens! */
505 }
506
507 for (unsigned i = 0; i < cso->variant_count; ++i) {
508 struct panfrost_shader_state *shader_state = &cso->variants[i];
509 panfrost_bo_unreference(shader_state->bo);
510 shader_state->bo = NULL;
511 }
512 free(cso->variants);
513
514 free(so);
515 }
516
517 static void *
518 panfrost_create_sampler_state(
519 struct pipe_context *pctx,
520 const struct pipe_sampler_state *cso)
521 {
522 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
523 struct panfrost_device *device = pan_device(pctx->screen);
524
525 so->base = *cso;
526
527 if (device->quirks & IS_BIFROST)
528 panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw);
529 else
530 panfrost_sampler_desc_init(cso, &so->hw);
531
532 return so;
533 }
534
535 static void
536 panfrost_bind_sampler_states(
537 struct pipe_context *pctx,
538 enum pipe_shader_type shader,
539 unsigned start_slot, unsigned num_sampler,
540 void **sampler)
541 {
542 assert(start_slot == 0);
543
544 struct panfrost_context *ctx = pan_context(pctx);
545
546 /* XXX: Should upload, not just copy? */
547 ctx->sampler_count[shader] = num_sampler;
548 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
549 }
550
551 static bool
552 panfrost_variant_matches(
553 struct panfrost_context *ctx,
554 struct panfrost_shader_state *variant,
555 enum pipe_shader_type type)
556 {
557 struct panfrost_device *dev = pan_device(ctx->base.screen);
558 struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
559
560 bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
561
562 if (variant->outputs_read) {
563 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
564
565 unsigned i;
566 BITSET_FOREACH_SET(i, &variant->outputs_read, 8) {
567 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
568
569 if ((fb->nr_cbufs > i) && fb->cbufs[i])
570 fmt = fb->cbufs[i]->format;
571
572 const struct util_format_description *desc =
573 util_format_description(fmt);
574
575 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
576 fmt = PIPE_FORMAT_NONE;
577
578 if (variant->rt_formats[i] != fmt)
579 return false;
580 }
581 }
582
583 /* Point sprites TODO on bifrost, always pass */
584 if (is_fragment && rasterizer && (rasterizer->sprite_coord_enable |
585 variant->point_sprite_mask)
586 && !(dev->quirks & IS_BIFROST)) {
587 /* Ensure the same varyings are turned to point sprites */
588 if (rasterizer->sprite_coord_enable != variant->point_sprite_mask)
589 return false;
590
591 /* Ensure the orientation is correct */
592 bool upper_left =
593 rasterizer->sprite_coord_mode ==
594 PIPE_SPRITE_COORD_UPPER_LEFT;
595
596 if (variant->point_sprite_upper_left != upper_left)
597 return false;
598 }
599
600 /* Otherwise, we're good to go */
601 return true;
602 }
603
604 /**
605 * Fix an uncompiled shader's stream output info, and produce a bitmask
606 * of which VARYING_SLOT_* are captured for stream output.
607 *
608 * Core Gallium stores output->register_index as a "slot" number, where
609 * slots are assigned consecutively to all outputs in info->outputs_written.
610 * This naive packing of outputs doesn't work for us - we too have slots,
611 * but the layout is defined by the VUE map, which we won't have until we
612 * compile a specific shader variant. So, we remap these and simply store
613 * VARYING_SLOT_* in our copy's output->register_index fields.
614 *
615 * We then produce a bitmask of outputs which are used for SO.
616 *
617 * Implementation from iris.
618 */
619
620 static uint64_t
621 update_so_info(struct pipe_stream_output_info *so_info,
622 uint64_t outputs_written)
623 {
624 uint64_t so_outputs = 0;
625 uint8_t reverse_map[64] = {0};
626 unsigned slot = 0;
627
628 while (outputs_written)
629 reverse_map[slot++] = u_bit_scan64(&outputs_written);
630
631 for (unsigned i = 0; i < so_info->num_outputs; i++) {
632 struct pipe_stream_output *output = &so_info->output[i];
633
634 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
635 output->register_index = reverse_map[output->register_index];
636
637 so_outputs |= 1ull << output->register_index;
638 }
639
640 return so_outputs;
641 }
642
643 static void
644 panfrost_bind_shader_state(
645 struct pipe_context *pctx,
646 void *hwcso,
647 enum pipe_shader_type type)
648 {
649 struct panfrost_context *ctx = pan_context(pctx);
650 struct panfrost_device *dev = pan_device(ctx->base.screen);
651 ctx->shader[type] = hwcso;
652
653 if (!hwcso) return;
654
655 /* Match the appropriate variant */
656
657 signed variant = -1;
658 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
659
660 for (unsigned i = 0; i < variants->variant_count; ++i) {
661 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
662 variant = i;
663 break;
664 }
665 }
666
667 if (variant == -1) {
668 /* No variant matched, so create a new one */
669 variant = variants->variant_count++;
670
671 if (variants->variant_count > variants->variant_space) {
672 unsigned old_space = variants->variant_space;
673
674 variants->variant_space *= 2;
675 if (variants->variant_space == 0)
676 variants->variant_space = 1;
677
678 /* Arbitrary limit to stop runaway programs from
679 * creating an unbounded number of shader variants. */
680 assert(variants->variant_space < 1024);
681
682 unsigned msize = sizeof(struct panfrost_shader_state);
683 variants->variants = realloc(variants->variants,
684 variants->variant_space * msize);
685
686 memset(&variants->variants[old_space], 0,
687 (variants->variant_space - old_space) * msize);
688 }
689
690 struct panfrost_shader_state *v =
691 &variants->variants[variant];
692
693 if (type == PIPE_SHADER_FRAGMENT) {
694 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
695 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
696 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
697
698 if ((fb->nr_cbufs > i) && fb->cbufs[i])
699 fmt = fb->cbufs[i]->format;
700
701 const struct util_format_description *desc =
702 util_format_description(fmt);
703
704 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
705 fmt = PIPE_FORMAT_NONE;
706
707 v->rt_formats[i] = fmt;
708 }
709
710 /* Point sprites are TODO on Bifrost */
711 if (ctx->rasterizer && !(dev->quirks & IS_BIFROST)) {
712 v->point_sprite_mask = ctx->rasterizer->base.sprite_coord_enable;
713 v->point_sprite_upper_left =
714 ctx->rasterizer->base.sprite_coord_mode ==
715 PIPE_SPRITE_COORD_UPPER_LEFT;
716 }
717 }
718 }
719
720 /* Select this variant */
721 variants->active_variant = variant;
722
723 struct panfrost_shader_state *shader_state = &variants->variants[variant];
724 assert(panfrost_variant_matches(ctx, shader_state, type));
725
726 /* We finally have a variant, so compile it */
727
728 if (!shader_state->compiled) {
729 uint64_t outputs_written = 0;
730
731 panfrost_shader_compile(ctx, variants->base.type,
732 variants->base.type == PIPE_SHADER_IR_NIR ?
733 variants->base.ir.nir :
734 variants->base.tokens,
735 tgsi_processor_to_shader_stage(type),
736 shader_state,
737 &outputs_written);
738
739 shader_state->compiled = true;
740
741 /* Fixup the stream out information, since what Gallium returns
742 * normally is mildly insane */
743
744 shader_state->stream_output = variants->base.stream_output;
745 shader_state->so_mask =
746 update_so_info(&shader_state->stream_output, outputs_written);
747 }
748 }
749
750 static void *
751 panfrost_create_vs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
752 {
753 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
754 }
755
756 static void *
757 panfrost_create_fs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
758 {
759 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
760 }
761
762 static void
763 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
764 {
765 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
766 }
767
768 static void
769 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
770 {
771 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
772 }
773
774 static void
775 panfrost_set_vertex_buffers(
776 struct pipe_context *pctx,
777 unsigned start_slot,
778 unsigned num_buffers,
779 const struct pipe_vertex_buffer *buffers)
780 {
781 struct panfrost_context *ctx = pan_context(pctx);
782
783 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
784 }
785
786 static void
787 panfrost_set_constant_buffer(
788 struct pipe_context *pctx,
789 enum pipe_shader_type shader, uint index,
790 const struct pipe_constant_buffer *buf)
791 {
792 struct panfrost_context *ctx = pan_context(pctx);
793 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
794
795 util_copy_constant_buffer(&pbuf->cb[index], buf);
796
797 unsigned mask = (1 << index);
798
799 if (unlikely(!buf)) {
800 pbuf->enabled_mask &= ~mask;
801 pbuf->dirty_mask &= ~mask;
802 return;
803 }
804
805 pbuf->enabled_mask |= mask;
806 pbuf->dirty_mask |= mask;
807 }
808
809 static void
810 panfrost_set_stencil_ref(
811 struct pipe_context *pctx,
812 const struct pipe_stencil_ref *ref)
813 {
814 struct panfrost_context *ctx = pan_context(pctx);
815 ctx->stencil_ref = *ref;
816 }
817
818 void
819 panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
820 struct pipe_context *pctx,
821 struct pipe_resource *texture)
822 {
823 struct panfrost_device *device = pan_device(pctx->screen);
824 struct panfrost_resource *prsrc = (struct panfrost_resource *)texture;
825 enum pipe_format format = so->base.format;
826 assert(prsrc->bo);
827
828 /* Format to access the stencil portion of a Z32_S8 texture */
829 if (format == PIPE_FORMAT_X32_S8X24_UINT) {
830 assert(prsrc->separate_stencil);
831 texture = &prsrc->separate_stencil->base;
832 prsrc = (struct panfrost_resource *)texture;
833 format = texture->format;
834 }
835
836 const struct util_format_description *desc = util_format_description(format);
837
838 bool fake_rgtc = !panfrost_supports_compressed_format(device, MALI_BC4_UNORM);
839
840 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC && fake_rgtc) {
841 if (desc->is_snorm)
842 format = PIPE_FORMAT_R8G8B8A8_SNORM;
843 else
844 format = PIPE_FORMAT_R8G8B8A8_UNORM;
845 desc = util_format_description(format);
846 }
847
848 so->texture_bo = prsrc->bo->gpu;
849 so->modifier = prsrc->modifier;
850
851 unsigned char user_swizzle[4] = {
852 so->base.swizzle_r,
853 so->base.swizzle_g,
854 so->base.swizzle_b,
855 so->base.swizzle_a
856 };
857
858 /* In the hardware, array_size refers specifically to array textures,
859 * whereas in Gallium, it also covers cubemaps */
860
861 unsigned array_size = texture->array_size;
862 unsigned depth = texture->depth0;
863
864 if (so->base.target == PIPE_TEXTURE_CUBE) {
865 /* TODO: Cubemap arrays */
866 assert(array_size == 6);
867 array_size /= 6;
868 }
869
870 /* MSAA only supported for 2D textures (and 2D texture arrays via an
871 * extension currently unimplemented */
872
873 if (so->base.target == PIPE_TEXTURE_2D) {
874 assert(depth == 1);
875 depth = texture->nr_samples;
876 } else {
877 /* MSAA only supported for 2D textures */
878 assert(texture->nr_samples <= 1);
879 }
880
881 enum mali_texture_dimension type =
882 panfrost_translate_texture_dimension(so->base.target);
883
884 if (device->quirks & IS_BIFROST) {
885 unsigned char composed_swizzle[4];
886 util_format_compose_swizzles(desc->swizzle, user_swizzle, composed_swizzle);
887
888 unsigned size = panfrost_estimate_texture_payload_size(
889 so->base.u.tex.first_level,
890 so->base.u.tex.last_level,
891 so->base.u.tex.first_layer,
892 so->base.u.tex.last_layer,
893 texture->nr_samples,
894 type, prsrc->modifier);
895
896 so->bo = panfrost_bo_create(device, size, 0);
897
898 panfrost_new_texture_bifrost(
899 &so->bifrost_descriptor,
900 texture->width0, texture->height0,
901 depth, array_size,
902 format,
903 type, prsrc->modifier,
904 so->base.u.tex.first_level,
905 so->base.u.tex.last_level,
906 so->base.u.tex.first_layer,
907 so->base.u.tex.last_layer,
908 texture->nr_samples,
909 prsrc->cubemap_stride,
910 panfrost_translate_swizzle_4(composed_swizzle),
911 prsrc->bo->gpu,
912 prsrc->slices,
913 so->bo);
914 } else {
915 unsigned size = panfrost_estimate_texture_payload_size(
916 so->base.u.tex.first_level,
917 so->base.u.tex.last_level,
918 so->base.u.tex.first_layer,
919 so->base.u.tex.last_layer,
920 texture->nr_samples,
921 type, prsrc->modifier);
922 size += MALI_MIDGARD_TEXTURE_LENGTH;
923
924 so->bo = panfrost_bo_create(device, size, 0);
925
926 panfrost_new_texture(
927 so->bo->cpu,
928 texture->width0, texture->height0,
929 depth, array_size,
930 format,
931 type, prsrc->modifier,
932 so->base.u.tex.first_level,
933 so->base.u.tex.last_level,
934 so->base.u.tex.first_layer,
935 so->base.u.tex.last_layer,
936 texture->nr_samples,
937 prsrc->cubemap_stride,
938 panfrost_translate_swizzle_4(user_swizzle),
939 prsrc->bo->gpu,
940 prsrc->slices);
941 }
942 }
943
944 static struct pipe_sampler_view *
945 panfrost_create_sampler_view(
946 struct pipe_context *pctx,
947 struct pipe_resource *texture,
948 const struct pipe_sampler_view *template)
949 {
950 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
951
952 pipe_reference(NULL, &texture->reference);
953
954 so->base = *template;
955 so->base.texture = texture;
956 so->base.reference.count = 1;
957 so->base.context = pctx;
958
959 panfrost_create_sampler_view_bo(so, pctx, texture);
960
961 return (struct pipe_sampler_view *) so;
962 }
963
964 static void
965 panfrost_set_sampler_views(
966 struct pipe_context *pctx,
967 enum pipe_shader_type shader,
968 unsigned start_slot, unsigned num_views,
969 struct pipe_sampler_view **views)
970 {
971 struct panfrost_context *ctx = pan_context(pctx);
972 unsigned new_nr = 0;
973 unsigned i;
974
975 assert(start_slot == 0);
976
977 for (i = 0; i < num_views; ++i) {
978 if (views[i])
979 new_nr = i + 1;
980 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
981 views[i]);
982 }
983
984 for (; i < ctx->sampler_view_count[shader]; i++) {
985 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
986 NULL);
987 }
988 ctx->sampler_view_count[shader] = new_nr;
989 }
990
991 static void
992 panfrost_sampler_view_destroy(
993 struct pipe_context *pctx,
994 struct pipe_sampler_view *pview)
995 {
996 struct panfrost_sampler_view *view = (struct panfrost_sampler_view *) pview;
997
998 pipe_resource_reference(&pview->texture, NULL);
999 panfrost_bo_unreference(view->bo);
1000 ralloc_free(view);
1001 }
1002
1003 static void
1004 panfrost_set_shader_buffers(
1005 struct pipe_context *pctx,
1006 enum pipe_shader_type shader,
1007 unsigned start, unsigned count,
1008 const struct pipe_shader_buffer *buffers,
1009 unsigned writable_bitmask)
1010 {
1011 struct panfrost_context *ctx = pan_context(pctx);
1012
1013 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
1014 buffers, start, count);
1015 }
1016
1017 static void
1018 panfrost_set_framebuffer_state(struct pipe_context *pctx,
1019 const struct pipe_framebuffer_state *fb)
1020 {
1021 struct panfrost_context *ctx = pan_context(pctx);
1022
1023 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
1024 ctx->batch = NULL;
1025
1026 /* We may need to generate a new variant if the fragment shader is
1027 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1028 struct panfrost_shader_variants *fs = ctx->shader[PIPE_SHADER_FRAGMENT];
1029
1030 if (fs && fs->variant_count && fs->variants[fs->active_variant].outputs_read)
1031 ctx->base.bind_fs_state(&ctx->base, fs);
1032 }
1033
1034 static inline unsigned
1035 pan_pipe_to_stencil_op(enum pipe_stencil_op in)
1036 {
1037 switch (in) {
1038 case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
1039 case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
1040 case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
1041 case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
1042 case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
1043 case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
1044 case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
1045 case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
1046 default: unreachable("Invalid stencil op");
1047 }
1048 }
1049
1050 static inline void
1051 pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
1052 {
1053 pan_pack(out, STENCIL, cfg) {
1054 cfg.mask = in->valuemask;
1055 cfg.compare_function = panfrost_translate_compare_func(in->func);
1056 cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
1057 cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
1058 cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
1059 }
1060 }
1061
1062 static void *
1063 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
1064 const struct pipe_depth_stencil_alpha_state *zsa)
1065 {
1066 struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
1067 so->base = *zsa;
1068
1069 pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
1070 pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
1071
1072 so->stencil_mask_front = zsa->stencil[0].writemask;
1073
1074 if (zsa->stencil[1].enabled)
1075 so->stencil_mask_back = zsa->stencil[1].writemask;
1076 else
1077 so->stencil_mask_back = so->stencil_mask_front;
1078
1079 /* Alpha lowered by frontend */
1080 assert(!zsa->alpha.enabled);
1081
1082 /* TODO: Bounds test should be easy */
1083 assert(!zsa->depth.bounds_test);
1084
1085 return so;
1086 }
1087
1088 static void
1089 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
1090 void *cso)
1091 {
1092 struct panfrost_context *ctx = pan_context(pipe);
1093 struct panfrost_zsa_state *zsa = cso;
1094 ctx->depth_stencil = zsa;
1095 }
1096
1097 static void
1098 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
1099 {
1100 free( depth );
1101 }
1102
1103 static void
1104 panfrost_set_sample_mask(struct pipe_context *pipe,
1105 unsigned sample_mask)
1106 {
1107 struct panfrost_context *ctx = pan_context(pipe);
1108 ctx->sample_mask = sample_mask;
1109 }
1110
1111 static void
1112 panfrost_set_min_samples(struct pipe_context *pipe,
1113 unsigned min_samples)
1114 {
1115 struct panfrost_context *ctx = pan_context(pipe);
1116 ctx->min_samples = min_samples;
1117 }
1118
1119
1120 static void
1121 panfrost_set_clip_state(struct pipe_context *pipe,
1122 const struct pipe_clip_state *clip)
1123 {
1124 //struct panfrost_context *panfrost = pan_context(pipe);
1125 }
1126
1127 static void
1128 panfrost_set_viewport_states(struct pipe_context *pipe,
1129 unsigned start_slot,
1130 unsigned num_viewports,
1131 const struct pipe_viewport_state *viewports)
1132 {
1133 struct panfrost_context *ctx = pan_context(pipe);
1134
1135 assert(start_slot == 0);
1136 assert(num_viewports == 1);
1137
1138 ctx->pipe_viewport = *viewports;
1139 }
1140
1141 static void
1142 panfrost_set_scissor_states(struct pipe_context *pipe,
1143 unsigned start_slot,
1144 unsigned num_scissors,
1145 const struct pipe_scissor_state *scissors)
1146 {
1147 struct panfrost_context *ctx = pan_context(pipe);
1148
1149 assert(start_slot == 0);
1150 assert(num_scissors == 1);
1151
1152 ctx->scissor = *scissors;
1153 }
1154
1155 static void
1156 panfrost_set_polygon_stipple(struct pipe_context *pipe,
1157 const struct pipe_poly_stipple *stipple)
1158 {
1159 //struct panfrost_context *panfrost = pan_context(pipe);
1160 }
1161
1162 static void
1163 panfrost_set_active_query_state(struct pipe_context *pipe,
1164 bool enable)
1165 {
1166 struct panfrost_context *ctx = pan_context(pipe);
1167 ctx->active_queries = enable;
1168 }
1169
1170 static void
1171 panfrost_destroy(struct pipe_context *pipe)
1172 {
1173 struct panfrost_context *panfrost = pan_context(pipe);
1174
1175 if (panfrost->blitter)
1176 util_blitter_destroy(panfrost->blitter);
1177
1178 if (panfrost->blitter_wallpaper)
1179 util_blitter_destroy(panfrost->blitter_wallpaper);
1180
1181 util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
1182 u_upload_destroy(pipe->stream_uploader);
1183
1184 ralloc_free(pipe);
1185 }
1186
1187 static struct pipe_query *
1188 panfrost_create_query(struct pipe_context *pipe,
1189 unsigned type,
1190 unsigned index)
1191 {
1192 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
1193
1194 q->type = type;
1195 q->index = index;
1196
1197 return (struct pipe_query *) q;
1198 }
1199
1200 static void
1201 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
1202 {
1203 struct panfrost_query *query = (struct panfrost_query *) q;
1204
1205 if (query->bo) {
1206 panfrost_bo_unreference(query->bo);
1207 query->bo = NULL;
1208 }
1209
1210 ralloc_free(q);
1211 }
1212
1213 static bool
1214 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
1215 {
1216 struct panfrost_context *ctx = pan_context(pipe);
1217 struct panfrost_query *query = (struct panfrost_query *) q;
1218
1219 switch (query->type) {
1220 case PIPE_QUERY_OCCLUSION_COUNTER:
1221 case PIPE_QUERY_OCCLUSION_PREDICATE:
1222 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1223 /* Allocate a bo for the query results to be stored */
1224 if (!query->bo) {
1225 query->bo = panfrost_bo_create(
1226 pan_device(ctx->base.screen),
1227 sizeof(unsigned), 0);
1228 }
1229
1230 unsigned *result = (unsigned *)query->bo->cpu;
1231 *result = 0; /* Default to 0 if nothing at all drawn. */
1232 ctx->occlusion_query = query;
1233 break;
1234
1235 /* Geometry statistics are computed in the driver. XXX: geom/tess
1236 * shaders.. */
1237
1238 case PIPE_QUERY_PRIMITIVES_GENERATED:
1239 query->start = ctx->prims_generated;
1240 break;
1241 case PIPE_QUERY_PRIMITIVES_EMITTED:
1242 query->start = ctx->tf_prims_generated;
1243 break;
1244
1245 default:
1246 /* TODO: timestamp queries, etc? */
1247 break;
1248 }
1249
1250 return true;
1251 }
1252
1253 static bool
1254 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
1255 {
1256 struct panfrost_context *ctx = pan_context(pipe);
1257 struct panfrost_query *query = (struct panfrost_query *) q;
1258
1259 switch (query->type) {
1260 case PIPE_QUERY_OCCLUSION_COUNTER:
1261 case PIPE_QUERY_OCCLUSION_PREDICATE:
1262 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1263 ctx->occlusion_query = NULL;
1264 break;
1265 case PIPE_QUERY_PRIMITIVES_GENERATED:
1266 query->end = ctx->prims_generated;
1267 break;
1268 case PIPE_QUERY_PRIMITIVES_EMITTED:
1269 query->end = ctx->tf_prims_generated;
1270 break;
1271 }
1272
1273 return true;
1274 }
1275
1276 static bool
1277 panfrost_get_query_result(struct pipe_context *pipe,
1278 struct pipe_query *q,
1279 bool wait,
1280 union pipe_query_result *vresult)
1281 {
1282 struct panfrost_query *query = (struct panfrost_query *) q;
1283 struct panfrost_context *ctx = pan_context(pipe);
1284
1285
1286 switch (query->type) {
1287 case PIPE_QUERY_OCCLUSION_COUNTER:
1288 case PIPE_QUERY_OCCLUSION_PREDICATE:
1289 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1290 panfrost_flush_batches_accessing_bo(ctx, query->bo, false);
1291 panfrost_bo_wait(query->bo, INT64_MAX, false);
1292
1293 /* Read back the query results */
1294 unsigned *result = (unsigned *) query->bo->cpu;
1295 unsigned passed = *result;
1296
1297 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1298 vresult->u64 = passed;
1299 } else {
1300 vresult->b = !!passed;
1301 }
1302
1303 break;
1304
1305 case PIPE_QUERY_PRIMITIVES_GENERATED:
1306 case PIPE_QUERY_PRIMITIVES_EMITTED:
1307 panfrost_flush_all_batches(ctx, 0);
1308 vresult->u64 = query->end - query->start;
1309 break;
1310
1311 default:
1312 /* TODO: more queries */
1313 break;
1314 }
1315
1316 return true;
1317 }
1318
1319 static struct pipe_stream_output_target *
1320 panfrost_create_stream_output_target(struct pipe_context *pctx,
1321 struct pipe_resource *prsc,
1322 unsigned buffer_offset,
1323 unsigned buffer_size)
1324 {
1325 struct pipe_stream_output_target *target;
1326
1327 target = rzalloc(pctx, struct pipe_stream_output_target);
1328
1329 if (!target)
1330 return NULL;
1331
1332 pipe_reference_init(&target->reference, 1);
1333 pipe_resource_reference(&target->buffer, prsc);
1334
1335 target->context = pctx;
1336 target->buffer_offset = buffer_offset;
1337 target->buffer_size = buffer_size;
1338
1339 return target;
1340 }
1341
1342 static void
1343 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
1344 struct pipe_stream_output_target *target)
1345 {
1346 pipe_resource_reference(&target->buffer, NULL);
1347 ralloc_free(target);
1348 }
1349
1350 static void
1351 panfrost_set_stream_output_targets(struct pipe_context *pctx,
1352 unsigned num_targets,
1353 struct pipe_stream_output_target **targets,
1354 const unsigned *offsets)
1355 {
1356 struct panfrost_context *ctx = pan_context(pctx);
1357 struct panfrost_streamout *so = &ctx->streamout;
1358
1359 assert(num_targets <= ARRAY_SIZE(so->targets));
1360
1361 for (unsigned i = 0; i < num_targets; i++) {
1362 if (offsets[i] != -1)
1363 so->offsets[i] = offsets[i];
1364
1365 pipe_so_target_reference(&so->targets[i], targets[i]);
1366 }
1367
1368 for (unsigned i = 0; i < so->num_targets; i++)
1369 pipe_so_target_reference(&so->targets[i], NULL);
1370
1371 so->num_targets = num_targets;
1372 }
1373
1374 struct pipe_context *
1375 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
1376 {
1377 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
1378 struct pipe_context *gallium = (struct pipe_context *) ctx;
1379 struct panfrost_device *dev = pan_device(screen);
1380
1381 gallium->screen = screen;
1382
1383 gallium->destroy = panfrost_destroy;
1384
1385 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
1386
1387 gallium->flush = panfrost_flush;
1388 gallium->clear = panfrost_clear;
1389 gallium->draw_vbo = panfrost_draw_vbo;
1390 gallium->texture_barrier = panfrost_texture_barrier;
1391
1392 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
1393 gallium->set_constant_buffer = panfrost_set_constant_buffer;
1394 gallium->set_shader_buffers = panfrost_set_shader_buffers;
1395
1396 gallium->set_stencil_ref = panfrost_set_stencil_ref;
1397
1398 gallium->create_sampler_view = panfrost_create_sampler_view;
1399 gallium->set_sampler_views = panfrost_set_sampler_views;
1400 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
1401
1402 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
1403 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
1404 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
1405
1406 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
1407 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
1408 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
1409
1410 gallium->create_fs_state = panfrost_create_fs_state;
1411 gallium->delete_fs_state = panfrost_delete_shader_state;
1412 gallium->bind_fs_state = panfrost_bind_fs_state;
1413
1414 gallium->create_vs_state = panfrost_create_vs_state;
1415 gallium->delete_vs_state = panfrost_delete_shader_state;
1416 gallium->bind_vs_state = panfrost_bind_vs_state;
1417
1418 gallium->create_sampler_state = panfrost_create_sampler_state;
1419 gallium->delete_sampler_state = panfrost_generic_cso_delete;
1420 gallium->bind_sampler_states = panfrost_bind_sampler_states;
1421
1422 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
1423 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
1424 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
1425
1426 gallium->set_sample_mask = panfrost_set_sample_mask;
1427 gallium->set_min_samples = panfrost_set_min_samples;
1428
1429 gallium->set_clip_state = panfrost_set_clip_state;
1430 gallium->set_viewport_states = panfrost_set_viewport_states;
1431 gallium->set_scissor_states = panfrost_set_scissor_states;
1432 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
1433 gallium->set_active_query_state = panfrost_set_active_query_state;
1434
1435 gallium->create_query = panfrost_create_query;
1436 gallium->destroy_query = panfrost_destroy_query;
1437 gallium->begin_query = panfrost_begin_query;
1438 gallium->end_query = panfrost_end_query;
1439 gallium->get_query_result = panfrost_get_query_result;
1440
1441 gallium->create_stream_output_target = panfrost_create_stream_output_target;
1442 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
1443 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
1444
1445 panfrost_resource_context_init(gallium);
1446 panfrost_blend_context_init(gallium);
1447 panfrost_compute_context_init(gallium);
1448
1449 gallium->stream_uploader = u_upload_create_default(gallium);
1450 gallium->const_uploader = gallium->stream_uploader;
1451 assert(gallium->stream_uploader);
1452
1453 /* All of our GPUs support ES mode. Midgard supports additionally
1454 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1455
1456 ctx->draw_modes = (1 << (PIPE_PRIM_QUADS + 1)) - 1;
1457
1458 if (!(dev->quirks & IS_BIFROST)) {
1459 ctx->draw_modes |= (1 << PIPE_PRIM_QUAD_STRIP);
1460 ctx->draw_modes |= (1 << PIPE_PRIM_POLYGON);
1461 }
1462
1463 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
1464
1465 ctx->blitter = util_blitter_create(gallium);
1466 ctx->blitter_wallpaper = util_blitter_create(gallium);
1467
1468 assert(ctx->blitter);
1469 assert(ctx->blitter_wallpaper);
1470
1471 /* Prepare for render! */
1472
1473 panfrost_batch_init(ctx);
1474
1475 if (!(dev->quirks & IS_BIFROST)) {
1476 for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c)
1477 ctx->blit_blend.rt[c].shaders = _mesa_hash_table_u64_create(ctx);
1478 }
1479
1480 /* By default mask everything on */
1481 ctx->sample_mask = ~0;
1482 ctx->active_queries = true;
1483
1484 return gallium;
1485 }