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panfrost: Move the const buf emission logic out of panfrost_emit_for_draw()
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27 #include <sys/poll.h>
28 #include <errno.h>
29
30 #include "pan_bo.h"
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
34
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
50
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
55 #include "pan_util.h"
56 #include "pandecode/decode.h"
57
58 struct midgard_tiler_descriptor
59 panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
60 {
61 struct panfrost_screen *screen = pan_screen(batch->ctx->base.screen);
62 bool hierarchy = !(screen->quirks & MIDGARD_NO_HIER_TILING);
63 struct midgard_tiler_descriptor t = {0};
64 unsigned height = batch->key.height;
65 unsigned width = batch->key.width;
66
67 t.hierarchy_mask =
68 panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
69
70 /* Compute the polygon header size and use that to offset the body */
71
72 unsigned header_size = panfrost_tiler_header_size(
73 width, height, t.hierarchy_mask, hierarchy);
74
75 t.polygon_list_size = panfrost_tiler_full_size(
76 width, height, t.hierarchy_mask, hierarchy);
77
78 /* Sanity check */
79
80 if (vertex_count) {
81 struct panfrost_bo *tiler_heap;
82
83 tiler_heap = panfrost_batch_get_tiler_heap(batch);
84 t.polygon_list = panfrost_batch_get_polygon_list(batch,
85 header_size +
86 t.polygon_list_size);
87
88
89 /* Allow the entire tiler heap */
90 t.heap_start = tiler_heap->gpu;
91 t.heap_end = tiler_heap->gpu + tiler_heap->size;
92 } else {
93 struct panfrost_bo *tiler_dummy;
94
95 tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
96 header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
97
98 /* The tiler is disabled, so don't allow the tiler heap */
99 t.heap_start = tiler_dummy->gpu;
100 t.heap_end = t.heap_start;
101
102 /* Use a dummy polygon list */
103 t.polygon_list = tiler_dummy->gpu;
104
105 /* Disable the tiler */
106 if (hierarchy)
107 t.hierarchy_mask |= MALI_TILER_DISABLED;
108 else {
109 t.hierarchy_mask = MALI_TILER_USER;
110 t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
111
112 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
113 uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
114 polygon_list_body[0] = 0xa0000000; /* TODO: Just that? */
115 }
116 }
117
118 t.polygon_list_body =
119 t.polygon_list + header_size;
120
121 return t;
122 }
123
124 static void
125 panfrost_clear(
126 struct pipe_context *pipe,
127 unsigned buffers,
128 const union pipe_color_union *color,
129 double depth, unsigned stencil)
130 {
131 struct panfrost_context *ctx = pan_context(pipe);
132
133 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
134 * the existing batch targeting this FBO has draws. We could probably
135 * avoid that by replacing plain clears by quad-draws with a specific
136 * color/depth/stencil value, thus avoiding the generation of extra
137 * fragment jobs.
138 */
139 struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx);
140
141 panfrost_batch_add_fbo_bos(batch);
142 panfrost_batch_clear(batch, buffers, color, depth, stencil);
143 }
144
145 /* TODO: Bifrost requires just a mali_shared_memory, without the rest of the
146 * framebuffer */
147
148 static void
149 panfrost_attach_vt_framebuffer(struct panfrost_context *ctx)
150 {
151 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
152 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
153
154 /* If we haven't, reserve space for the framebuffer */
155
156 if (!batch->framebuffer.gpu) {
157 unsigned size = (screen->quirks & MIDGARD_SFBD) ?
158 sizeof(struct mali_single_framebuffer) :
159 sizeof(struct mali_framebuffer);
160
161 batch->framebuffer = panfrost_allocate_transient(batch, size);
162
163 /* Tag the pointer */
164 if (!(screen->quirks & MIDGARD_SFBD))
165 batch->framebuffer.gpu |= MALI_MFBD;
166 }
167
168 for (unsigned i = 0; i < PIPE_SHADER_TYPES; ++i)
169 ctx->payloads[i].postfix.shared_memory = batch->framebuffer.gpu;
170 }
171
172 /* Reset per-frame context, called on context initialisation as well as after
173 * flushing a frame */
174
175 void
176 panfrost_invalidate_frame(struct panfrost_context *ctx)
177 {
178 for (unsigned i = 0; i < PIPE_SHADER_TYPES; ++i)
179 ctx->payloads[i].postfix.shared_memory = 0;
180
181 /* TODO: When does this need to be handled? */
182 ctx->active_queries = true;
183 }
184
185 /* In practice, every field of these payloads should be configurable
186 * arbitrarily, which means these functions are basically catch-all's for
187 * as-of-yet unwavering unknowns */
188
189 static void
190 panfrost_emit_vertex_payload(struct panfrost_context *ctx)
191 {
192 /* 0x2 bit clear on 32-bit T6XX */
193
194 struct midgard_payload_vertex_tiler payload = {
195 .gl_enables = 0x4 | 0x2,
196 };
197
198 /* Vertex and compute are closely coupled, so share a payload */
199
200 memcpy(&ctx->payloads[PIPE_SHADER_VERTEX], &payload, sizeof(payload));
201 memcpy(&ctx->payloads[PIPE_SHADER_COMPUTE], &payload, sizeof(payload));
202 }
203
204 static unsigned
205 translate_tex_wrap(enum pipe_tex_wrap w)
206 {
207 switch (w) {
208 case PIPE_TEX_WRAP_REPEAT:
209 return MALI_WRAP_REPEAT;
210
211 case PIPE_TEX_WRAP_CLAMP:
212 return MALI_WRAP_CLAMP;
213
214 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
215 return MALI_WRAP_CLAMP_TO_EDGE;
216
217 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
218 return MALI_WRAP_CLAMP_TO_BORDER;
219
220 case PIPE_TEX_WRAP_MIRROR_REPEAT:
221 return MALI_WRAP_MIRRORED_REPEAT;
222
223 case PIPE_TEX_WRAP_MIRROR_CLAMP:
224 return MALI_WRAP_MIRRORED_CLAMP;
225
226 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
227 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE;
228
229 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
230 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER;
231
232 default:
233 unreachable("Invalid wrap");
234 }
235 }
236
237 static unsigned
238 panfrost_translate_compare_func(enum pipe_compare_func in)
239 {
240 switch (in) {
241 case PIPE_FUNC_NEVER:
242 return MALI_FUNC_NEVER;
243
244 case PIPE_FUNC_LESS:
245 return MALI_FUNC_LESS;
246
247 case PIPE_FUNC_EQUAL:
248 return MALI_FUNC_EQUAL;
249
250 case PIPE_FUNC_LEQUAL:
251 return MALI_FUNC_LEQUAL;
252
253 case PIPE_FUNC_GREATER:
254 return MALI_FUNC_GREATER;
255
256 case PIPE_FUNC_NOTEQUAL:
257 return MALI_FUNC_NOTEQUAL;
258
259 case PIPE_FUNC_GEQUAL:
260 return MALI_FUNC_GEQUAL;
261
262 case PIPE_FUNC_ALWAYS:
263 return MALI_FUNC_ALWAYS;
264
265 default:
266 unreachable("Invalid func");
267 }
268 }
269
270 static unsigned
271 panfrost_translate_stencil_op(enum pipe_stencil_op in)
272 {
273 switch (in) {
274 case PIPE_STENCIL_OP_KEEP:
275 return MALI_STENCIL_KEEP;
276
277 case PIPE_STENCIL_OP_ZERO:
278 return MALI_STENCIL_ZERO;
279
280 case PIPE_STENCIL_OP_REPLACE:
281 return MALI_STENCIL_REPLACE;
282
283 case PIPE_STENCIL_OP_INCR:
284 return MALI_STENCIL_INCR;
285
286 case PIPE_STENCIL_OP_DECR:
287 return MALI_STENCIL_DECR;
288
289 case PIPE_STENCIL_OP_INCR_WRAP:
290 return MALI_STENCIL_INCR_WRAP;
291
292 case PIPE_STENCIL_OP_DECR_WRAP:
293 return MALI_STENCIL_DECR_WRAP;
294
295 case PIPE_STENCIL_OP_INVERT:
296 return MALI_STENCIL_INVERT;
297
298 default:
299 unreachable("Invalid stencil op");
300 }
301 }
302
303 static void
304 panfrost_make_stencil_state(const struct pipe_stencil_state *in, struct mali_stencil_test *out)
305 {
306 out->ref = 0; /* Gallium gets it from elsewhere */
307
308 out->mask = in->valuemask;
309 out->func = panfrost_translate_compare_func(in->func);
310 out->sfail = panfrost_translate_stencil_op(in->fail_op);
311 out->dpfail = panfrost_translate_stencil_op(in->zfail_op);
312 out->dppass = panfrost_translate_stencil_op(in->zpass_op);
313 }
314
315 static void
316 panfrost_default_shader_backend(struct panfrost_context *ctx)
317 {
318 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
319 struct mali_shader_meta shader = {
320 .alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000),
321
322 .unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010,
323 .unknown2_4 = MALI_NO_MSAA | 0x4e0,
324 };
325
326 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
327 * required (independent of 32-bit/64-bit descriptors), or why it's not
328 * used on later GPU revisions. Otherwise, all shader jobs fault on
329 * these earlier chips (perhaps this is a chicken bit of some kind).
330 * More investigation is needed. */
331
332 if (screen->quirks & MIDGARD_SFBD)
333 shader.unknown2_4 |= 0x10;
334
335 struct pipe_stencil_state default_stencil = {
336 .enabled = 0,
337 .func = PIPE_FUNC_ALWAYS,
338 .fail_op = MALI_STENCIL_KEEP,
339 .zfail_op = MALI_STENCIL_KEEP,
340 .zpass_op = MALI_STENCIL_KEEP,
341 .writemask = 0xFF,
342 .valuemask = 0xFF
343 };
344
345 panfrost_make_stencil_state(&default_stencil, &shader.stencil_front);
346 shader.stencil_mask_front = default_stencil.writemask;
347
348 panfrost_make_stencil_state(&default_stencil, &shader.stencil_back);
349 shader.stencil_mask_back = default_stencil.writemask;
350
351 if (default_stencil.enabled)
352 shader.unknown2_4 |= MALI_STENCIL_TEST;
353
354 memcpy(&ctx->fragment_shader_core, &shader, sizeof(shader));
355 }
356
357 bool
358 panfrost_writes_point_size(struct panfrost_context *ctx)
359 {
360 assert(ctx->shader[PIPE_SHADER_VERTEX]);
361 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
362
363 return vs->writes_point_size && ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.draw_mode == MALI_POINTS;
364 }
365
366 /* Stage the attribute descriptors so we can adjust src_offset
367 * to let BOs align nicely */
368
369 static void
370 panfrost_stage_attributes(struct panfrost_context *ctx)
371 {
372 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
373 struct panfrost_vertex_state *so = ctx->vertex;
374
375 size_t sz = sizeof(struct mali_attr_meta) * PAN_MAX_ATTRIBUTE;
376 struct panfrost_transfer transfer = panfrost_allocate_transient(batch, sz);
377 struct mali_attr_meta *target = (struct mali_attr_meta *) transfer.cpu;
378
379 /* Copy as-is for the first pass */
380 memcpy(target, so->hw, sz);
381
382 /* Fixup offsets for the second pass. Recall that the hardware
383 * calculates attribute addresses as:
384 *
385 * addr = base + (stride * vtx) + src_offset;
386 *
387 * However, on Mali, base must be aligned to 64-bytes, so we
388 * instead let:
389 *
390 * base' = base & ~63 = base - (base & 63)
391 *
392 * To compensate when using base' (see emit_vertex_data), we have
393 * to adjust src_offset by the masked off piece:
394 *
395 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
396 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
397 * = base + (stride * vtx) + src_offset
398 * = addr;
399 *
400 * QED.
401 */
402
403 unsigned start = ctx->payloads[PIPE_SHADER_VERTEX].offset_start;
404
405 for (unsigned i = 0; i < so->num_elements; ++i) {
406 unsigned vbi = so->pipe[i].vertex_buffer_index;
407 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
408 struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer.resource);
409 mali_ptr addr = rsrc->bo->gpu + buf->buffer_offset;
410
411 /* Adjust by the masked off bits of the offset. Make sure we
412 * read src_offset from so->hw (which is not GPU visible)
413 * rather than target (which is) due to caching effects */
414
415 unsigned src_offset = so->hw[i].src_offset;
416 src_offset += (addr & 63);
417
418 /* Also, somewhat obscurely per-instance data needs to be
419 * offset in response to a delayed start in an indexed draw */
420
421 if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
422 src_offset -= buf->stride * start;
423
424 target[i].src_offset = src_offset;
425 }
426
427 /* Let's also include vertex builtins */
428
429 struct mali_attr_meta builtin = {
430 .format = MALI_R32UI,
431 .swizzle = panfrost_get_default_swizzle(1)
432 };
433
434 /* See mali_attr_meta specification for the magic number */
435
436 builtin.index = so->vertexid_index;
437 memcpy(&target[PAN_VERTEX_ID], &builtin, 4);
438
439 builtin.index = so->vertexid_index + 1;
440 memcpy(&target[PAN_INSTANCE_ID], &builtin, 4);
441
442 ctx->payloads[PIPE_SHADER_VERTEX].postfix.attribute_meta = transfer.gpu;
443 }
444
445 static void
446 panfrost_upload_sampler_descriptors(struct panfrost_context *ctx)
447 {
448 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
449 size_t desc_size = sizeof(struct mali_sampler_descriptor);
450
451 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
452 mali_ptr upload = 0;
453
454 if (ctx->sampler_count[t]) {
455 size_t transfer_size = desc_size * ctx->sampler_count[t];
456
457 struct panfrost_transfer transfer =
458 panfrost_allocate_transient(batch, transfer_size);
459
460 struct mali_sampler_descriptor *desc =
461 (struct mali_sampler_descriptor *) transfer.cpu;
462
463 for (int i = 0; i < ctx->sampler_count[t]; ++i)
464 desc[i] = ctx->samplers[t][i]->hw;
465
466 upload = transfer.gpu;
467 }
468
469 ctx->payloads[t].postfix.sampler_descriptor = upload;
470 }
471 }
472
473 static mali_ptr
474 panfrost_upload_tex(
475 struct panfrost_context *ctx,
476 enum pipe_shader_type st,
477 struct panfrost_sampler_view *view)
478 {
479 if (!view)
480 return (mali_ptr) 0;
481
482 struct pipe_sampler_view *pview = &view->base;
483 struct panfrost_resource *rsrc = pan_resource(pview->texture);
484
485 /* Add the BO to the job so it's retained until the job is done. */
486 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
487
488 panfrost_batch_add_bo(batch, rsrc->bo,
489 PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
490 panfrost_bo_access_for_stage(st));
491
492 panfrost_batch_add_bo(batch, view->bo,
493 PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
494 panfrost_bo_access_for_stage(st));
495
496 return view->bo->gpu;
497 }
498
499 static void
500 panfrost_upload_texture_descriptors(struct panfrost_context *ctx)
501 {
502 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
503
504 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
505 mali_ptr trampoline = 0;
506
507 if (ctx->sampler_view_count[t]) {
508 uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
509
510 for (int i = 0; i < ctx->sampler_view_count[t]; ++i)
511 trampolines[i] =
512 panfrost_upload_tex(ctx, t, ctx->sampler_views[t][i]);
513
514 trampoline = panfrost_upload_transient(batch, trampolines, sizeof(uint64_t) * ctx->sampler_view_count[t]);
515 }
516
517 ctx->payloads[t].postfix.texture_trampoline = trampoline;
518 }
519 }
520
521 /* Compute number of UBOs active (more specifically, compute the highest UBO
522 * number addressable -- if there are gaps, include them in the count anyway).
523 * We always include UBO #0 in the count, since we *need* uniforms enabled for
524 * sysvals. */
525
526 unsigned
527 panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
528 {
529 unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
530 return 32 - __builtin_clz(mask);
531 }
532
533 /* Fixes up a shader state with current state */
534
535 static void
536 panfrost_patch_shader_state(struct panfrost_context *ctx,
537 enum pipe_shader_type stage)
538 {
539 struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, stage);
540
541 if (!ss) {
542 ctx->payloads[stage].postfix.shader = 0;
543 return;
544 }
545
546 ss->tripipe->texture_count = ctx->sampler_view_count[stage];
547 ss->tripipe->sampler_count = ctx->sampler_count[stage];
548
549 ss->tripipe->midgard1.flags_lo = 0x220;
550
551 unsigned ubo_count = panfrost_ubo_count(ctx, stage);
552 ss->tripipe->midgard1.uniform_buffer_count = ubo_count;
553
554 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
555
556 /* Add the shader BO to the batch. */
557 panfrost_batch_add_bo(batch, ss->bo,
558 PAN_BO_ACCESS_PRIVATE |
559 PAN_BO_ACCESS_READ |
560 panfrost_bo_access_for_stage(stage));
561
562 ctx->payloads[stage].postfix.shader = panfrost_upload_transient(batch,
563 ss->tripipe,
564 sizeof(struct mali_shader_meta));
565 }
566
567 /* Go through dirty flags and actualise them in the cmdstream. */
568
569 void
570 panfrost_emit_for_draw(struct panfrost_context *ctx, bool with_vertex_data)
571 {
572 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
573 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
574
575 panfrost_batch_add_fbo_bos(batch);
576 panfrost_attach_vt_framebuffer(ctx);
577
578 if (with_vertex_data) {
579 panfrost_emit_vertex_data(batch);
580
581 /* Varyings emitted for -all- geometry */
582 unsigned total_count = ctx->padded_count * ctx->instance_count;
583 panfrost_emit_varying_descriptor(ctx, total_count);
584 }
585
586
587 if (ctx->rasterizer) {
588 bool msaa = ctx->rasterizer->base.multisample;
589 ctx->payloads[PIPE_SHADER_FRAGMENT].gl_enables = ctx->rasterizer->tiler_gl_enables;
590
591 /* TODO: Sample size */
592 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_HAS_MSAA, msaa);
593 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_MSAA, !msaa);
594 }
595
596 panfrost_batch_set_requirements(batch);
597
598 if (ctx->occlusion_query) {
599 ctx->payloads[PIPE_SHADER_FRAGMENT].gl_enables |= MALI_OCCLUSION_QUERY;
600 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.occlusion_counter = ctx->occlusion_query->bo->gpu;
601 }
602
603 panfrost_patch_shader_state(ctx, PIPE_SHADER_VERTEX);
604 panfrost_patch_shader_state(ctx, PIPE_SHADER_COMPUTE);
605
606 if (ctx->shader[PIPE_SHADER_VERTEX] && ctx->shader[PIPE_SHADER_FRAGMENT]) {
607 /* Check if we need to link the gl_PointSize varying */
608 if (!panfrost_writes_point_size(ctx)) {
609 /* If the size is constant, write it out. Otherwise,
610 * don't touch primitive_size (since we would clobber
611 * the pointer there) */
612
613 bool points = ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.draw_mode == MALI_POINTS;
614
615 ctx->payloads[PIPE_SHADER_FRAGMENT].primitive_size.constant = points ?
616 ctx->rasterizer->base.point_size :
617 ctx->rasterizer->base.line_width;
618 }
619 }
620
621 if (ctx->shader[PIPE_SHADER_FRAGMENT]) {
622 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
623
624 panfrost_patch_shader_state(ctx, PIPE_SHADER_FRAGMENT);
625
626 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
627
628 COPY(shader);
629 COPY(attribute_count);
630 COPY(varying_count);
631 COPY(texture_count);
632 COPY(sampler_count);
633 COPY(midgard1.uniform_count);
634 COPY(midgard1.uniform_buffer_count);
635 COPY(midgard1.work_count);
636 COPY(midgard1.flags_lo);
637 COPY(midgard1.flags_hi);
638
639 #undef COPY
640
641 /* Get blending setup */
642 unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
643
644 struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS];
645 unsigned shader_offset = 0;
646 struct panfrost_bo *shader_bo = NULL;
647
648 for (unsigned c = 0; c < rt_count; ++c) {
649 blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo, &shader_offset);
650 }
651
652 /* If there is a blend shader, work registers are shared. XXX: opt */
653
654 for (unsigned c = 0; c < rt_count; ++c) {
655 if (blend[c].is_shader)
656 ctx->fragment_shader_core.midgard1.work_count = 16;
657 }
658
659 /* Depending on whether it's legal to in the given shader, we
660 * try to enable early-z testing (or forward-pixel kill?) */
661
662 SET_BIT(ctx->fragment_shader_core.midgard1.flags_lo, MALI_EARLY_Z,
663 !variant->can_discard && !variant->writes_depth);
664
665 /* Add the writes Z/S flags if needed. */
666 SET_BIT(ctx->fragment_shader_core.midgard1.flags_lo,
667 MALI_WRITES_Z, variant->writes_depth);
668 SET_BIT(ctx->fragment_shader_core.midgard1.flags_hi,
669 MALI_WRITES_S, variant->writes_stencil);
670
671 /* Any time texturing is used, derivatives are implicitly
672 * calculated, so we need to enable helper invocations */
673
674 SET_BIT(ctx->fragment_shader_core.midgard1.flags_lo, MALI_HELPER_INVOCATIONS, variant->helper_invocations);
675
676 /* Assign the stencil refs late */
677
678 unsigned front_ref = ctx->stencil_ref.ref_value[0];
679 unsigned back_ref = ctx->stencil_ref.ref_value[1];
680 bool back_enab = ctx->depth_stencil->stencil[1].enabled;
681
682 ctx->fragment_shader_core.stencil_front.ref = front_ref;
683 ctx->fragment_shader_core.stencil_back.ref = back_enab ? back_ref : front_ref;
684
685 /* CAN_DISCARD should be set if the fragment shader possibly
686 * contains a 'discard' instruction. It is likely this is
687 * related to optimizations related to forward-pixel kill, as
688 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
689 * thing?" by Peter Harris
690 */
691
692 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_CAN_DISCARD, variant->can_discard);
693 SET_BIT(ctx->fragment_shader_core.midgard1.flags_lo, 0x400, variant->can_discard);
694
695 /* Even on MFBD, the shader descriptor gets blend shaders. It's
696 * *also* copied to the blend_meta appended (by convention),
697 * but this is the field actually read by the hardware. (Or
698 * maybe both are read...?). Specify the last RTi with a blend
699 * shader. */
700
701 ctx->fragment_shader_core.blend.shader = 0;
702
703 for (signed rt = (rt_count - 1); rt >= 0; --rt) {
704 if (blend[rt].is_shader) {
705 ctx->fragment_shader_core.blend.shader =
706 blend[rt].shader.gpu | blend[rt].shader.first_tag;
707 break;
708 }
709 }
710
711 if (screen->quirks & MIDGARD_SFBD) {
712 /* When only a single render target platform is used, the blend
713 * information is inside the shader meta itself. We
714 * additionally need to signal CAN_DISCARD for nontrivial blend
715 * modes (so we're able to read back the destination buffer) */
716
717 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_HAS_BLEND_SHADER, blend[0].is_shader);
718
719 if (!blend[0].is_shader) {
720 ctx->fragment_shader_core.blend.equation =
721 *blend[0].equation.equation;
722 ctx->fragment_shader_core.blend.constant =
723 blend[0].equation.constant;
724 }
725
726 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_CAN_DISCARD, !blend[0].no_blending);
727 }
728
729 size_t size = sizeof(struct mali_shader_meta) + (sizeof(struct midgard_blend_rt) * rt_count);
730 struct panfrost_transfer transfer = panfrost_allocate_transient(batch, size);
731 memcpy(transfer.cpu, &ctx->fragment_shader_core, sizeof(struct mali_shader_meta));
732
733 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.shader = transfer.gpu;
734
735 if (!(screen->quirks & MIDGARD_SFBD)) {
736 /* Additional blend descriptor tacked on for jobs using MFBD */
737
738 struct midgard_blend_rt rts[4];
739
740 for (unsigned i = 0; i < rt_count; ++i) {
741 rts[i].flags = 0x200;
742
743 bool is_srgb =
744 (ctx->pipe_framebuffer.nr_cbufs > i) &&
745 (ctx->pipe_framebuffer.cbufs[i]) &&
746 util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format);
747
748 SET_BIT(rts[i].flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader);
749 SET_BIT(rts[i].flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending);
750 SET_BIT(rts[i].flags, MALI_BLEND_SRGB, is_srgb);
751 SET_BIT(rts[i].flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither);
752
753 if (blend[i].is_shader) {
754 rts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag;
755 } else {
756 rts[i].blend.equation = *blend[i].equation.equation;
757 rts[i].blend.constant = blend[i].equation.constant;
758 }
759 }
760
761 memcpy(transfer.cpu + sizeof(struct mali_shader_meta), rts, sizeof(rts[0]) * rt_count);
762 }
763 }
764
765 /* We stage to transient, so always dirty.. */
766 if (ctx->vertex)
767 panfrost_stage_attributes(ctx);
768
769 panfrost_upload_sampler_descriptors(ctx);
770 panfrost_upload_texture_descriptors(ctx);
771
772 for (int i = 0; i < PIPE_SHADER_TYPES; ++i)
773 panfrost_emit_const_buf(batch, i, &ctx->payloads[i]);
774
775 /* TODO: Upload the viewport somewhere more appropriate */
776
777 panfrost_emit_viewport(batch, &ctx->payloads[PIPE_SHADER_FRAGMENT]);
778 }
779
780 /* Corresponds to exactly one draw, but does not submit anything */
781
782 static void
783 panfrost_queue_draw(struct panfrost_context *ctx)
784 {
785 /* Handle dirty flags now */
786 panfrost_emit_for_draw(ctx, true);
787
788 /* If rasterizer discard is enable, only submit the vertex */
789
790 bool rasterizer_discard = ctx->rasterizer
791 && ctx->rasterizer->base.rasterizer_discard;
792
793
794 struct midgard_payload_vertex_tiler *vertex_payload = &ctx->payloads[PIPE_SHADER_VERTEX];
795 struct midgard_payload_vertex_tiler *tiler_payload = &ctx->payloads[PIPE_SHADER_FRAGMENT];
796
797 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
798 bool wallpapering = ctx->wallpaper_batch && batch->tiler_dep;
799
800 if (wallpapering) {
801 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
802 panfrost_new_job(batch, JOB_TYPE_TILER, false, batch->job_index + 2, tiler_payload, sizeof(*tiler_payload), true);
803 panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0, vertex_payload, sizeof(*vertex_payload), true);
804 } else {
805 unsigned vertex = panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0, vertex_payload, sizeof(*vertex_payload), false);
806
807 if (!rasterizer_discard)
808 panfrost_new_job(batch, JOB_TYPE_TILER, false, vertex, tiler_payload, sizeof(*tiler_payload), false);
809 }
810
811 panfrost_batch_adjust_stack_size(batch);
812 }
813
814 /* The entire frame is in memory -- send it off to the kernel! */
815
816 void
817 panfrost_flush(
818 struct pipe_context *pipe,
819 struct pipe_fence_handle **fence,
820 unsigned flags)
821 {
822 struct panfrost_context *ctx = pan_context(pipe);
823 struct util_dynarray fences;
824
825 /* We must collect the fences before the flush is done, otherwise we'll
826 * lose track of them.
827 */
828 if (fence) {
829 util_dynarray_init(&fences, NULL);
830 hash_table_foreach(ctx->batches, hentry) {
831 struct panfrost_batch *batch = hentry->data;
832
833 panfrost_batch_fence_reference(batch->out_sync);
834 util_dynarray_append(&fences,
835 struct panfrost_batch_fence *,
836 batch->out_sync);
837 }
838 }
839
840 /* Submit all pending jobs */
841 panfrost_flush_all_batches(ctx, false);
842
843 if (fence) {
844 struct panfrost_fence *f = panfrost_fence_create(ctx, &fences);
845 pipe->screen->fence_reference(pipe->screen, fence, NULL);
846 *fence = (struct pipe_fence_handle *)f;
847
848 util_dynarray_foreach(&fences, struct panfrost_batch_fence *, fence)
849 panfrost_batch_fence_unreference(*fence);
850
851 util_dynarray_fini(&fences);
852 }
853
854 if (pan_debug & PAN_DBG_TRACE)
855 pandecode_next_frame();
856 }
857
858 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
859
860 static int
861 g2m_draw_mode(enum pipe_prim_type mode)
862 {
863 switch (mode) {
864 DEFINE_CASE(POINTS);
865 DEFINE_CASE(LINES);
866 DEFINE_CASE(LINE_LOOP);
867 DEFINE_CASE(LINE_STRIP);
868 DEFINE_CASE(TRIANGLES);
869 DEFINE_CASE(TRIANGLE_STRIP);
870 DEFINE_CASE(TRIANGLE_FAN);
871 DEFINE_CASE(QUADS);
872 DEFINE_CASE(QUAD_STRIP);
873 DEFINE_CASE(POLYGON);
874
875 default:
876 unreachable("Invalid draw mode");
877 }
878 }
879
880 #undef DEFINE_CASE
881
882 static unsigned
883 panfrost_translate_index_size(unsigned size)
884 {
885 switch (size) {
886 case 1:
887 return MALI_DRAW_INDEXED_UINT8;
888
889 case 2:
890 return MALI_DRAW_INDEXED_UINT16;
891
892 case 4:
893 return MALI_DRAW_INDEXED_UINT32;
894
895 default:
896 unreachable("Invalid index size");
897 }
898 }
899
900 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
901 * good for the duration of the draw (transient), could last longer. Also get
902 * the bounds on the index buffer for the range accessed by the draw. We do
903 * these operations together because there are natural optimizations which
904 * require them to be together. */
905
906 static mali_ptr
907 panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, const struct pipe_draw_info *info, unsigned *min_index, unsigned *max_index)
908 {
909 struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
910
911 off_t offset = info->start * info->index_size;
912 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
913 mali_ptr out = 0;
914
915 bool needs_indices = true;
916
917 if (info->max_index != ~0u) {
918 *min_index = info->min_index;
919 *max_index = info->max_index;
920 needs_indices = false;
921 }
922
923 if (!info->has_user_indices) {
924 /* Only resources can be directly mapped */
925 panfrost_batch_add_bo(batch, rsrc->bo,
926 PAN_BO_ACCESS_SHARED |
927 PAN_BO_ACCESS_READ |
928 PAN_BO_ACCESS_VERTEX_TILER);
929 out = rsrc->bo->gpu + offset;
930
931 /* Check the cache */
932 needs_indices = !panfrost_minmax_cache_get(rsrc->index_cache, info->start, info->count,
933 min_index, max_index);
934 } else {
935 /* Otherwise, we need to upload to transient memory */
936 const uint8_t *ibuf8 = (const uint8_t *) info->index.user;
937 out = panfrost_upload_transient(batch, ibuf8 + offset, info->count * info->index_size);
938 }
939
940 if (needs_indices) {
941 /* Fallback */
942 u_vbuf_get_minmax_index(&ctx->base, info, min_index, max_index);
943
944 if (!info->has_user_indices) {
945 panfrost_minmax_cache_add(rsrc->index_cache, info->start, info->count,
946 *min_index, *max_index);
947 }
948 }
949
950
951 return out;
952 }
953
954 static bool
955 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
956 {
957 const struct pipe_scissor_state *ss = &ctx->scissor;
958
959 /* Check if we're scissoring at all */
960
961 if (!(ctx->rasterizer && ctx->rasterizer->base.scissor))
962 return false;
963
964 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
965 }
966
967 /* Count generated primitives (when there is no geom/tess shaders) for
968 * transform feedback */
969
970 static void
971 panfrost_statistics_record(
972 struct panfrost_context *ctx,
973 const struct pipe_draw_info *info)
974 {
975 if (!ctx->active_queries)
976 return;
977
978 uint32_t prims = u_prims_for_vertices(info->mode, info->count);
979 ctx->prims_generated += prims;
980
981 if (!ctx->streamout.num_targets)
982 return;
983
984 ctx->tf_prims_generated += prims;
985 }
986
987 static void
988 panfrost_draw_vbo(
989 struct pipe_context *pipe,
990 const struct pipe_draw_info *info)
991 {
992 struct panfrost_context *ctx = pan_context(pipe);
993
994 /* First of all, check the scissor to see if anything is drawn at all.
995 * If it's not, we drop the draw (mostly a conformance issue;
996 * well-behaved apps shouldn't hit this) */
997
998 if (panfrost_scissor_culls_everything(ctx))
999 return;
1000
1001 int mode = info->mode;
1002
1003 /* Fallback unsupported restart index */
1004 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
1005
1006 if (info->primitive_restart && info->index_size
1007 && info->restart_index != primitive_index) {
1008 util_draw_vbo_without_prim_restart(pipe, info);
1009 return;
1010 }
1011
1012 /* Fallback for unsupported modes */
1013
1014 assert(ctx->rasterizer != NULL);
1015
1016 if (!(ctx->draw_modes & (1 << mode))) {
1017 if (mode == PIPE_PRIM_QUADS && info->count == 4 && !ctx->rasterizer->base.flatshade) {
1018 mode = PIPE_PRIM_TRIANGLE_FAN;
1019 } else {
1020 if (info->count < 4) {
1021 /* Degenerate case? */
1022 return;
1023 }
1024
1025 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
1026 util_primconvert_draw_vbo(ctx->primconvert, info);
1027 return;
1028 }
1029 }
1030
1031 ctx->payloads[PIPE_SHADER_VERTEX].offset_start = info->start;
1032 ctx->payloads[PIPE_SHADER_FRAGMENT].offset_start = info->start;
1033
1034 /* Now that we have a guaranteed terminating path, find the job.
1035 * Assignment commented out to prevent unused warning */
1036
1037 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx);
1038
1039 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.draw_mode = g2m_draw_mode(mode);
1040
1041 /* Take into account a negative bias */
1042 ctx->vertex_count = info->count + abs(info->index_bias);
1043 ctx->instance_count = info->instance_count;
1044 ctx->active_prim = info->mode;
1045
1046 /* For non-indexed draws, they're the same */
1047 unsigned vertex_count = ctx->vertex_count;
1048
1049 unsigned draw_flags = 0;
1050
1051 /* The draw flags interpret how primitive size is interpreted */
1052
1053 if (panfrost_writes_point_size(ctx))
1054 draw_flags |= MALI_DRAW_VARYING_SIZE;
1055
1056 if (info->primitive_restart)
1057 draw_flags |= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX;
1058
1059 /* These doesn't make much sense */
1060
1061 draw_flags |= 0x3000;
1062
1063 if (ctx->rasterizer && ctx->rasterizer->base.flatshade_first)
1064 draw_flags |= MALI_DRAW_FLATSHADE_FIRST;
1065
1066 panfrost_statistics_record(ctx, info);
1067
1068 if (info->index_size) {
1069 unsigned min_index = 0, max_index = 0;
1070 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.indices =
1071 panfrost_get_index_buffer_bounded(ctx, info, &min_index, &max_index);
1072
1073 /* Use the corresponding values */
1074 vertex_count = max_index - min_index + 1;
1075 ctx->payloads[PIPE_SHADER_VERTEX].offset_start = min_index + info->index_bias;
1076 ctx->payloads[PIPE_SHADER_FRAGMENT].offset_start = min_index + info->index_bias;
1077
1078 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.offset_bias_correction = -min_index;
1079 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.index_count = MALI_POSITIVE(info->count);
1080
1081 draw_flags |= panfrost_translate_index_size(info->index_size);
1082 } else {
1083 /* Index count == vertex count, if no indexing is applied, as
1084 * if it is internally indexed in the expected order */
1085
1086 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.offset_bias_correction = 0;
1087 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.index_count = MALI_POSITIVE(ctx->vertex_count);
1088
1089 /* Reverse index state */
1090 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.indices = (mali_ptr) 0;
1091 }
1092
1093 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1094 * vertex_count, 1) */
1095
1096 panfrost_pack_work_groups_fused(
1097 &ctx->payloads[PIPE_SHADER_VERTEX].prefix,
1098 &ctx->payloads[PIPE_SHADER_FRAGMENT].prefix,
1099 1, vertex_count, info->instance_count,
1100 1, 1, 1);
1101
1102 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.unknown_draw = draw_flags;
1103
1104 /* Encode the padded vertex count */
1105
1106 if (info->instance_count > 1) {
1107 ctx->padded_count = panfrost_padded_vertex_count(vertex_count);
1108
1109 unsigned shift = __builtin_ctz(ctx->padded_count);
1110 unsigned k = ctx->padded_count >> (shift + 1);
1111
1112 ctx->payloads[PIPE_SHADER_VERTEX].instance_shift = shift;
1113 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_shift = shift;
1114
1115 ctx->payloads[PIPE_SHADER_VERTEX].instance_odd = k;
1116 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_odd = k;
1117 } else {
1118 ctx->padded_count = vertex_count;
1119
1120 /* Reset instancing state */
1121 ctx->payloads[PIPE_SHADER_VERTEX].instance_shift = 0;
1122 ctx->payloads[PIPE_SHADER_VERTEX].instance_odd = 0;
1123 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_shift = 0;
1124 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_odd = 0;
1125 }
1126
1127 /* Fire off the draw itself */
1128 panfrost_queue_draw(ctx);
1129
1130 /* Increment transform feedback offsets */
1131
1132 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
1133 unsigned output_count = u_stream_outputs_for_vertices(
1134 ctx->active_prim, ctx->vertex_count);
1135
1136 ctx->streamout.offsets[i] += output_count;
1137 }
1138 }
1139
1140 /* CSO state */
1141
1142 static void
1143 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
1144 {
1145 free(hwcso);
1146 }
1147
1148 static void *
1149 panfrost_create_rasterizer_state(
1150 struct pipe_context *pctx,
1151 const struct pipe_rasterizer_state *cso)
1152 {
1153 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
1154
1155 so->base = *cso;
1156
1157 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1158 so->tiler_gl_enables = 0x7;
1159
1160 if (cso->front_ccw)
1161 so->tiler_gl_enables |= MALI_FRONT_CCW_TOP;
1162
1163 if (cso->cull_face & PIPE_FACE_FRONT)
1164 so->tiler_gl_enables |= MALI_CULL_FACE_FRONT;
1165
1166 if (cso->cull_face & PIPE_FACE_BACK)
1167 so->tiler_gl_enables |= MALI_CULL_FACE_BACK;
1168
1169 return so;
1170 }
1171
1172 static void
1173 panfrost_bind_rasterizer_state(
1174 struct pipe_context *pctx,
1175 void *hwcso)
1176 {
1177 struct panfrost_context *ctx = pan_context(pctx);
1178
1179 ctx->rasterizer = hwcso;
1180
1181 if (!hwcso)
1182 return;
1183
1184 ctx->fragment_shader_core.depth_units = ctx->rasterizer->base.offset_units * 2.0f;
1185 ctx->fragment_shader_core.depth_factor = ctx->rasterizer->base.offset_scale;
1186
1187 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1188 assert(ctx->rasterizer->base.offset_clamp == 0.0);
1189
1190 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1191
1192 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_DEPTH_RANGE_A, ctx->rasterizer->base.offset_tri);
1193 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_DEPTH_RANGE_B, ctx->rasterizer->base.offset_tri);
1194
1195 /* Point sprites are emulated */
1196
1197 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
1198
1199 if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
1200 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
1201 }
1202
1203 static void *
1204 panfrost_create_vertex_elements_state(
1205 struct pipe_context *pctx,
1206 unsigned num_elements,
1207 const struct pipe_vertex_element *elements)
1208 {
1209 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
1210
1211 so->num_elements = num_elements;
1212 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
1213
1214 for (int i = 0; i < num_elements; ++i) {
1215 so->hw[i].index = i;
1216
1217 enum pipe_format fmt = elements[i].src_format;
1218 const struct util_format_description *desc = util_format_description(fmt);
1219 so->hw[i].unknown1 = 0x2;
1220 so->hw[i].swizzle = panfrost_get_default_swizzle(desc->nr_channels);
1221
1222 so->hw[i].format = panfrost_find_format(desc);
1223
1224 /* The field itself should probably be shifted over */
1225 so->hw[i].src_offset = elements[i].src_offset;
1226 }
1227
1228 return so;
1229 }
1230
1231 static void
1232 panfrost_bind_vertex_elements_state(
1233 struct pipe_context *pctx,
1234 void *hwcso)
1235 {
1236 struct panfrost_context *ctx = pan_context(pctx);
1237 ctx->vertex = hwcso;
1238 }
1239
1240 static void *
1241 panfrost_create_shader_state(
1242 struct pipe_context *pctx,
1243 const struct pipe_shader_state *cso,
1244 enum pipe_shader_type stage)
1245 {
1246 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
1247 so->base = *cso;
1248
1249 /* Token deep copy to prevent memory corruption */
1250
1251 if (cso->type == PIPE_SHADER_IR_TGSI)
1252 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
1253
1254 /* Precompile for shader-db if we need to */
1255 if (unlikely((pan_debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
1256 struct panfrost_context *ctx = pan_context(pctx);
1257
1258 struct mali_shader_meta meta;
1259 struct panfrost_shader_state state;
1260 uint64_t outputs_written;
1261
1262 panfrost_shader_compile(ctx, &meta,
1263 PIPE_SHADER_IR_NIR,
1264 so->base.ir.nir,
1265 tgsi_processor_to_shader_stage(stage), &state,
1266 &outputs_written);
1267 }
1268
1269 return so;
1270 }
1271
1272 static void
1273 panfrost_delete_shader_state(
1274 struct pipe_context *pctx,
1275 void *so)
1276 {
1277 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
1278
1279 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
1280 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1281 }
1282
1283 for (unsigned i = 0; i < cso->variant_count; ++i) {
1284 struct panfrost_shader_state *shader_state = &cso->variants[i];
1285 panfrost_bo_unreference(shader_state->bo);
1286 shader_state->bo = NULL;
1287 }
1288 free(cso->variants);
1289
1290 free(so);
1291 }
1292
1293 static void *
1294 panfrost_create_sampler_state(
1295 struct pipe_context *pctx,
1296 const struct pipe_sampler_state *cso)
1297 {
1298 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
1299 so->base = *cso;
1300
1301 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1302
1303 bool min_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
1304 bool mag_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
1305 bool mip_linear = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR;
1306
1307 unsigned min_filter = min_nearest ? MALI_SAMP_MIN_NEAREST : 0;
1308 unsigned mag_filter = mag_nearest ? MALI_SAMP_MAG_NEAREST : 0;
1309 unsigned mip_filter = mip_linear ?
1310 (MALI_SAMP_MIP_LINEAR_1 | MALI_SAMP_MIP_LINEAR_2) : 0;
1311 unsigned normalized = cso->normalized_coords ? MALI_SAMP_NORM_COORDS : 0;
1312
1313 struct mali_sampler_descriptor sampler_descriptor = {
1314 .filter_mode = min_filter | mag_filter | mip_filter | normalized,
1315 .wrap_s = translate_tex_wrap(cso->wrap_s),
1316 .wrap_t = translate_tex_wrap(cso->wrap_t),
1317 .wrap_r = translate_tex_wrap(cso->wrap_r),
1318 .compare_func = panfrost_flip_compare_func(
1319 panfrost_translate_compare_func(
1320 cso->compare_func)),
1321 .border_color = {
1322 cso->border_color.f[0],
1323 cso->border_color.f[1],
1324 cso->border_color.f[2],
1325 cso->border_color.f[3]
1326 },
1327 .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */
1328 .max_lod = FIXED_16(cso->max_lod, false),
1329 .lod_bias = FIXED_16(cso->lod_bias, true), /* can be negative */
1330 .seamless_cube_map = cso->seamless_cube_map,
1331 };
1332
1333 /* If necessary, we disable mipmapping in the sampler descriptor by
1334 * clamping the LOD as tight as possible (from 0 to epsilon,
1335 * essentially -- remember these are fixed point numbers, so
1336 * epsilon=1/256) */
1337
1338 if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) {
1339 sampler_descriptor.max_lod = sampler_descriptor.min_lod;
1340
1341 /* Enforce that there is something in the middle by adding epsilon*/
1342
1343 if (sampler_descriptor.min_lod == sampler_descriptor.max_lod)
1344 sampler_descriptor.max_lod++;
1345
1346 /* Sanity check */
1347 assert(sampler_descriptor.max_lod > sampler_descriptor.min_lod);
1348 }
1349
1350 so->hw = sampler_descriptor;
1351
1352 return so;
1353 }
1354
1355 static void
1356 panfrost_bind_sampler_states(
1357 struct pipe_context *pctx,
1358 enum pipe_shader_type shader,
1359 unsigned start_slot, unsigned num_sampler,
1360 void **sampler)
1361 {
1362 assert(start_slot == 0);
1363
1364 struct panfrost_context *ctx = pan_context(pctx);
1365
1366 /* XXX: Should upload, not just copy? */
1367 ctx->sampler_count[shader] = num_sampler;
1368 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
1369 }
1370
1371 static bool
1372 panfrost_variant_matches(
1373 struct panfrost_context *ctx,
1374 struct panfrost_shader_state *variant,
1375 enum pipe_shader_type type)
1376 {
1377 struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
1378 struct pipe_alpha_state *alpha = &ctx->depth_stencil->alpha;
1379
1380 bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
1381
1382 if (is_fragment && (alpha->enabled || variant->alpha_state.enabled)) {
1383 /* Make sure enable state is at least the same */
1384 if (alpha->enabled != variant->alpha_state.enabled) {
1385 return false;
1386 }
1387
1388 /* Check that the contents of the test are the same */
1389 bool same_func = alpha->func == variant->alpha_state.func;
1390 bool same_ref = alpha->ref_value == variant->alpha_state.ref_value;
1391
1392 if (!(same_func && same_ref)) {
1393 return false;
1394 }
1395 }
1396
1397 if (is_fragment && rasterizer && (rasterizer->sprite_coord_enable |
1398 variant->point_sprite_mask)) {
1399 /* Ensure the same varyings are turned to point sprites */
1400 if (rasterizer->sprite_coord_enable != variant->point_sprite_mask)
1401 return false;
1402
1403 /* Ensure the orientation is correct */
1404 bool upper_left =
1405 rasterizer->sprite_coord_mode ==
1406 PIPE_SPRITE_COORD_UPPER_LEFT;
1407
1408 if (variant->point_sprite_upper_left != upper_left)
1409 return false;
1410 }
1411
1412 /* Otherwise, we're good to go */
1413 return true;
1414 }
1415
1416 /**
1417 * Fix an uncompiled shader's stream output info, and produce a bitmask
1418 * of which VARYING_SLOT_* are captured for stream output.
1419 *
1420 * Core Gallium stores output->register_index as a "slot" number, where
1421 * slots are assigned consecutively to all outputs in info->outputs_written.
1422 * This naive packing of outputs doesn't work for us - we too have slots,
1423 * but the layout is defined by the VUE map, which we won't have until we
1424 * compile a specific shader variant. So, we remap these and simply store
1425 * VARYING_SLOT_* in our copy's output->register_index fields.
1426 *
1427 * We then produce a bitmask of outputs which are used for SO.
1428 *
1429 * Implementation from iris.
1430 */
1431
1432 static uint64_t
1433 update_so_info(struct pipe_stream_output_info *so_info,
1434 uint64_t outputs_written)
1435 {
1436 uint64_t so_outputs = 0;
1437 uint8_t reverse_map[64] = {0};
1438 unsigned slot = 0;
1439
1440 while (outputs_written)
1441 reverse_map[slot++] = u_bit_scan64(&outputs_written);
1442
1443 for (unsigned i = 0; i < so_info->num_outputs; i++) {
1444 struct pipe_stream_output *output = &so_info->output[i];
1445
1446 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1447 output->register_index = reverse_map[output->register_index];
1448
1449 so_outputs |= 1ull << output->register_index;
1450 }
1451
1452 return so_outputs;
1453 }
1454
1455 static void
1456 panfrost_bind_shader_state(
1457 struct pipe_context *pctx,
1458 void *hwcso,
1459 enum pipe_shader_type type)
1460 {
1461 struct panfrost_context *ctx = pan_context(pctx);
1462 ctx->shader[type] = hwcso;
1463
1464 if (!hwcso) return;
1465
1466 /* Match the appropriate variant */
1467
1468 signed variant = -1;
1469 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
1470
1471 for (unsigned i = 0; i < variants->variant_count; ++i) {
1472 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
1473 variant = i;
1474 break;
1475 }
1476 }
1477
1478 if (variant == -1) {
1479 /* No variant matched, so create a new one */
1480 variant = variants->variant_count++;
1481
1482 if (variants->variant_count > variants->variant_space) {
1483 unsigned old_space = variants->variant_space;
1484
1485 variants->variant_space *= 2;
1486 if (variants->variant_space == 0)
1487 variants->variant_space = 1;
1488
1489 /* Arbitrary limit to stop runaway programs from
1490 * creating an unbounded number of shader variants. */
1491 assert(variants->variant_space < 1024);
1492
1493 unsigned msize = sizeof(struct panfrost_shader_state);
1494 variants->variants = realloc(variants->variants,
1495 variants->variant_space * msize);
1496
1497 memset(&variants->variants[old_space], 0,
1498 (variants->variant_space - old_space) * msize);
1499 }
1500
1501 struct panfrost_shader_state *v =
1502 &variants->variants[variant];
1503
1504 if (type == PIPE_SHADER_FRAGMENT) {
1505 v->alpha_state = ctx->depth_stencil->alpha;
1506
1507 if (ctx->rasterizer) {
1508 v->point_sprite_mask = ctx->rasterizer->base.sprite_coord_enable;
1509 v->point_sprite_upper_left =
1510 ctx->rasterizer->base.sprite_coord_mode ==
1511 PIPE_SPRITE_COORD_UPPER_LEFT;
1512 }
1513 }
1514
1515 variants->variants[variant].tripipe = calloc(1, sizeof(struct mali_shader_meta));
1516
1517 }
1518
1519 /* Select this variant */
1520 variants->active_variant = variant;
1521
1522 struct panfrost_shader_state *shader_state = &variants->variants[variant];
1523 assert(panfrost_variant_matches(ctx, shader_state, type));
1524
1525 /* We finally have a variant, so compile it */
1526
1527 if (!shader_state->compiled) {
1528 uint64_t outputs_written = 0;
1529
1530 panfrost_shader_compile(ctx, shader_state->tripipe,
1531 variants->base.type,
1532 variants->base.type == PIPE_SHADER_IR_NIR ?
1533 variants->base.ir.nir :
1534 variants->base.tokens,
1535 tgsi_processor_to_shader_stage(type), shader_state,
1536 &outputs_written);
1537
1538 shader_state->compiled = true;
1539
1540 /* Fixup the stream out information, since what Gallium returns
1541 * normally is mildly insane */
1542
1543 shader_state->stream_output = variants->base.stream_output;
1544 shader_state->so_mask =
1545 update_so_info(&shader_state->stream_output, outputs_written);
1546 }
1547 }
1548
1549 static void *
1550 panfrost_create_vs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
1551 {
1552 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
1553 }
1554
1555 static void *
1556 panfrost_create_fs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
1557 {
1558 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
1559 }
1560
1561 static void
1562 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
1563 {
1564 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
1565 }
1566
1567 static void
1568 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
1569 {
1570 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
1571 }
1572
1573 static void
1574 panfrost_set_vertex_buffers(
1575 struct pipe_context *pctx,
1576 unsigned start_slot,
1577 unsigned num_buffers,
1578 const struct pipe_vertex_buffer *buffers)
1579 {
1580 struct panfrost_context *ctx = pan_context(pctx);
1581
1582 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
1583 }
1584
1585 static void
1586 panfrost_set_constant_buffer(
1587 struct pipe_context *pctx,
1588 enum pipe_shader_type shader, uint index,
1589 const struct pipe_constant_buffer *buf)
1590 {
1591 struct panfrost_context *ctx = pan_context(pctx);
1592 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
1593
1594 util_copy_constant_buffer(&pbuf->cb[index], buf);
1595
1596 unsigned mask = (1 << index);
1597
1598 if (unlikely(!buf)) {
1599 pbuf->enabled_mask &= ~mask;
1600 pbuf->dirty_mask &= ~mask;
1601 return;
1602 }
1603
1604 pbuf->enabled_mask |= mask;
1605 pbuf->dirty_mask |= mask;
1606 }
1607
1608 static void
1609 panfrost_set_stencil_ref(
1610 struct pipe_context *pctx,
1611 const struct pipe_stencil_ref *ref)
1612 {
1613 struct panfrost_context *ctx = pan_context(pctx);
1614 ctx->stencil_ref = *ref;
1615 }
1616
1617 static enum mali_texture_type
1618 panfrost_translate_texture_type(enum pipe_texture_target t) {
1619 switch (t)
1620 {
1621 case PIPE_BUFFER:
1622 case PIPE_TEXTURE_1D:
1623 case PIPE_TEXTURE_1D_ARRAY:
1624 return MALI_TEX_1D;
1625
1626 case PIPE_TEXTURE_2D:
1627 case PIPE_TEXTURE_2D_ARRAY:
1628 case PIPE_TEXTURE_RECT:
1629 return MALI_TEX_2D;
1630
1631 case PIPE_TEXTURE_3D:
1632 return MALI_TEX_3D;
1633
1634 case PIPE_TEXTURE_CUBE:
1635 case PIPE_TEXTURE_CUBE_ARRAY:
1636 return MALI_TEX_CUBE;
1637
1638 default:
1639 unreachable("Unknown target");
1640 }
1641 }
1642
1643 static struct pipe_sampler_view *
1644 panfrost_create_sampler_view(
1645 struct pipe_context *pctx,
1646 struct pipe_resource *texture,
1647 const struct pipe_sampler_view *template)
1648 {
1649 struct panfrost_screen *screen = pan_screen(pctx->screen);
1650 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
1651
1652 pipe_reference(NULL, &texture->reference);
1653
1654 struct panfrost_resource *prsrc = (struct panfrost_resource *) texture;
1655 assert(prsrc->bo);
1656
1657 so->base = *template;
1658 so->base.texture = texture;
1659 so->base.reference.count = 1;
1660 so->base.context = pctx;
1661
1662 unsigned char user_swizzle[4] = {
1663 template->swizzle_r,
1664 template->swizzle_g,
1665 template->swizzle_b,
1666 template->swizzle_a
1667 };
1668
1669 /* In the hardware, array_size refers specifically to array textures,
1670 * whereas in Gallium, it also covers cubemaps */
1671
1672 unsigned array_size = texture->array_size;
1673
1674 if (template->target == PIPE_TEXTURE_CUBE) {
1675 /* TODO: Cubemap arrays */
1676 assert(array_size == 6);
1677 array_size /= 6;
1678 }
1679
1680 enum mali_texture_type type =
1681 panfrost_translate_texture_type(template->target);
1682
1683 unsigned size = panfrost_estimate_texture_size(
1684 template->u.tex.first_level,
1685 template->u.tex.last_level,
1686 template->u.tex.first_layer,
1687 template->u.tex.last_layer,
1688 type, prsrc->layout);
1689
1690 so->bo = panfrost_bo_create(screen, size, 0);
1691
1692 panfrost_new_texture(
1693 so->bo->cpu,
1694 texture->width0, texture->height0,
1695 texture->depth0, array_size,
1696 template->format,
1697 type, prsrc->layout,
1698 template->u.tex.first_level,
1699 template->u.tex.last_level,
1700 template->u.tex.first_layer,
1701 template->u.tex.last_layer,
1702 prsrc->cubemap_stride,
1703 panfrost_translate_swizzle_4(user_swizzle),
1704 prsrc->bo->gpu,
1705 prsrc->slices);
1706
1707 return (struct pipe_sampler_view *) so;
1708 }
1709
1710 static void
1711 panfrost_set_sampler_views(
1712 struct pipe_context *pctx,
1713 enum pipe_shader_type shader,
1714 unsigned start_slot, unsigned num_views,
1715 struct pipe_sampler_view **views)
1716 {
1717 struct panfrost_context *ctx = pan_context(pctx);
1718 unsigned new_nr = 0;
1719 unsigned i;
1720
1721 assert(start_slot == 0);
1722
1723 for (i = 0; i < num_views; ++i) {
1724 if (views[i])
1725 new_nr = i + 1;
1726 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
1727 views[i]);
1728 }
1729
1730 for (; i < ctx->sampler_view_count[shader]; i++) {
1731 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
1732 NULL);
1733 }
1734 ctx->sampler_view_count[shader] = new_nr;
1735 }
1736
1737 static void
1738 panfrost_sampler_view_destroy(
1739 struct pipe_context *pctx,
1740 struct pipe_sampler_view *pview)
1741 {
1742 struct panfrost_sampler_view *view = (struct panfrost_sampler_view *) pview;
1743
1744 pipe_resource_reference(&pview->texture, NULL);
1745 panfrost_bo_unreference(view->bo);
1746 ralloc_free(view);
1747 }
1748
1749 static void
1750 panfrost_set_shader_buffers(
1751 struct pipe_context *pctx,
1752 enum pipe_shader_type shader,
1753 unsigned start, unsigned count,
1754 const struct pipe_shader_buffer *buffers,
1755 unsigned writable_bitmask)
1756 {
1757 struct panfrost_context *ctx = pan_context(pctx);
1758
1759 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
1760 buffers, start, count);
1761 }
1762
1763 /* Hints that a framebuffer should use AFBC where possible */
1764
1765 static void
1766 panfrost_hint_afbc(
1767 struct panfrost_screen *screen,
1768 const struct pipe_framebuffer_state *fb)
1769 {
1770 /* AFBC implemenation incomplete; hide it */
1771 if (!(pan_debug & PAN_DBG_AFBC)) return;
1772
1773 /* Hint AFBC to the resources bound to each color buffer */
1774
1775 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
1776 struct pipe_surface *surf = fb->cbufs[i];
1777 struct panfrost_resource *rsrc = pan_resource(surf->texture);
1778 panfrost_resource_hint_layout(screen, rsrc, MALI_TEXTURE_AFBC, 1);
1779 }
1780
1781 /* Also hint it to the depth buffer */
1782
1783 if (fb->zsbuf) {
1784 struct panfrost_resource *rsrc = pan_resource(fb->zsbuf->texture);
1785 panfrost_resource_hint_layout(screen, rsrc, MALI_TEXTURE_AFBC, 1);
1786 }
1787 }
1788
1789 static void
1790 panfrost_set_framebuffer_state(struct pipe_context *pctx,
1791 const struct pipe_framebuffer_state *fb)
1792 {
1793 struct panfrost_context *ctx = pan_context(pctx);
1794
1795 panfrost_hint_afbc(pan_screen(pctx->screen), fb);
1796 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
1797 ctx->batch = NULL;
1798 panfrost_invalidate_frame(ctx);
1799 }
1800
1801 static void *
1802 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
1803 const struct pipe_depth_stencil_alpha_state *depth_stencil)
1804 {
1805 return mem_dup(depth_stencil, sizeof(*depth_stencil));
1806 }
1807
1808 static void
1809 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
1810 void *cso)
1811 {
1812 struct panfrost_context *ctx = pan_context(pipe);
1813 struct pipe_depth_stencil_alpha_state *depth_stencil = cso;
1814 ctx->depth_stencil = depth_stencil;
1815
1816 if (!depth_stencil)
1817 return;
1818
1819 /* Alpha does not exist in the hardware (it's not in ES3), so it's
1820 * emulated in the fragment shader */
1821
1822 if (depth_stencil->alpha.enabled) {
1823 /* We need to trigger a new shader (maybe) */
1824 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
1825 }
1826
1827 /* Stencil state */
1828 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_STENCIL_TEST, depth_stencil->stencil[0].enabled);
1829
1830 panfrost_make_stencil_state(&depth_stencil->stencil[0], &ctx->fragment_shader_core.stencil_front);
1831 ctx->fragment_shader_core.stencil_mask_front = depth_stencil->stencil[0].writemask;
1832
1833 /* If back-stencil is not enabled, use the front values */
1834 bool back_enab = ctx->depth_stencil->stencil[1].enabled;
1835 unsigned back_index = back_enab ? 1 : 0;
1836
1837 panfrost_make_stencil_state(&depth_stencil->stencil[back_index], &ctx->fragment_shader_core.stencil_back);
1838 ctx->fragment_shader_core.stencil_mask_back = depth_stencil->stencil[back_index].writemask;
1839
1840 /* Depth state (TODO: Refactor) */
1841 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_DEPTH_WRITEMASK,
1842 depth_stencil->depth.writemask);
1843
1844 int func = depth_stencil->depth.enabled ? depth_stencil->depth.func : PIPE_FUNC_ALWAYS;
1845
1846 ctx->fragment_shader_core.unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
1847 ctx->fragment_shader_core.unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func));
1848
1849 /* Bounds test not implemented */
1850 assert(!depth_stencil->depth.bounds_test);
1851 }
1852
1853 static void
1854 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
1855 {
1856 free( depth );
1857 }
1858
1859 static void
1860 panfrost_set_sample_mask(struct pipe_context *pipe,
1861 unsigned sample_mask)
1862 {
1863 }
1864
1865 static void
1866 panfrost_set_clip_state(struct pipe_context *pipe,
1867 const struct pipe_clip_state *clip)
1868 {
1869 //struct panfrost_context *panfrost = pan_context(pipe);
1870 }
1871
1872 static void
1873 panfrost_set_viewport_states(struct pipe_context *pipe,
1874 unsigned start_slot,
1875 unsigned num_viewports,
1876 const struct pipe_viewport_state *viewports)
1877 {
1878 struct panfrost_context *ctx = pan_context(pipe);
1879
1880 assert(start_slot == 0);
1881 assert(num_viewports == 1);
1882
1883 ctx->pipe_viewport = *viewports;
1884 }
1885
1886 static void
1887 panfrost_set_scissor_states(struct pipe_context *pipe,
1888 unsigned start_slot,
1889 unsigned num_scissors,
1890 const struct pipe_scissor_state *scissors)
1891 {
1892 struct panfrost_context *ctx = pan_context(pipe);
1893
1894 assert(start_slot == 0);
1895 assert(num_scissors == 1);
1896
1897 ctx->scissor = *scissors;
1898 }
1899
1900 static void
1901 panfrost_set_polygon_stipple(struct pipe_context *pipe,
1902 const struct pipe_poly_stipple *stipple)
1903 {
1904 //struct panfrost_context *panfrost = pan_context(pipe);
1905 }
1906
1907 static void
1908 panfrost_set_active_query_state(struct pipe_context *pipe,
1909 bool enable)
1910 {
1911 struct panfrost_context *ctx = pan_context(pipe);
1912 ctx->active_queries = enable;
1913 }
1914
1915 static void
1916 panfrost_destroy(struct pipe_context *pipe)
1917 {
1918 struct panfrost_context *panfrost = pan_context(pipe);
1919
1920 if (panfrost->blitter)
1921 util_blitter_destroy(panfrost->blitter);
1922
1923 if (panfrost->blitter_wallpaper)
1924 util_blitter_destroy(panfrost->blitter_wallpaper);
1925
1926 util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
1927 u_upload_destroy(pipe->stream_uploader);
1928
1929 ralloc_free(pipe);
1930 }
1931
1932 static struct pipe_query *
1933 panfrost_create_query(struct pipe_context *pipe,
1934 unsigned type,
1935 unsigned index)
1936 {
1937 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
1938
1939 q->type = type;
1940 q->index = index;
1941
1942 return (struct pipe_query *) q;
1943 }
1944
1945 static void
1946 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
1947 {
1948 struct panfrost_query *query = (struct panfrost_query *) q;
1949
1950 if (query->bo) {
1951 panfrost_bo_unreference(query->bo);
1952 query->bo = NULL;
1953 }
1954
1955 ralloc_free(q);
1956 }
1957
1958 static bool
1959 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
1960 {
1961 struct panfrost_context *ctx = pan_context(pipe);
1962 struct panfrost_query *query = (struct panfrost_query *) q;
1963
1964 switch (query->type) {
1965 case PIPE_QUERY_OCCLUSION_COUNTER:
1966 case PIPE_QUERY_OCCLUSION_PREDICATE:
1967 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1968 /* Allocate a bo for the query results to be stored */
1969 if (!query->bo) {
1970 query->bo = panfrost_bo_create(
1971 pan_screen(ctx->base.screen),
1972 sizeof(unsigned), 0);
1973 }
1974
1975 unsigned *result = (unsigned *)query->bo->cpu;
1976 *result = 0; /* Default to 0 if nothing at all drawn. */
1977 ctx->occlusion_query = query;
1978 break;
1979
1980 /* Geometry statistics are computed in the driver. XXX: geom/tess
1981 * shaders.. */
1982
1983 case PIPE_QUERY_PRIMITIVES_GENERATED:
1984 query->start = ctx->prims_generated;
1985 break;
1986 case PIPE_QUERY_PRIMITIVES_EMITTED:
1987 query->start = ctx->tf_prims_generated;
1988 break;
1989
1990 default:
1991 DBG("Skipping query %u\n", query->type);
1992 break;
1993 }
1994
1995 return true;
1996 }
1997
1998 static bool
1999 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
2000 {
2001 struct panfrost_context *ctx = pan_context(pipe);
2002 struct panfrost_query *query = (struct panfrost_query *) q;
2003
2004 switch (query->type) {
2005 case PIPE_QUERY_OCCLUSION_COUNTER:
2006 case PIPE_QUERY_OCCLUSION_PREDICATE:
2007 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
2008 ctx->occlusion_query = NULL;
2009 break;
2010 case PIPE_QUERY_PRIMITIVES_GENERATED:
2011 query->end = ctx->prims_generated;
2012 break;
2013 case PIPE_QUERY_PRIMITIVES_EMITTED:
2014 query->end = ctx->tf_prims_generated;
2015 break;
2016 }
2017
2018 return true;
2019 }
2020
2021 static bool
2022 panfrost_get_query_result(struct pipe_context *pipe,
2023 struct pipe_query *q,
2024 bool wait,
2025 union pipe_query_result *vresult)
2026 {
2027 struct panfrost_query *query = (struct panfrost_query *) q;
2028 struct panfrost_context *ctx = pan_context(pipe);
2029
2030
2031 switch (query->type) {
2032 case PIPE_QUERY_OCCLUSION_COUNTER:
2033 case PIPE_QUERY_OCCLUSION_PREDICATE:
2034 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
2035 /* Flush first */
2036 panfrost_flush_all_batches(ctx, true);
2037
2038 /* Read back the query results */
2039 unsigned *result = (unsigned *) query->bo->cpu;
2040 unsigned passed = *result;
2041
2042 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
2043 vresult->u64 = passed;
2044 } else {
2045 vresult->b = !!passed;
2046 }
2047
2048 break;
2049
2050 case PIPE_QUERY_PRIMITIVES_GENERATED:
2051 case PIPE_QUERY_PRIMITIVES_EMITTED:
2052 panfrost_flush_all_batches(ctx, true);
2053 vresult->u64 = query->end - query->start;
2054 break;
2055
2056 default:
2057 DBG("Skipped query get %u\n", query->type);
2058 break;
2059 }
2060
2061 return true;
2062 }
2063
2064 static struct pipe_stream_output_target *
2065 panfrost_create_stream_output_target(struct pipe_context *pctx,
2066 struct pipe_resource *prsc,
2067 unsigned buffer_offset,
2068 unsigned buffer_size)
2069 {
2070 struct pipe_stream_output_target *target;
2071
2072 target = rzalloc(pctx, struct pipe_stream_output_target);
2073
2074 if (!target)
2075 return NULL;
2076
2077 pipe_reference_init(&target->reference, 1);
2078 pipe_resource_reference(&target->buffer, prsc);
2079
2080 target->context = pctx;
2081 target->buffer_offset = buffer_offset;
2082 target->buffer_size = buffer_size;
2083
2084 return target;
2085 }
2086
2087 static void
2088 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
2089 struct pipe_stream_output_target *target)
2090 {
2091 pipe_resource_reference(&target->buffer, NULL);
2092 ralloc_free(target);
2093 }
2094
2095 static void
2096 panfrost_set_stream_output_targets(struct pipe_context *pctx,
2097 unsigned num_targets,
2098 struct pipe_stream_output_target **targets,
2099 const unsigned *offsets)
2100 {
2101 struct panfrost_context *ctx = pan_context(pctx);
2102 struct panfrost_streamout *so = &ctx->streamout;
2103
2104 assert(num_targets <= ARRAY_SIZE(so->targets));
2105
2106 for (unsigned i = 0; i < num_targets; i++) {
2107 if (offsets[i] != -1)
2108 so->offsets[i] = offsets[i];
2109
2110 pipe_so_target_reference(&so->targets[i], targets[i]);
2111 }
2112
2113 for (unsigned i = 0; i < so->num_targets; i++)
2114 pipe_so_target_reference(&so->targets[i], NULL);
2115
2116 so->num_targets = num_targets;
2117 }
2118
2119 struct pipe_context *
2120 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
2121 {
2122 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
2123 struct pipe_context *gallium = (struct pipe_context *) ctx;
2124
2125 gallium->screen = screen;
2126
2127 gallium->destroy = panfrost_destroy;
2128
2129 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
2130
2131 gallium->flush = panfrost_flush;
2132 gallium->clear = panfrost_clear;
2133 gallium->draw_vbo = panfrost_draw_vbo;
2134
2135 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
2136 gallium->set_constant_buffer = panfrost_set_constant_buffer;
2137 gallium->set_shader_buffers = panfrost_set_shader_buffers;
2138
2139 gallium->set_stencil_ref = panfrost_set_stencil_ref;
2140
2141 gallium->create_sampler_view = panfrost_create_sampler_view;
2142 gallium->set_sampler_views = panfrost_set_sampler_views;
2143 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
2144
2145 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
2146 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
2147 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
2148
2149 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
2150 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
2151 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
2152
2153 gallium->create_fs_state = panfrost_create_fs_state;
2154 gallium->delete_fs_state = panfrost_delete_shader_state;
2155 gallium->bind_fs_state = panfrost_bind_fs_state;
2156
2157 gallium->create_vs_state = panfrost_create_vs_state;
2158 gallium->delete_vs_state = panfrost_delete_shader_state;
2159 gallium->bind_vs_state = panfrost_bind_vs_state;
2160
2161 gallium->create_sampler_state = panfrost_create_sampler_state;
2162 gallium->delete_sampler_state = panfrost_generic_cso_delete;
2163 gallium->bind_sampler_states = panfrost_bind_sampler_states;
2164
2165 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
2166 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
2167 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
2168
2169 gallium->set_sample_mask = panfrost_set_sample_mask;
2170
2171 gallium->set_clip_state = panfrost_set_clip_state;
2172 gallium->set_viewport_states = panfrost_set_viewport_states;
2173 gallium->set_scissor_states = panfrost_set_scissor_states;
2174 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
2175 gallium->set_active_query_state = panfrost_set_active_query_state;
2176
2177 gallium->create_query = panfrost_create_query;
2178 gallium->destroy_query = panfrost_destroy_query;
2179 gallium->begin_query = panfrost_begin_query;
2180 gallium->end_query = panfrost_end_query;
2181 gallium->get_query_result = panfrost_get_query_result;
2182
2183 gallium->create_stream_output_target = panfrost_create_stream_output_target;
2184 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
2185 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
2186
2187 panfrost_resource_context_init(gallium);
2188 panfrost_blend_context_init(gallium);
2189 panfrost_compute_context_init(gallium);
2190
2191 /* XXX: leaks */
2192 gallium->stream_uploader = u_upload_create_default(gallium);
2193 gallium->const_uploader = gallium->stream_uploader;
2194 assert(gallium->stream_uploader);
2195
2196 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2197 ctx->draw_modes = (1 << (PIPE_PRIM_POLYGON + 1)) - 1;
2198
2199 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
2200
2201 ctx->blitter = util_blitter_create(gallium);
2202 ctx->blitter_wallpaper = util_blitter_create(gallium);
2203
2204 assert(ctx->blitter);
2205 assert(ctx->blitter_wallpaper);
2206
2207 /* Prepare for render! */
2208
2209 panfrost_batch_init(ctx);
2210 panfrost_emit_vertex_payload(ctx);
2211 panfrost_invalidate_frame(ctx);
2212 panfrost_default_shader_backend(ctx);
2213
2214 return gallium;
2215 }