2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
56 #include "pandecode/decode.h"
58 struct midgard_tiler_descriptor
59 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
61 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
62 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
63 struct midgard_tiler_descriptor t
= {0};
64 unsigned height
= batch
->key
.height
;
65 unsigned width
= batch
->key
.width
;
68 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
70 /* Compute the polygon header size and use that to offset the body */
72 unsigned header_size
= panfrost_tiler_header_size(
73 width
, height
, t
.hierarchy_mask
, hierarchy
);
75 t
.polygon_list_size
= panfrost_tiler_full_size(
76 width
, height
, t
.hierarchy_mask
, hierarchy
);
81 struct panfrost_bo
*tiler_heap
;
83 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
84 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
89 /* Allow the entire tiler heap */
90 t
.heap_start
= tiler_heap
->gpu
;
91 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
93 struct panfrost_bo
*tiler_dummy
;
95 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
96 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
98 /* The tiler is disabled, so don't allow the tiler heap */
99 t
.heap_start
= tiler_dummy
->gpu
;
100 t
.heap_end
= t
.heap_start
;
102 /* Use a dummy polygon list */
103 t
.polygon_list
= tiler_dummy
->gpu
;
105 /* Disable the tiler */
107 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
109 t
.hierarchy_mask
= MALI_TILER_USER
;
110 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
112 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
113 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
114 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
118 t
.polygon_list_body
=
119 t
.polygon_list
+ header_size
;
126 struct pipe_context
*pipe
,
128 const union pipe_color_union
*color
,
129 double depth
, unsigned stencil
)
131 struct panfrost_context
*ctx
= pan_context(pipe
);
133 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
134 * the existing batch targeting this FBO has draws. We could probably
135 * avoid that by replacing plain clears by quad-draws with a specific
136 * color/depth/stencil value, thus avoiding the generation of extra
139 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
141 panfrost_batch_add_fbo_bos(batch
);
142 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
145 /* Reset per-frame context, called on context initialisation as well as after
146 * flushing a frame */
149 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
151 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
152 ctx
->payloads
[i
].postfix
.shared_memory
= 0;
154 /* TODO: When does this need to be handled? */
155 ctx
->active_queries
= true;
158 /* In practice, every field of these payloads should be configurable
159 * arbitrarily, which means these functions are basically catch-all's for
160 * as-of-yet unwavering unknowns */
163 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
165 /* 0x2 bit clear on 32-bit T6XX */
167 struct midgard_payload_vertex_tiler payload
= {
168 .gl_enables
= 0x4 | 0x2,
171 /* Vertex and compute are closely coupled, so share a payload */
173 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
174 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
178 translate_tex_wrap(enum pipe_tex_wrap w
)
181 case PIPE_TEX_WRAP_REPEAT
:
182 return MALI_WRAP_REPEAT
;
184 case PIPE_TEX_WRAP_CLAMP
:
185 return MALI_WRAP_CLAMP
;
187 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
188 return MALI_WRAP_CLAMP_TO_EDGE
;
190 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
191 return MALI_WRAP_CLAMP_TO_BORDER
;
193 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
194 return MALI_WRAP_MIRRORED_REPEAT
;
196 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
197 return MALI_WRAP_MIRRORED_CLAMP
;
199 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
200 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
202 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
203 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
206 unreachable("Invalid wrap");
211 panfrost_translate_compare_func(enum pipe_compare_func in
)
214 case PIPE_FUNC_NEVER
:
215 return MALI_FUNC_NEVER
;
218 return MALI_FUNC_LESS
;
220 case PIPE_FUNC_EQUAL
:
221 return MALI_FUNC_EQUAL
;
223 case PIPE_FUNC_LEQUAL
:
224 return MALI_FUNC_LEQUAL
;
226 case PIPE_FUNC_GREATER
:
227 return MALI_FUNC_GREATER
;
229 case PIPE_FUNC_NOTEQUAL
:
230 return MALI_FUNC_NOTEQUAL
;
232 case PIPE_FUNC_GEQUAL
:
233 return MALI_FUNC_GEQUAL
;
235 case PIPE_FUNC_ALWAYS
:
236 return MALI_FUNC_ALWAYS
;
239 unreachable("Invalid func");
244 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
247 case PIPE_STENCIL_OP_KEEP
:
248 return MALI_STENCIL_KEEP
;
250 case PIPE_STENCIL_OP_ZERO
:
251 return MALI_STENCIL_ZERO
;
253 case PIPE_STENCIL_OP_REPLACE
:
254 return MALI_STENCIL_REPLACE
;
256 case PIPE_STENCIL_OP_INCR
:
257 return MALI_STENCIL_INCR
;
259 case PIPE_STENCIL_OP_DECR
:
260 return MALI_STENCIL_DECR
;
262 case PIPE_STENCIL_OP_INCR_WRAP
:
263 return MALI_STENCIL_INCR_WRAP
;
265 case PIPE_STENCIL_OP_DECR_WRAP
:
266 return MALI_STENCIL_DECR_WRAP
;
268 case PIPE_STENCIL_OP_INVERT
:
269 return MALI_STENCIL_INVERT
;
272 unreachable("Invalid stencil op");
277 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
279 out
->ref
= 0; /* Gallium gets it from elsewhere */
281 out
->mask
= in
->valuemask
;
282 out
->func
= panfrost_translate_compare_func(in
->func
);
283 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
284 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
285 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
289 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
291 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
292 struct mali_shader_meta shader
= {
293 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
295 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
296 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
299 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
300 * required (independent of 32-bit/64-bit descriptors), or why it's not
301 * used on later GPU revisions. Otherwise, all shader jobs fault on
302 * these earlier chips (perhaps this is a chicken bit of some kind).
303 * More investigation is needed. */
305 if (screen
->quirks
& MIDGARD_SFBD
)
306 shader
.unknown2_4
|= 0x10;
308 struct pipe_stencil_state default_stencil
= {
310 .func
= PIPE_FUNC_ALWAYS
,
311 .fail_op
= MALI_STENCIL_KEEP
,
312 .zfail_op
= MALI_STENCIL_KEEP
,
313 .zpass_op
= MALI_STENCIL_KEEP
,
318 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
319 shader
.stencil_mask_front
= default_stencil
.writemask
;
321 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
322 shader
.stencil_mask_back
= default_stencil
.writemask
;
324 if (default_stencil
.enabled
)
325 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
327 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
331 panfrost_writes_point_size(struct panfrost_context
*ctx
)
333 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
334 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
336 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
339 /* Stage the attribute descriptors so we can adjust src_offset
340 * to let BOs align nicely */
343 panfrost_stage_attributes(struct panfrost_context
*ctx
)
345 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
346 struct panfrost_vertex_state
*so
= ctx
->vertex
;
348 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
349 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
350 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
352 /* Copy as-is for the first pass */
353 memcpy(target
, so
->hw
, sz
);
355 /* Fixup offsets for the second pass. Recall that the hardware
356 * calculates attribute addresses as:
358 * addr = base + (stride * vtx) + src_offset;
360 * However, on Mali, base must be aligned to 64-bytes, so we
363 * base' = base & ~63 = base - (base & 63)
365 * To compensate when using base' (see emit_vertex_data), we have
366 * to adjust src_offset by the masked off piece:
368 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
369 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
370 * = base + (stride * vtx) + src_offset
376 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
378 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
379 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
380 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
381 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
382 mali_ptr addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
384 /* Adjust by the masked off bits of the offset. Make sure we
385 * read src_offset from so->hw (which is not GPU visible)
386 * rather than target (which is) due to caching effects */
388 unsigned src_offset
= so
->hw
[i
].src_offset
;
389 src_offset
+= (addr
& 63);
391 /* Also, somewhat obscurely per-instance data needs to be
392 * offset in response to a delayed start in an indexed draw */
394 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
395 src_offset
-= buf
->stride
* start
;
397 target
[i
].src_offset
= src_offset
;
400 /* Let's also include vertex builtins */
402 struct mali_attr_meta builtin
= {
403 .format
= MALI_R32UI
,
404 .swizzle
= panfrost_get_default_swizzle(1)
407 /* See mali_attr_meta specification for the magic number */
409 builtin
.index
= so
->vertexid_index
;
410 memcpy(&target
[PAN_VERTEX_ID
], &builtin
, 4);
412 builtin
.index
= so
->vertexid_index
+ 1;
413 memcpy(&target
[PAN_INSTANCE_ID
], &builtin
, 4);
415 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
419 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
421 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
422 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
424 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
427 if (ctx
->sampler_count
[t
]) {
428 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
430 struct panfrost_transfer transfer
=
431 panfrost_allocate_transient(batch
, transfer_size
);
433 struct mali_sampler_descriptor
*desc
=
434 (struct mali_sampler_descriptor
*) transfer
.cpu
;
436 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
437 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
439 upload
= transfer
.gpu
;
442 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
448 struct panfrost_context
*ctx
,
449 enum pipe_shader_type st
,
450 struct panfrost_sampler_view
*view
)
455 struct pipe_sampler_view
*pview
= &view
->base
;
456 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
458 /* Add the BO to the job so it's retained until the job is done. */
459 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
461 panfrost_batch_add_bo(batch
, rsrc
->bo
,
462 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
463 panfrost_bo_access_for_stage(st
));
465 panfrost_batch_add_bo(batch
, view
->bo
,
466 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
467 panfrost_bo_access_for_stage(st
));
469 return view
->bo
->gpu
;
473 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
475 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
477 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
478 mali_ptr trampoline
= 0;
480 if (ctx
->sampler_view_count
[t
]) {
481 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
483 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
485 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
487 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
490 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
494 /* Compute number of UBOs active (more specifically, compute the highest UBO
495 * number addressable -- if there are gaps, include them in the count anyway).
496 * We always include UBO #0 in the count, since we *need* uniforms enabled for
500 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
502 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
503 return 32 - __builtin_clz(mask
);
506 /* Fixes up a shader state with current state */
509 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
510 enum pipe_shader_type stage
)
512 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, stage
);
517 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
518 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
520 ss
->tripipe
->midgard1
.flags_lo
= 0x220;
522 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
523 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
526 /* Go through dirty flags and actualise them in the cmdstream. */
529 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
531 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
532 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
534 panfrost_batch_add_fbo_bos(batch
);
536 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
537 panfrost_vt_attach_framebuffer(ctx
, &ctx
->payloads
[i
]);
539 if (with_vertex_data
) {
540 panfrost_emit_vertex_data(batch
);
542 /* Varyings emitted for -all- geometry */
543 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
544 panfrost_emit_varying_descriptor(ctx
, total_count
);
548 if (ctx
->rasterizer
) {
549 bool msaa
= ctx
->rasterizer
->base
.multisample
;
550 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
552 /* TODO: Sample size */
553 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
554 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
557 panfrost_batch_set_requirements(batch
);
559 if (ctx
->occlusion_query
) {
560 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
561 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
564 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
565 panfrost_emit_shader_meta(batch
, PIPE_SHADER_VERTEX
,
566 &ctx
->payloads
[PIPE_SHADER_VERTEX
]);
567 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
568 panfrost_emit_shader_meta(batch
, PIPE_SHADER_COMPUTE
,
569 &ctx
->payloads
[PIPE_SHADER_COMPUTE
]);
571 if (ctx
->shader
[PIPE_SHADER_VERTEX
] && ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
572 /* Check if we need to link the gl_PointSize varying */
573 if (!panfrost_writes_point_size(ctx
)) {
574 /* If the size is constant, write it out. Otherwise,
575 * don't touch primitive_size (since we would clobber
576 * the pointer there) */
578 bool points
= ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
580 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= points
?
581 ctx
->rasterizer
->base
.point_size
:
582 ctx
->rasterizer
->base
.line_width
;
586 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
587 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
589 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
591 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
594 COPY(attribute_count
);
598 COPY(midgard1
.uniform_count
);
599 COPY(midgard1
.uniform_buffer_count
);
600 COPY(midgard1
.work_count
);
601 COPY(midgard1
.flags_lo
);
602 COPY(midgard1
.flags_hi
);
606 /* Get blending setup */
607 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
609 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
610 unsigned shader_offset
= 0;
611 struct panfrost_bo
*shader_bo
= NULL
;
613 for (unsigned c
= 0; c
< rt_count
; ++c
) {
614 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
617 /* If there is a blend shader, work registers are shared. XXX: opt */
619 for (unsigned c
= 0; c
< rt_count
; ++c
) {
620 if (blend
[c
].is_shader
)
621 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
624 /* Depending on whether it's legal to in the given shader, we
625 * try to enable early-z testing (or forward-pixel kill?) */
627 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_EARLY_Z
,
628 !variant
->can_discard
&& !variant
->writes_depth
);
630 /* Add the writes Z/S flags if needed. */
631 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
,
632 MALI_WRITES_Z
, variant
->writes_depth
);
633 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_hi
,
634 MALI_WRITES_S
, variant
->writes_stencil
);
636 /* Any time texturing is used, derivatives are implicitly
637 * calculated, so we need to enable helper invocations */
639 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
641 /* Assign the stencil refs late */
643 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
644 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
645 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
647 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
648 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
650 /* CAN_DISCARD should be set if the fragment shader possibly
651 * contains a 'discard' instruction. It is likely this is
652 * related to optimizations related to forward-pixel kill, as
653 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
654 * thing?" by Peter Harris
657 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
658 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, 0x400, variant
->can_discard
);
660 /* Even on MFBD, the shader descriptor gets blend shaders. It's
661 * *also* copied to the blend_meta appended (by convention),
662 * but this is the field actually read by the hardware. (Or
663 * maybe both are read...?). Specify the last RTi with a blend
666 ctx
->fragment_shader_core
.blend
.shader
= 0;
668 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
669 if (blend
[rt
].is_shader
) {
670 ctx
->fragment_shader_core
.blend
.shader
=
671 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
676 if (screen
->quirks
& MIDGARD_SFBD
) {
677 /* When only a single render target platform is used, the blend
678 * information is inside the shader meta itself. We
679 * additionally need to signal CAN_DISCARD for nontrivial blend
680 * modes (so we're able to read back the destination buffer) */
682 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
684 if (!blend
[0].is_shader
) {
685 ctx
->fragment_shader_core
.blend
.equation
=
686 *blend
[0].equation
.equation
;
687 ctx
->fragment_shader_core
.blend
.constant
=
688 blend
[0].equation
.constant
;
691 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
694 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
695 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
696 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
698 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
700 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
701 /* Additional blend descriptor tacked on for jobs using MFBD */
703 struct midgard_blend_rt rts
[4];
705 for (unsigned i
= 0; i
< rt_count
; ++i
) {
706 rts
[i
].flags
= 0x200;
709 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
710 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
711 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
713 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
714 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
715 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
716 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
718 if (blend
[i
].is_shader
) {
719 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
721 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
722 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
726 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
730 /* We stage to transient, so always dirty.. */
732 panfrost_stage_attributes(ctx
);
734 panfrost_upload_sampler_descriptors(ctx
);
735 panfrost_upload_texture_descriptors(ctx
);
737 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
738 panfrost_emit_const_buf(batch
, i
, &ctx
->payloads
[i
]);
740 /* TODO: Upload the viewport somewhere more appropriate */
742 panfrost_emit_viewport(batch
, &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
745 /* Corresponds to exactly one draw, but does not submit anything */
748 panfrost_queue_draw(struct panfrost_context
*ctx
)
750 /* Handle dirty flags now */
751 panfrost_emit_for_draw(ctx
, true);
753 /* If rasterizer discard is enable, only submit the vertex */
755 bool rasterizer_discard
= ctx
->rasterizer
756 && ctx
->rasterizer
->base
.rasterizer_discard
;
759 struct midgard_payload_vertex_tiler
*vertex_payload
= &ctx
->payloads
[PIPE_SHADER_VERTEX
];
760 struct midgard_payload_vertex_tiler
*tiler_payload
= &ctx
->payloads
[PIPE_SHADER_FRAGMENT
];
762 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
763 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->tiler_dep
;
766 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
767 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, batch
->job_index
+ 2, tiler_payload
, sizeof(*tiler_payload
), true);
768 panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), true);
770 unsigned vertex
= panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), false);
772 if (!rasterizer_discard
)
773 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, vertex
, tiler_payload
, sizeof(*tiler_payload
), false);
776 panfrost_batch_adjust_stack_size(batch
);
779 /* The entire frame is in memory -- send it off to the kernel! */
783 struct pipe_context
*pipe
,
784 struct pipe_fence_handle
**fence
,
787 struct panfrost_context
*ctx
= pan_context(pipe
);
788 struct util_dynarray fences
;
790 /* We must collect the fences before the flush is done, otherwise we'll
791 * lose track of them.
794 util_dynarray_init(&fences
, NULL
);
795 hash_table_foreach(ctx
->batches
, hentry
) {
796 struct panfrost_batch
*batch
= hentry
->data
;
798 panfrost_batch_fence_reference(batch
->out_sync
);
799 util_dynarray_append(&fences
,
800 struct panfrost_batch_fence
*,
805 /* Submit all pending jobs */
806 panfrost_flush_all_batches(ctx
, false);
809 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
810 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
811 *fence
= (struct pipe_fence_handle
*)f
;
813 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
814 panfrost_batch_fence_unreference(*fence
);
816 util_dynarray_fini(&fences
);
819 if (pan_debug
& PAN_DBG_TRACE
)
820 pandecode_next_frame();
823 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
826 g2m_draw_mode(enum pipe_prim_type mode
)
831 DEFINE_CASE(LINE_LOOP
);
832 DEFINE_CASE(LINE_STRIP
);
833 DEFINE_CASE(TRIANGLES
);
834 DEFINE_CASE(TRIANGLE_STRIP
);
835 DEFINE_CASE(TRIANGLE_FAN
);
837 DEFINE_CASE(QUAD_STRIP
);
838 DEFINE_CASE(POLYGON
);
841 unreachable("Invalid draw mode");
848 panfrost_translate_index_size(unsigned size
)
852 return MALI_DRAW_INDEXED_UINT8
;
855 return MALI_DRAW_INDEXED_UINT16
;
858 return MALI_DRAW_INDEXED_UINT32
;
861 unreachable("Invalid index size");
865 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
866 * good for the duration of the draw (transient), could last longer. Also get
867 * the bounds on the index buffer for the range accessed by the draw. We do
868 * these operations together because there are natural optimizations which
869 * require them to be together. */
872 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
, unsigned *min_index
, unsigned *max_index
)
874 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
876 off_t offset
= info
->start
* info
->index_size
;
877 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
880 bool needs_indices
= true;
882 if (info
->max_index
!= ~0u) {
883 *min_index
= info
->min_index
;
884 *max_index
= info
->max_index
;
885 needs_indices
= false;
888 if (!info
->has_user_indices
) {
889 /* Only resources can be directly mapped */
890 panfrost_batch_add_bo(batch
, rsrc
->bo
,
891 PAN_BO_ACCESS_SHARED
|
893 PAN_BO_ACCESS_VERTEX_TILER
);
894 out
= rsrc
->bo
->gpu
+ offset
;
896 /* Check the cache */
897 needs_indices
= !panfrost_minmax_cache_get(rsrc
->index_cache
, info
->start
, info
->count
,
898 min_index
, max_index
);
900 /* Otherwise, we need to upload to transient memory */
901 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
902 out
= panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
907 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
909 if (!info
->has_user_indices
) {
910 panfrost_minmax_cache_add(rsrc
->index_cache
, info
->start
, info
->count
,
911 *min_index
, *max_index
);
920 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
922 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
924 /* Check if we're scissoring at all */
926 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
929 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
932 /* Count generated primitives (when there is no geom/tess shaders) for
933 * transform feedback */
936 panfrost_statistics_record(
937 struct panfrost_context
*ctx
,
938 const struct pipe_draw_info
*info
)
940 if (!ctx
->active_queries
)
943 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
944 ctx
->prims_generated
+= prims
;
946 if (!ctx
->streamout
.num_targets
)
949 ctx
->tf_prims_generated
+= prims
;
954 struct pipe_context
*pipe
,
955 const struct pipe_draw_info
*info
)
957 struct panfrost_context
*ctx
= pan_context(pipe
);
959 /* First of all, check the scissor to see if anything is drawn at all.
960 * If it's not, we drop the draw (mostly a conformance issue;
961 * well-behaved apps shouldn't hit this) */
963 if (panfrost_scissor_culls_everything(ctx
))
966 int mode
= info
->mode
;
968 /* Fallback unsupported restart index */
969 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
971 if (info
->primitive_restart
&& info
->index_size
972 && info
->restart_index
!= primitive_index
) {
973 util_draw_vbo_without_prim_restart(pipe
, info
);
977 /* Fallback for unsupported modes */
979 assert(ctx
->rasterizer
!= NULL
);
981 if (!(ctx
->draw_modes
& (1 << mode
))) {
982 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
983 mode
= PIPE_PRIM_TRIANGLE_FAN
;
985 if (info
->count
< 4) {
986 /* Degenerate case? */
990 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
991 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
996 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
997 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
999 /* Now that we have a guaranteed terminating path, find the job.
1000 * Assignment commented out to prevent unused warning */
1002 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1004 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1006 /* Take into account a negative bias */
1007 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1008 ctx
->instance_count
= info
->instance_count
;
1009 ctx
->active_prim
= info
->mode
;
1011 /* For non-indexed draws, they're the same */
1012 unsigned vertex_count
= ctx
->vertex_count
;
1014 unsigned draw_flags
= 0;
1016 /* The draw flags interpret how primitive size is interpreted */
1018 if (panfrost_writes_point_size(ctx
))
1019 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1021 if (info
->primitive_restart
)
1022 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1024 /* These doesn't make much sense */
1026 draw_flags
|= 0x3000;
1028 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1029 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1031 panfrost_statistics_record(ctx
, info
);
1033 if (info
->index_size
) {
1034 unsigned min_index
= 0, max_index
= 0;
1035 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
=
1036 panfrost_get_index_buffer_bounded(ctx
, info
, &min_index
, &max_index
);
1038 /* Use the corresponding values */
1039 vertex_count
= max_index
- min_index
+ 1;
1040 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1041 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1043 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1044 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1046 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1048 /* Index count == vertex count, if no indexing is applied, as
1049 * if it is internally indexed in the expected order */
1051 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1052 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1054 /* Reverse index state */
1055 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
1058 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1059 * vertex_count, 1) */
1061 panfrost_pack_work_groups_fused(
1062 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1063 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1064 1, vertex_count
, info
->instance_count
,
1067 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1069 /* Encode the padded vertex count */
1071 if (info
->instance_count
> 1) {
1072 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1074 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1075 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1077 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1078 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1080 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1081 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1083 ctx
->padded_count
= vertex_count
;
1085 /* Reset instancing state */
1086 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1087 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1088 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1089 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1092 /* Fire off the draw itself */
1093 panfrost_queue_draw(ctx
);
1095 /* Increment transform feedback offsets */
1097 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1098 unsigned output_count
= u_stream_outputs_for_vertices(
1099 ctx
->active_prim
, ctx
->vertex_count
);
1101 ctx
->streamout
.offsets
[i
] += output_count
;
1108 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1114 panfrost_create_rasterizer_state(
1115 struct pipe_context
*pctx
,
1116 const struct pipe_rasterizer_state
*cso
)
1118 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1122 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1123 so
->tiler_gl_enables
= 0x7;
1126 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1128 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1129 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1131 if (cso
->cull_face
& PIPE_FACE_BACK
)
1132 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1138 panfrost_bind_rasterizer_state(
1139 struct pipe_context
*pctx
,
1142 struct panfrost_context
*ctx
= pan_context(pctx
);
1144 ctx
->rasterizer
= hwcso
;
1149 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1150 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1152 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1153 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1155 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1157 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1158 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1160 /* Point sprites are emulated */
1162 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
1164 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1165 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1169 panfrost_create_vertex_elements_state(
1170 struct pipe_context
*pctx
,
1171 unsigned num_elements
,
1172 const struct pipe_vertex_element
*elements
)
1174 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1176 so
->num_elements
= num_elements
;
1177 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1179 for (int i
= 0; i
< num_elements
; ++i
) {
1180 so
->hw
[i
].index
= i
;
1182 enum pipe_format fmt
= elements
[i
].src_format
;
1183 const struct util_format_description
*desc
= util_format_description(fmt
);
1184 so
->hw
[i
].unknown1
= 0x2;
1185 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1187 so
->hw
[i
].format
= panfrost_find_format(desc
);
1189 /* The field itself should probably be shifted over */
1190 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1197 panfrost_bind_vertex_elements_state(
1198 struct pipe_context
*pctx
,
1201 struct panfrost_context
*ctx
= pan_context(pctx
);
1202 ctx
->vertex
= hwcso
;
1206 panfrost_create_shader_state(
1207 struct pipe_context
*pctx
,
1208 const struct pipe_shader_state
*cso
,
1209 enum pipe_shader_type stage
)
1211 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1214 /* Token deep copy to prevent memory corruption */
1216 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1217 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1219 /* Precompile for shader-db if we need to */
1220 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1221 struct panfrost_context
*ctx
= pan_context(pctx
);
1223 struct mali_shader_meta meta
;
1224 struct panfrost_shader_state state
;
1225 uint64_t outputs_written
;
1227 panfrost_shader_compile(ctx
, &meta
,
1230 tgsi_processor_to_shader_stage(stage
), &state
,
1238 panfrost_delete_shader_state(
1239 struct pipe_context
*pctx
,
1242 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1244 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1245 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1248 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1249 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1250 panfrost_bo_unreference(shader_state
->bo
);
1251 shader_state
->bo
= NULL
;
1253 free(cso
->variants
);
1259 panfrost_create_sampler_state(
1260 struct pipe_context
*pctx
,
1261 const struct pipe_sampler_state
*cso
)
1263 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1266 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1268 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1269 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1270 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1272 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1273 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1274 unsigned mip_filter
= mip_linear
?
1275 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1276 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1278 struct mali_sampler_descriptor sampler_descriptor
= {
1279 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1280 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1281 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1282 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1283 .compare_func
= panfrost_flip_compare_func(
1284 panfrost_translate_compare_func(
1285 cso
->compare_func
)),
1287 cso
->border_color
.f
[0],
1288 cso
->border_color
.f
[1],
1289 cso
->border_color
.f
[2],
1290 cso
->border_color
.f
[3]
1292 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1293 .max_lod
= FIXED_16(cso
->max_lod
, false),
1294 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1295 .seamless_cube_map
= cso
->seamless_cube_map
,
1298 /* If necessary, we disable mipmapping in the sampler descriptor by
1299 * clamping the LOD as tight as possible (from 0 to epsilon,
1300 * essentially -- remember these are fixed point numbers, so
1303 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
1304 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1306 /* Enforce that there is something in the middle by adding epsilon*/
1308 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1309 sampler_descriptor
.max_lod
++;
1312 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1315 so
->hw
= sampler_descriptor
;
1321 panfrost_bind_sampler_states(
1322 struct pipe_context
*pctx
,
1323 enum pipe_shader_type shader
,
1324 unsigned start_slot
, unsigned num_sampler
,
1327 assert(start_slot
== 0);
1329 struct panfrost_context
*ctx
= pan_context(pctx
);
1331 /* XXX: Should upload, not just copy? */
1332 ctx
->sampler_count
[shader
] = num_sampler
;
1333 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1337 panfrost_variant_matches(
1338 struct panfrost_context
*ctx
,
1339 struct panfrost_shader_state
*variant
,
1340 enum pipe_shader_type type
)
1342 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1343 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1345 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1347 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1348 /* Make sure enable state is at least the same */
1349 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1353 /* Check that the contents of the test are the same */
1354 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1355 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1357 if (!(same_func
&& same_ref
)) {
1362 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1363 variant
->point_sprite_mask
)) {
1364 /* Ensure the same varyings are turned to point sprites */
1365 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1368 /* Ensure the orientation is correct */
1370 rasterizer
->sprite_coord_mode
==
1371 PIPE_SPRITE_COORD_UPPER_LEFT
;
1373 if (variant
->point_sprite_upper_left
!= upper_left
)
1377 /* Otherwise, we're good to go */
1382 * Fix an uncompiled shader's stream output info, and produce a bitmask
1383 * of which VARYING_SLOT_* are captured for stream output.
1385 * Core Gallium stores output->register_index as a "slot" number, where
1386 * slots are assigned consecutively to all outputs in info->outputs_written.
1387 * This naive packing of outputs doesn't work for us - we too have slots,
1388 * but the layout is defined by the VUE map, which we won't have until we
1389 * compile a specific shader variant. So, we remap these and simply store
1390 * VARYING_SLOT_* in our copy's output->register_index fields.
1392 * We then produce a bitmask of outputs which are used for SO.
1394 * Implementation from iris.
1398 update_so_info(struct pipe_stream_output_info
*so_info
,
1399 uint64_t outputs_written
)
1401 uint64_t so_outputs
= 0;
1402 uint8_t reverse_map
[64] = {0};
1405 while (outputs_written
)
1406 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1408 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1409 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1411 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1412 output
->register_index
= reverse_map
[output
->register_index
];
1414 so_outputs
|= 1ull << output
->register_index
;
1421 panfrost_bind_shader_state(
1422 struct pipe_context
*pctx
,
1424 enum pipe_shader_type type
)
1426 struct panfrost_context
*ctx
= pan_context(pctx
);
1427 ctx
->shader
[type
] = hwcso
;
1431 /* Match the appropriate variant */
1433 signed variant
= -1;
1434 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1436 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1437 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1443 if (variant
== -1) {
1444 /* No variant matched, so create a new one */
1445 variant
= variants
->variant_count
++;
1447 if (variants
->variant_count
> variants
->variant_space
) {
1448 unsigned old_space
= variants
->variant_space
;
1450 variants
->variant_space
*= 2;
1451 if (variants
->variant_space
== 0)
1452 variants
->variant_space
= 1;
1454 /* Arbitrary limit to stop runaway programs from
1455 * creating an unbounded number of shader variants. */
1456 assert(variants
->variant_space
< 1024);
1458 unsigned msize
= sizeof(struct panfrost_shader_state
);
1459 variants
->variants
= realloc(variants
->variants
,
1460 variants
->variant_space
* msize
);
1462 memset(&variants
->variants
[old_space
], 0,
1463 (variants
->variant_space
- old_space
) * msize
);
1466 struct panfrost_shader_state
*v
=
1467 &variants
->variants
[variant
];
1469 if (type
== PIPE_SHADER_FRAGMENT
) {
1470 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1472 if (ctx
->rasterizer
) {
1473 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1474 v
->point_sprite_upper_left
=
1475 ctx
->rasterizer
->base
.sprite_coord_mode
==
1476 PIPE_SPRITE_COORD_UPPER_LEFT
;
1480 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1484 /* Select this variant */
1485 variants
->active_variant
= variant
;
1487 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1488 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1490 /* We finally have a variant, so compile it */
1492 if (!shader_state
->compiled
) {
1493 uint64_t outputs_written
= 0;
1495 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1496 variants
->base
.type
,
1497 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1498 variants
->base
.ir
.nir
:
1499 variants
->base
.tokens
,
1500 tgsi_processor_to_shader_stage(type
), shader_state
,
1503 shader_state
->compiled
= true;
1505 /* Fixup the stream out information, since what Gallium returns
1506 * normally is mildly insane */
1508 shader_state
->stream_output
= variants
->base
.stream_output
;
1509 shader_state
->so_mask
=
1510 update_so_info(&shader_state
->stream_output
, outputs_written
);
1515 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1517 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1521 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1523 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1527 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1529 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1533 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1535 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1539 panfrost_set_vertex_buffers(
1540 struct pipe_context
*pctx
,
1541 unsigned start_slot
,
1542 unsigned num_buffers
,
1543 const struct pipe_vertex_buffer
*buffers
)
1545 struct panfrost_context
*ctx
= pan_context(pctx
);
1547 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1551 panfrost_set_constant_buffer(
1552 struct pipe_context
*pctx
,
1553 enum pipe_shader_type shader
, uint index
,
1554 const struct pipe_constant_buffer
*buf
)
1556 struct panfrost_context
*ctx
= pan_context(pctx
);
1557 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1559 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
1561 unsigned mask
= (1 << index
);
1563 if (unlikely(!buf
)) {
1564 pbuf
->enabled_mask
&= ~mask
;
1565 pbuf
->dirty_mask
&= ~mask
;
1569 pbuf
->enabled_mask
|= mask
;
1570 pbuf
->dirty_mask
|= mask
;
1574 panfrost_set_stencil_ref(
1575 struct pipe_context
*pctx
,
1576 const struct pipe_stencil_ref
*ref
)
1578 struct panfrost_context
*ctx
= pan_context(pctx
);
1579 ctx
->stencil_ref
= *ref
;
1582 static enum mali_texture_type
1583 panfrost_translate_texture_type(enum pipe_texture_target t
) {
1587 case PIPE_TEXTURE_1D
:
1588 case PIPE_TEXTURE_1D_ARRAY
:
1591 case PIPE_TEXTURE_2D
:
1592 case PIPE_TEXTURE_2D_ARRAY
:
1593 case PIPE_TEXTURE_RECT
:
1596 case PIPE_TEXTURE_3D
:
1599 case PIPE_TEXTURE_CUBE
:
1600 case PIPE_TEXTURE_CUBE_ARRAY
:
1601 return MALI_TEX_CUBE
;
1604 unreachable("Unknown target");
1608 static struct pipe_sampler_view
*
1609 panfrost_create_sampler_view(
1610 struct pipe_context
*pctx
,
1611 struct pipe_resource
*texture
,
1612 const struct pipe_sampler_view
*template)
1614 struct panfrost_screen
*screen
= pan_screen(pctx
->screen
);
1615 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
1617 pipe_reference(NULL
, &texture
->reference
);
1619 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1622 so
->base
= *template;
1623 so
->base
.texture
= texture
;
1624 so
->base
.reference
.count
= 1;
1625 so
->base
.context
= pctx
;
1627 unsigned char user_swizzle
[4] = {
1628 template->swizzle_r
,
1629 template->swizzle_g
,
1630 template->swizzle_b
,
1634 /* In the hardware, array_size refers specifically to array textures,
1635 * whereas in Gallium, it also covers cubemaps */
1637 unsigned array_size
= texture
->array_size
;
1639 if (template->target
== PIPE_TEXTURE_CUBE
) {
1640 /* TODO: Cubemap arrays */
1641 assert(array_size
== 6);
1645 enum mali_texture_type type
=
1646 panfrost_translate_texture_type(template->target
);
1648 unsigned size
= panfrost_estimate_texture_size(
1649 template->u
.tex
.first_level
,
1650 template->u
.tex
.last_level
,
1651 template->u
.tex
.first_layer
,
1652 template->u
.tex
.last_layer
,
1653 type
, prsrc
->layout
);
1655 so
->bo
= panfrost_bo_create(screen
, size
, 0);
1657 panfrost_new_texture(
1659 texture
->width0
, texture
->height0
,
1660 texture
->depth0
, array_size
,
1662 type
, prsrc
->layout
,
1663 template->u
.tex
.first_level
,
1664 template->u
.tex
.last_level
,
1665 template->u
.tex
.first_layer
,
1666 template->u
.tex
.last_layer
,
1667 prsrc
->cubemap_stride
,
1668 panfrost_translate_swizzle_4(user_swizzle
),
1672 return (struct pipe_sampler_view
*) so
;
1676 panfrost_set_sampler_views(
1677 struct pipe_context
*pctx
,
1678 enum pipe_shader_type shader
,
1679 unsigned start_slot
, unsigned num_views
,
1680 struct pipe_sampler_view
**views
)
1682 struct panfrost_context
*ctx
= pan_context(pctx
);
1683 unsigned new_nr
= 0;
1686 assert(start_slot
== 0);
1688 for (i
= 0; i
< num_views
; ++i
) {
1691 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1695 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1696 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1699 ctx
->sampler_view_count
[shader
] = new_nr
;
1703 panfrost_sampler_view_destroy(
1704 struct pipe_context
*pctx
,
1705 struct pipe_sampler_view
*pview
)
1707 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1709 pipe_resource_reference(&pview
->texture
, NULL
);
1710 panfrost_bo_unreference(view
->bo
);
1715 panfrost_set_shader_buffers(
1716 struct pipe_context
*pctx
,
1717 enum pipe_shader_type shader
,
1718 unsigned start
, unsigned count
,
1719 const struct pipe_shader_buffer
*buffers
,
1720 unsigned writable_bitmask
)
1722 struct panfrost_context
*ctx
= pan_context(pctx
);
1724 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1725 buffers
, start
, count
);
1728 /* Hints that a framebuffer should use AFBC where possible */
1732 struct panfrost_screen
*screen
,
1733 const struct pipe_framebuffer_state
*fb
)
1735 /* AFBC implemenation incomplete; hide it */
1736 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
1738 /* Hint AFBC to the resources bound to each color buffer */
1740 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
1741 struct pipe_surface
*surf
= fb
->cbufs
[i
];
1742 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1743 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1746 /* Also hint it to the depth buffer */
1749 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
1750 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1755 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1756 const struct pipe_framebuffer_state
*fb
)
1758 struct panfrost_context
*ctx
= pan_context(pctx
);
1760 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
1761 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1763 panfrost_invalidate_frame(ctx
);
1767 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1768 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
1770 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
1774 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1777 struct panfrost_context
*ctx
= pan_context(pipe
);
1778 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
1779 ctx
->depth_stencil
= depth_stencil
;
1784 /* Alpha does not exist in the hardware (it's not in ES3), so it's
1785 * emulated in the fragment shader */
1787 if (depth_stencil
->alpha
.enabled
) {
1788 /* We need to trigger a new shader (maybe) */
1789 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1793 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
1795 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
1796 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
1798 /* If back-stencil is not enabled, use the front values */
1799 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1800 unsigned back_index
= back_enab
? 1 : 0;
1802 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
1803 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
1805 /* Depth state (TODO: Refactor) */
1806 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
1807 depth_stencil
->depth
.writemask
);
1809 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
1811 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
1812 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
1814 /* Bounds test not implemented */
1815 assert(!depth_stencil
->depth
.bounds_test
);
1819 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1825 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1826 unsigned sample_mask
)
1831 panfrost_set_clip_state(struct pipe_context
*pipe
,
1832 const struct pipe_clip_state
*clip
)
1834 //struct panfrost_context *panfrost = pan_context(pipe);
1838 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1839 unsigned start_slot
,
1840 unsigned num_viewports
,
1841 const struct pipe_viewport_state
*viewports
)
1843 struct panfrost_context
*ctx
= pan_context(pipe
);
1845 assert(start_slot
== 0);
1846 assert(num_viewports
== 1);
1848 ctx
->pipe_viewport
= *viewports
;
1852 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1853 unsigned start_slot
,
1854 unsigned num_scissors
,
1855 const struct pipe_scissor_state
*scissors
)
1857 struct panfrost_context
*ctx
= pan_context(pipe
);
1859 assert(start_slot
== 0);
1860 assert(num_scissors
== 1);
1862 ctx
->scissor
= *scissors
;
1866 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1867 const struct pipe_poly_stipple
*stipple
)
1869 //struct panfrost_context *panfrost = pan_context(pipe);
1873 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1876 struct panfrost_context
*ctx
= pan_context(pipe
);
1877 ctx
->active_queries
= enable
;
1881 panfrost_destroy(struct pipe_context
*pipe
)
1883 struct panfrost_context
*panfrost
= pan_context(pipe
);
1885 if (panfrost
->blitter
)
1886 util_blitter_destroy(panfrost
->blitter
);
1888 if (panfrost
->blitter_wallpaper
)
1889 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1891 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1892 u_upload_destroy(pipe
->stream_uploader
);
1897 static struct pipe_query
*
1898 panfrost_create_query(struct pipe_context
*pipe
,
1902 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1907 return (struct pipe_query
*) q
;
1911 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1913 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1916 panfrost_bo_unreference(query
->bo
);
1924 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1926 struct panfrost_context
*ctx
= pan_context(pipe
);
1927 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1929 switch (query
->type
) {
1930 case PIPE_QUERY_OCCLUSION_COUNTER
:
1931 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1932 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1933 /* Allocate a bo for the query results to be stored */
1935 query
->bo
= panfrost_bo_create(
1936 pan_screen(ctx
->base
.screen
),
1937 sizeof(unsigned), 0);
1940 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1941 *result
= 0; /* Default to 0 if nothing at all drawn. */
1942 ctx
->occlusion_query
= query
;
1945 /* Geometry statistics are computed in the driver. XXX: geom/tess
1948 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1949 query
->start
= ctx
->prims_generated
;
1951 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1952 query
->start
= ctx
->tf_prims_generated
;
1956 DBG("Skipping query %u\n", query
->type
);
1964 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1966 struct panfrost_context
*ctx
= pan_context(pipe
);
1967 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1969 switch (query
->type
) {
1970 case PIPE_QUERY_OCCLUSION_COUNTER
:
1971 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1972 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1973 ctx
->occlusion_query
= NULL
;
1975 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1976 query
->end
= ctx
->prims_generated
;
1978 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1979 query
->end
= ctx
->tf_prims_generated
;
1987 panfrost_get_query_result(struct pipe_context
*pipe
,
1988 struct pipe_query
*q
,
1990 union pipe_query_result
*vresult
)
1992 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1993 struct panfrost_context
*ctx
= pan_context(pipe
);
1996 switch (query
->type
) {
1997 case PIPE_QUERY_OCCLUSION_COUNTER
:
1998 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1999 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2001 panfrost_flush_all_batches(ctx
, true);
2003 /* Read back the query results */
2004 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2005 unsigned passed
= *result
;
2007 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2008 vresult
->u64
= passed
;
2010 vresult
->b
= !!passed
;
2015 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2016 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2017 panfrost_flush_all_batches(ctx
, true);
2018 vresult
->u64
= query
->end
- query
->start
;
2022 DBG("Skipped query get %u\n", query
->type
);
2029 static struct pipe_stream_output_target
*
2030 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2031 struct pipe_resource
*prsc
,
2032 unsigned buffer_offset
,
2033 unsigned buffer_size
)
2035 struct pipe_stream_output_target
*target
;
2037 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2042 pipe_reference_init(&target
->reference
, 1);
2043 pipe_resource_reference(&target
->buffer
, prsc
);
2045 target
->context
= pctx
;
2046 target
->buffer_offset
= buffer_offset
;
2047 target
->buffer_size
= buffer_size
;
2053 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2054 struct pipe_stream_output_target
*target
)
2056 pipe_resource_reference(&target
->buffer
, NULL
);
2057 ralloc_free(target
);
2061 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2062 unsigned num_targets
,
2063 struct pipe_stream_output_target
**targets
,
2064 const unsigned *offsets
)
2066 struct panfrost_context
*ctx
= pan_context(pctx
);
2067 struct panfrost_streamout
*so
= &ctx
->streamout
;
2069 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2071 for (unsigned i
= 0; i
< num_targets
; i
++) {
2072 if (offsets
[i
] != -1)
2073 so
->offsets
[i
] = offsets
[i
];
2075 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2078 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2079 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2081 so
->num_targets
= num_targets
;
2084 struct pipe_context
*
2085 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2087 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2088 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2090 gallium
->screen
= screen
;
2092 gallium
->destroy
= panfrost_destroy
;
2094 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2096 gallium
->flush
= panfrost_flush
;
2097 gallium
->clear
= panfrost_clear
;
2098 gallium
->draw_vbo
= panfrost_draw_vbo
;
2100 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2101 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2102 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2104 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2106 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2107 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2108 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2110 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2111 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2112 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2114 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2115 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2116 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2118 gallium
->create_fs_state
= panfrost_create_fs_state
;
2119 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2120 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2122 gallium
->create_vs_state
= panfrost_create_vs_state
;
2123 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2124 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2126 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2127 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2128 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2130 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2131 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2132 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2134 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2136 gallium
->set_clip_state
= panfrost_set_clip_state
;
2137 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2138 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2139 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2140 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2142 gallium
->create_query
= panfrost_create_query
;
2143 gallium
->destroy_query
= panfrost_destroy_query
;
2144 gallium
->begin_query
= panfrost_begin_query
;
2145 gallium
->end_query
= panfrost_end_query
;
2146 gallium
->get_query_result
= panfrost_get_query_result
;
2148 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2149 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2150 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2152 panfrost_resource_context_init(gallium
);
2153 panfrost_blend_context_init(gallium
);
2154 panfrost_compute_context_init(gallium
);
2157 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2158 gallium
->const_uploader
= gallium
->stream_uploader
;
2159 assert(gallium
->stream_uploader
);
2161 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2162 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2164 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2166 ctx
->blitter
= util_blitter_create(gallium
);
2167 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2169 assert(ctx
->blitter
);
2170 assert(ctx
->blitter_wallpaper
);
2172 /* Prepare for render! */
2174 panfrost_batch_init(ctx
);
2175 panfrost_emit_vertex_payload(ctx
);
2176 panfrost_invalidate_frame(ctx
);
2177 panfrost_default_shader_backend(ctx
);