2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "panfrost-quirks.h"
34 #include "util/macros.h"
35 #include "util/format/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/format/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
54 #include "pandecode/decode.h"
56 struct midgard_tiler_descriptor
57 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
59 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
60 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
61 struct midgard_tiler_descriptor t
= {0};
62 unsigned height
= batch
->key
.height
;
63 unsigned width
= batch
->key
.width
;
66 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
68 /* Compute the polygon header size and use that to offset the body */
70 unsigned header_size
= panfrost_tiler_header_size(
71 width
, height
, t
.hierarchy_mask
, hierarchy
);
73 t
.polygon_list_size
= panfrost_tiler_full_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
79 struct panfrost_bo
*tiler_heap
;
81 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
82 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
87 /* Allow the entire tiler heap */
88 t
.heap_start
= tiler_heap
->gpu
;
89 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
91 struct panfrost_bo
*tiler_dummy
;
93 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
94 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
96 /* The tiler is disabled, so don't allow the tiler heap */
97 t
.heap_start
= tiler_dummy
->gpu
;
98 t
.heap_end
= t
.heap_start
;
100 /* Use a dummy polygon list */
101 t
.polygon_list
= tiler_dummy
->gpu
;
103 /* Disable the tiler */
105 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
107 t
.hierarchy_mask
= MALI_TILER_USER
;
108 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
110 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
111 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
112 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
116 t
.polygon_list_body
=
117 t
.polygon_list
+ header_size
;
124 struct pipe_context
*pipe
,
126 const union pipe_color_union
*color
,
127 double depth
, unsigned stencil
)
129 struct panfrost_context
*ctx
= pan_context(pipe
);
131 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
132 * the existing batch targeting this FBO has draws. We could probably
133 * avoid that by replacing plain clears by quad-draws with a specific
134 * color/depth/stencil value, thus avoiding the generation of extra
137 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
139 panfrost_batch_add_fbo_bos(batch
);
140 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
143 /* TODO: Bifrost requires just a mali_shared_memory, without the rest of the
147 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
149 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
150 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
152 /* If we haven't, reserve space for the framebuffer */
154 if (!batch
->framebuffer
.gpu
) {
155 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
156 sizeof(struct mali_single_framebuffer
) :
157 sizeof(struct mali_framebuffer
);
159 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
161 /* Tag the pointer */
162 if (!(screen
->quirks
& MIDGARD_SFBD
))
163 batch
->framebuffer
.gpu
|= MALI_MFBD
;
166 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
167 ctx
->payloads
[i
].postfix
.shared_memory
= batch
->framebuffer
.gpu
;
170 /* Reset per-frame context, called on context initialisation as well as after
171 * flushing a frame */
174 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
176 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
177 ctx
->payloads
[i
].postfix
.shared_memory
= 0;
179 /* TODO: When does this need to be handled? */
180 ctx
->active_queries
= true;
183 /* In practice, every field of these payloads should be configurable
184 * arbitrarily, which means these functions are basically catch-all's for
185 * as-of-yet unwavering unknowns */
188 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
190 /* 0x2 bit clear on 32-bit T6XX */
192 struct midgard_payload_vertex_tiler payload
= {
193 .gl_enables
= 0x4 | 0x2,
196 /* Vertex and compute are closely coupled, so share a payload */
198 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
199 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
203 translate_tex_wrap(enum pipe_tex_wrap w
)
206 case PIPE_TEX_WRAP_REPEAT
:
207 return MALI_WRAP_REPEAT
;
209 case PIPE_TEX_WRAP_CLAMP
:
210 return MALI_WRAP_CLAMP
;
212 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
213 return MALI_WRAP_CLAMP_TO_EDGE
;
215 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
216 return MALI_WRAP_CLAMP_TO_BORDER
;
218 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
219 return MALI_WRAP_MIRRORED_REPEAT
;
221 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
222 return MALI_WRAP_MIRRORED_CLAMP
;
224 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
225 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
227 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
228 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
231 unreachable("Invalid wrap");
236 panfrost_translate_compare_func(enum pipe_compare_func in
)
239 case PIPE_FUNC_NEVER
:
240 return MALI_FUNC_NEVER
;
243 return MALI_FUNC_LESS
;
245 case PIPE_FUNC_EQUAL
:
246 return MALI_FUNC_EQUAL
;
248 case PIPE_FUNC_LEQUAL
:
249 return MALI_FUNC_LEQUAL
;
251 case PIPE_FUNC_GREATER
:
252 return MALI_FUNC_GREATER
;
254 case PIPE_FUNC_NOTEQUAL
:
255 return MALI_FUNC_NOTEQUAL
;
257 case PIPE_FUNC_GEQUAL
:
258 return MALI_FUNC_GEQUAL
;
260 case PIPE_FUNC_ALWAYS
:
261 return MALI_FUNC_ALWAYS
;
264 unreachable("Invalid func");
269 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
272 case PIPE_STENCIL_OP_KEEP
:
273 return MALI_STENCIL_KEEP
;
275 case PIPE_STENCIL_OP_ZERO
:
276 return MALI_STENCIL_ZERO
;
278 case PIPE_STENCIL_OP_REPLACE
:
279 return MALI_STENCIL_REPLACE
;
281 case PIPE_STENCIL_OP_INCR
:
282 return MALI_STENCIL_INCR
;
284 case PIPE_STENCIL_OP_DECR
:
285 return MALI_STENCIL_DECR
;
287 case PIPE_STENCIL_OP_INCR_WRAP
:
288 return MALI_STENCIL_INCR_WRAP
;
290 case PIPE_STENCIL_OP_DECR_WRAP
:
291 return MALI_STENCIL_DECR_WRAP
;
293 case PIPE_STENCIL_OP_INVERT
:
294 return MALI_STENCIL_INVERT
;
297 unreachable("Invalid stencil op");
302 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
304 out
->ref
= 0; /* Gallium gets it from elsewhere */
306 out
->mask
= in
->valuemask
;
307 out
->func
= panfrost_translate_compare_func(in
->func
);
308 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
309 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
310 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
314 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
316 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
317 struct mali_shader_meta shader
= {
318 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
320 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
321 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
324 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
325 * required (independent of 32-bit/64-bit descriptors), or why it's not
326 * used on later GPU revisions. Otherwise, all shader jobs fault on
327 * these earlier chips (perhaps this is a chicken bit of some kind).
328 * More investigation is needed. */
330 if (screen
->quirks
& MIDGARD_SFBD
)
331 shader
.unknown2_4
|= 0x10;
333 struct pipe_stencil_state default_stencil
= {
335 .func
= PIPE_FUNC_ALWAYS
,
336 .fail_op
= MALI_STENCIL_KEEP
,
337 .zfail_op
= MALI_STENCIL_KEEP
,
338 .zpass_op
= MALI_STENCIL_KEEP
,
343 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
344 shader
.stencil_mask_front
= default_stencil
.writemask
;
346 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
347 shader
.stencil_mask_back
= default_stencil
.writemask
;
349 if (default_stencil
.enabled
)
350 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
352 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
356 panfrost_writes_point_size(struct panfrost_context
*ctx
)
358 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
359 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
361 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
364 /* Stage the attribute descriptors so we can adjust src_offset
365 * to let BOs align nicely */
368 panfrost_stage_attributes(struct panfrost_context
*ctx
)
370 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
371 struct panfrost_vertex_state
*so
= ctx
->vertex
;
373 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
374 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
375 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
377 /* Copy as-is for the first pass */
378 memcpy(target
, so
->hw
, sz
);
380 /* Fixup offsets for the second pass. Recall that the hardware
381 * calculates attribute addresses as:
383 * addr = base + (stride * vtx) + src_offset;
385 * However, on Mali, base must be aligned to 64-bytes, so we
388 * base' = base & ~63 = base - (base & 63)
390 * To compensate when using base' (see emit_vertex_data), we have
391 * to adjust src_offset by the masked off piece:
393 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
394 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
395 * = base + (stride * vtx) + src_offset
401 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
403 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
404 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
405 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
406 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
407 mali_ptr addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
409 /* Adjust by the masked off bits of the offset. Make sure we
410 * read src_offset from so->hw (which is not GPU visible)
411 * rather than target (which is) due to caching effects */
413 unsigned src_offset
= so
->hw
[i
].src_offset
;
414 src_offset
+= (addr
& 63);
416 /* Also, somewhat obscurely per-instance data needs to be
417 * offset in response to a delayed start in an indexed draw */
419 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
420 src_offset
-= buf
->stride
* start
;
422 target
[i
].src_offset
= src_offset
;
425 /* Let's also include vertex builtins */
427 struct mali_attr_meta builtin
= {
428 .format
= MALI_R32UI
,
429 .swizzle
= panfrost_get_default_swizzle(1)
432 /* See mali_attr_meta specification for the magic number */
434 builtin
.index
= so
->vertexid_index
;
435 memcpy(&target
[PAN_VERTEX_ID
], &builtin
, 4);
437 builtin
.index
= so
->vertexid_index
+ 1;
438 memcpy(&target
[PAN_INSTANCE_ID
], &builtin
, 4);
440 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
444 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
446 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
447 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
449 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
452 if (ctx
->sampler_count
[t
]) {
453 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
455 struct panfrost_transfer transfer
=
456 panfrost_allocate_transient(batch
, transfer_size
);
458 struct mali_sampler_descriptor
*desc
=
459 (struct mali_sampler_descriptor
*) transfer
.cpu
;
461 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
462 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
464 upload
= transfer
.gpu
;
467 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
473 struct panfrost_context
*ctx
,
474 enum pipe_shader_type st
,
475 struct panfrost_sampler_view
*view
)
480 struct pipe_sampler_view
*pview
= &view
->base
;
481 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
483 /* Add the BO to the job so it's retained until the job is done. */
484 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
486 panfrost_batch_add_bo(batch
, rsrc
->bo
,
487 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
488 panfrost_bo_access_for_stage(st
));
490 panfrost_batch_add_bo(batch
, view
->bo
,
491 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
492 panfrost_bo_access_for_stage(st
));
494 return view
->bo
->gpu
;
498 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
500 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
502 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
503 mali_ptr trampoline
= 0;
505 if (ctx
->sampler_view_count
[t
]) {
506 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
508 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
510 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
512 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
515 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
519 struct sysval_uniform
{
528 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
529 struct sysval_uniform
*uniform
)
531 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
533 uniform
->f
[0] = vp
->scale
[0];
534 uniform
->f
[1] = vp
->scale
[1];
535 uniform
->f
[2] = vp
->scale
[2];
538 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
539 struct sysval_uniform
*uniform
)
541 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
543 uniform
->f
[0] = vp
->translate
[0];
544 uniform
->f
[1] = vp
->translate
[1];
545 uniform
->f
[2] = vp
->translate
[2];
548 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
549 enum pipe_shader_type st
,
550 unsigned int sysvalid
,
551 struct sysval_uniform
*uniform
)
553 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
554 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
555 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
556 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
559 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
562 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
563 tex
->u
.tex
.first_level
);
566 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
567 tex
->u
.tex
.first_level
);
570 uniform
->i
[dim
] = tex
->texture
->array_size
;
573 static void panfrost_upload_ssbo_sysval(
574 struct panfrost_context
*ctx
,
575 enum pipe_shader_type st
,
577 struct sysval_uniform
*uniform
)
579 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
580 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
582 /* Compute address */
583 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
584 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
586 panfrost_batch_add_bo(batch
, bo
,
587 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
588 panfrost_bo_access_for_stage(st
));
590 /* Upload address and size as sysval */
591 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
592 uniform
->u
[2] = sb
.buffer_size
;
596 panfrost_upload_sampler_sysval(
597 struct panfrost_context
*ctx
,
598 enum pipe_shader_type st
,
599 unsigned sampler_index
,
600 struct sysval_uniform
*uniform
)
602 struct pipe_sampler_state
*sampl
=
603 &ctx
->samplers
[st
][sampler_index
]->base
;
605 uniform
->f
[0] = sampl
->min_lod
;
606 uniform
->f
[1] = sampl
->max_lod
;
607 uniform
->f
[2] = sampl
->lod_bias
;
609 /* Even without any errata, Midgard represents "no mipmapping" as
610 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
611 * panfrost_create_sampler_state which also explains our choice of
612 * epsilon value (again to keep behaviour consistent) */
614 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
615 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
618 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
619 struct sysval_uniform
*uniform
)
621 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
622 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
623 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
626 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
627 struct panfrost_shader_state
*ss
,
628 enum pipe_shader_type st
)
630 struct sysval_uniform
*uniforms
= (void *)buf
;
632 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
633 int sysval
= ss
->sysval
[i
];
635 switch (PAN_SYSVAL_TYPE(sysval
)) {
636 case PAN_SYSVAL_VIEWPORT_SCALE
:
637 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
639 case PAN_SYSVAL_VIEWPORT_OFFSET
:
640 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
642 case PAN_SYSVAL_TEXTURE_SIZE
:
643 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
646 case PAN_SYSVAL_SSBO
:
647 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
650 case PAN_SYSVAL_NUM_WORK_GROUPS
:
651 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
653 case PAN_SYSVAL_SAMPLER
:
654 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
664 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
666 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
667 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
670 return rsrc
->bo
->cpu
;
671 else if (cb
->user_buffer
)
672 return cb
->user_buffer
;
674 unreachable("No constant buffer");
678 panfrost_map_constant_buffer_gpu(
679 struct panfrost_context
*ctx
,
680 enum pipe_shader_type st
,
681 struct panfrost_constant_buffer
*buf
,
684 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
685 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
686 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
689 panfrost_batch_add_bo(batch
, rsrc
->bo
,
690 PAN_BO_ACCESS_SHARED
|
692 panfrost_bo_access_for_stage(st
));
694 /* Alignment gauranteed by PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
695 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
696 } else if (cb
->user_buffer
) {
697 return panfrost_upload_transient(batch
, cb
->user_buffer
+ cb
->buffer_offset
, cb
->buffer_size
);
699 unreachable("No constant buffer");
703 /* Compute number of UBOs active (more specifically, compute the highest UBO
704 * number addressable -- if there are gaps, include them in the count anyway).
705 * We always include UBO #0 in the count, since we *need* uniforms enabled for
709 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
711 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
712 return 32 - __builtin_clz(mask
);
715 /* Fixes up a shader state with current state */
718 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
719 enum pipe_shader_type stage
)
721 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
724 ctx
->payloads
[stage
].postfix
.shader
= 0;
728 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
730 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
731 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
733 ss
->tripipe
->midgard1
.flags_lo
= 0x220;
735 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
736 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
738 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
740 /* Add the shader BO to the batch. */
741 panfrost_batch_add_bo(batch
, ss
->bo
,
742 PAN_BO_ACCESS_PRIVATE
|
744 panfrost_bo_access_for_stage(stage
));
746 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
748 sizeof(struct mali_shader_meta
));
751 /* Go through dirty flags and actualise them in the cmdstream. */
754 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
756 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
757 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
759 panfrost_batch_add_fbo_bos(batch
);
760 panfrost_attach_vt_framebuffer(ctx
);
762 if (with_vertex_data
) {
763 panfrost_emit_vertex_data(batch
);
765 /* Varyings emitted for -all- geometry */
766 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
767 panfrost_emit_varying_descriptor(ctx
, total_count
);
771 if (ctx
->rasterizer
) {
772 bool msaa
= ctx
->rasterizer
->base
.multisample
;
773 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
775 /* TODO: Sample size */
776 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
777 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
780 panfrost_batch_set_requirements(batch
);
782 if (ctx
->occlusion_query
) {
783 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
784 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
787 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
788 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
790 if (ctx
->shader
[PIPE_SHADER_VERTEX
] && ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
791 /* Check if we need to link the gl_PointSize varying */
792 if (!panfrost_writes_point_size(ctx
)) {
793 /* If the size is constant, write it out. Otherwise,
794 * don't touch primitive_size (since we would clobber
795 * the pointer there) */
797 bool points
= ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
799 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= points
?
800 ctx
->rasterizer
->base
.point_size
:
801 ctx
->rasterizer
->base
.line_width
;
805 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
806 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
808 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
810 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
813 COPY(attribute_count
);
817 COPY(midgard1
.uniform_count
);
818 COPY(midgard1
.uniform_buffer_count
);
819 COPY(midgard1
.work_count
);
820 COPY(midgard1
.flags_lo
);
821 COPY(midgard1
.flags_hi
);
825 /* Get blending setup */
826 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
828 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
829 unsigned shader_offset
= 0;
830 struct panfrost_bo
*shader_bo
= NULL
;
832 for (unsigned c
= 0; c
< rt_count
; ++c
) {
833 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
836 /* If there is a blend shader, work registers are shared. XXX: opt */
838 for (unsigned c
= 0; c
< rt_count
; ++c
) {
839 if (blend
[c
].is_shader
)
840 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
843 /* Depending on whether it's legal to in the given shader, we
844 * try to enable early-z testing (or forward-pixel kill?) */
846 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_EARLY_Z
,
847 !variant
->can_discard
&& !variant
->writes_depth
);
849 /* Add the writes Z/S flags if needed. */
850 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
,
851 MALI_WRITES_Z
, variant
->writes_depth
);
852 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_hi
,
853 MALI_WRITES_S
, variant
->writes_stencil
);
855 /* Any time texturing is used, derivatives are implicitly
856 * calculated, so we need to enable helper invocations */
858 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
860 /* Assign the stencil refs late */
862 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
863 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
864 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
866 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
867 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
869 /* CAN_DISCARD should be set if the fragment shader possibly
870 * contains a 'discard' instruction. It is likely this is
871 * related to optimizations related to forward-pixel kill, as
872 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
873 * thing?" by Peter Harris
876 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
877 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, 0x400, variant
->can_discard
);
879 /* Even on MFBD, the shader descriptor gets blend shaders. It's
880 * *also* copied to the blend_meta appended (by convention),
881 * but this is the field actually read by the hardware. (Or
882 * maybe both are read...?). Specify the last RTi with a blend
885 ctx
->fragment_shader_core
.blend
.shader
= 0;
887 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
888 if (blend
[rt
].is_shader
) {
889 ctx
->fragment_shader_core
.blend
.shader
=
890 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
895 if (screen
->quirks
& MIDGARD_SFBD
) {
896 /* When only a single render target platform is used, the blend
897 * information is inside the shader meta itself. We
898 * additionally need to signal CAN_DISCARD for nontrivial blend
899 * modes (so we're able to read back the destination buffer) */
901 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
903 if (!blend
[0].is_shader
) {
904 ctx
->fragment_shader_core
.blend
.equation
=
905 *blend
[0].equation
.equation
;
906 ctx
->fragment_shader_core
.blend
.constant
=
907 blend
[0].equation
.constant
;
910 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
913 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
914 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
915 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
917 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
919 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
920 /* Additional blend descriptor tacked on for jobs using MFBD */
922 struct midgard_blend_rt rts
[4];
924 for (unsigned i
= 0; i
< rt_count
; ++i
) {
925 rts
[i
].flags
= 0x200;
928 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
929 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
930 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
932 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
933 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
934 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
935 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
937 if (blend
[i
].is_shader
) {
938 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
940 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
941 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
945 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
949 /* We stage to transient, so always dirty.. */
951 panfrost_stage_attributes(ctx
);
953 panfrost_upload_sampler_descriptors(ctx
);
954 panfrost_upload_texture_descriptors(ctx
);
956 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
958 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
959 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
964 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
966 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
968 /* Uniforms are implicitly UBO #0 */
969 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
971 /* Allocate room for the sysval and the uniforms */
972 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
973 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
974 size_t size
= sys_size
+ uniform_size
;
975 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
977 /* Upload sysvals requested by the shader */
978 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
980 /* Upload uniforms */
981 if (has_uniforms
&& uniform_size
) {
982 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
983 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
987 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
989 struct mali_vertex_tiler_postfix
*postfix
=
990 &ctx
->payloads
[i
].postfix
;
992 /* Next up, attach UBOs. UBO #0 is the uniforms we just
995 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
996 assert(ubo_count
>= 1);
998 size_t sz
= sizeof(uint64_t) * ubo_count
;
999 uint64_t ubos
[PAN_MAX_CONST_BUFFERS
];
1001 /* Upload uniforms as a UBO */
1002 ubos
[0] = MALI_MAKE_UBO(2 + uniform_count
, transfer
.gpu
);
1004 /* The rest are honest-to-goodness UBOs */
1006 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1007 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1009 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1010 bool empty
= usz
== 0;
1012 if (!enabled
|| empty
) {
1013 /* Stub out disabled UBOs to catch accesses */
1014 ubos
[ubo
] = MALI_MAKE_UBO(0, 0xDEAD0000);
1018 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1020 unsigned bytes_per_field
= 16;
1021 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1022 ubos
[ubo
] = MALI_MAKE_UBO(aligned
/ bytes_per_field
, gpu
);
1025 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1026 postfix
->uniforms
= transfer
.gpu
;
1027 postfix
->uniform_buffers
= ubufs
;
1029 buf
->dirty_mask
= 0;
1032 /* TODO: Upload the viewport somewhere more appropriate */
1034 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1035 * (somewhat) asymmetric ints. */
1036 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1038 struct mali_viewport view
= {
1039 /* By default, do no viewport clipping, i.e. clip to (-inf,
1040 * inf) in each direction. Clipping to the viewport in theory
1041 * should work, but in practice causes issues when we're not
1042 * explicitly trying to scissor */
1044 .clip_minx
= -INFINITY
,
1045 .clip_miny
= -INFINITY
,
1046 .clip_maxx
= INFINITY
,
1047 .clip_maxy
= INFINITY
,
1050 /* Always scissor to the viewport by default. */
1051 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1052 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1054 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1055 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1057 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1058 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1060 /* Apply the scissor test */
1062 unsigned minx
, miny
, maxx
, maxy
;
1064 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1065 minx
= MAX2(ss
->minx
, vp_minx
);
1066 miny
= MAX2(ss
->miny
, vp_miny
);
1067 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1068 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1076 /* Hardware needs the min/max to be strictly ordered, so flip if we
1077 * need to. The viewport transformation in the vertex shader will
1078 * handle the negatives if we don't */
1081 unsigned temp
= miny
;
1087 unsigned temp
= minx
;
1098 /* Clamp to the framebuffer size as a last check */
1100 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1101 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1103 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1104 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1106 /* Update the job, unless we're doing wallpapering (whose lack of
1107 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1108 * just... be faster :) */
1110 if (!ctx
->wallpaper_batch
)
1111 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1115 view
.viewport0
[0] = minx
;
1116 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1118 view
.viewport0
[1] = miny
;
1119 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1121 view
.clip_minz
= minz
;
1122 view
.clip_maxz
= maxz
;
1124 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1125 panfrost_upload_transient(batch
,
1127 sizeof(struct mali_viewport
));
1130 /* Corresponds to exactly one draw, but does not submit anything */
1133 panfrost_queue_draw(struct panfrost_context
*ctx
)
1135 /* Handle dirty flags now */
1136 panfrost_emit_for_draw(ctx
, true);
1138 /* If rasterizer discard is enable, only submit the vertex */
1140 bool rasterizer_discard
= ctx
->rasterizer
1141 && ctx
->rasterizer
->base
.rasterizer_discard
;
1144 struct midgard_payload_vertex_tiler
*vertex_payload
= &ctx
->payloads
[PIPE_SHADER_VERTEX
];
1145 struct midgard_payload_vertex_tiler
*tiler_payload
= &ctx
->payloads
[PIPE_SHADER_FRAGMENT
];
1147 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1148 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->tiler_dep
;
1151 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
1152 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, batch
->job_index
+ 2, tiler_payload
, sizeof(*tiler_payload
), true);
1153 panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), true);
1155 unsigned vertex
= panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), false);
1157 if (!rasterizer_discard
)
1158 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, vertex
, tiler_payload
, sizeof(*tiler_payload
), false);
1161 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1162 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1167 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1168 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1172 /* The entire frame is in memory -- send it off to the kernel! */
1176 struct pipe_context
*pipe
,
1177 struct pipe_fence_handle
**fence
,
1180 struct panfrost_context
*ctx
= pan_context(pipe
);
1181 struct util_dynarray fences
;
1183 /* We must collect the fences before the flush is done, otherwise we'll
1184 * lose track of them.
1187 util_dynarray_init(&fences
, NULL
);
1188 hash_table_foreach(ctx
->batches
, hentry
) {
1189 struct panfrost_batch
*batch
= hentry
->data
;
1191 panfrost_batch_fence_reference(batch
->out_sync
);
1192 util_dynarray_append(&fences
,
1193 struct panfrost_batch_fence
*,
1198 /* Submit all pending jobs */
1199 panfrost_flush_all_batches(ctx
, false);
1202 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1203 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1204 *fence
= (struct pipe_fence_handle
*)f
;
1206 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1207 panfrost_batch_fence_unreference(*fence
);
1209 util_dynarray_fini(&fences
);
1212 if (pan_debug
& PAN_DBG_TRACE
)
1213 pandecode_next_frame();
1216 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1219 g2m_draw_mode(enum pipe_prim_type mode
)
1222 DEFINE_CASE(POINTS
);
1224 DEFINE_CASE(LINE_LOOP
);
1225 DEFINE_CASE(LINE_STRIP
);
1226 DEFINE_CASE(TRIANGLES
);
1227 DEFINE_CASE(TRIANGLE_STRIP
);
1228 DEFINE_CASE(TRIANGLE_FAN
);
1230 DEFINE_CASE(QUAD_STRIP
);
1231 DEFINE_CASE(POLYGON
);
1234 unreachable("Invalid draw mode");
1241 panfrost_translate_index_size(unsigned size
)
1245 return MALI_DRAW_INDEXED_UINT8
;
1248 return MALI_DRAW_INDEXED_UINT16
;
1251 return MALI_DRAW_INDEXED_UINT32
;
1254 unreachable("Invalid index size");
1258 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1259 * good for the duration of the draw (transient), could last longer. Also get
1260 * the bounds on the index buffer for the range accessed by the draw. We do
1261 * these operations together because there are natural optimizations which
1262 * require them to be together. */
1265 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
, unsigned *min_index
, unsigned *max_index
)
1267 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1269 off_t offset
= info
->start
* info
->index_size
;
1270 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1273 bool needs_indices
= true;
1275 if (info
->max_index
!= ~0u) {
1276 *min_index
= info
->min_index
;
1277 *max_index
= info
->max_index
;
1278 needs_indices
= false;
1281 uint64_t ht_key
= 0;
1283 if (!info
->has_user_indices
) {
1284 /* Only resources can be directly mapped */
1285 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1286 PAN_BO_ACCESS_SHARED
|
1287 PAN_BO_ACCESS_READ
|
1288 PAN_BO_ACCESS_VERTEX_TILER
);
1289 out
= rsrc
->bo
->gpu
+ offset
;
1291 /* Check the cache */
1292 if (rsrc
->index_cache
) {
1293 ht_key
= (((uint64_t) info
->count
) << 32) | info
->start
;
1295 struct panfrost_minmax_cache
*cache
= rsrc
->index_cache
;
1297 for (unsigned i
= 0; i
< cache
->size
; ++i
) {
1298 if (cache
->keys
[i
] == ht_key
) {
1299 uint64_t hit
= cache
->values
[i
];
1301 *min_index
= hit
& 0xffffffff;
1302 *max_index
= hit
>> 32;
1303 needs_indices
= false;
1309 /* Otherwise, we need to upload to transient memory */
1310 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1311 out
= panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1314 if (needs_indices
) {
1316 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
1318 if (!info
->has_user_indices
&& rsrc
->index_cache
) {
1319 struct panfrost_minmax_cache
*cache
= rsrc
->index_cache
;
1320 uint64_t value
= (*min_index
) | (((uint64_t) *max_index
) << 32);
1323 if (cache
->size
== PANFROST_MINMAX_SIZE
) {
1324 index
= cache
->index
++;
1325 cache
->index
= cache
->index
% PANFROST_MINMAX_SIZE
;
1327 index
= cache
->size
++;
1330 cache
->keys
[index
] = ht_key
;
1331 cache
->values
[index
] = value
;
1340 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1342 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1344 /* Check if we're scissoring at all */
1346 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1349 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1352 /* Count generated primitives (when there is no geom/tess shaders) for
1353 * transform feedback */
1356 panfrost_statistics_record(
1357 struct panfrost_context
*ctx
,
1358 const struct pipe_draw_info
*info
)
1360 if (!ctx
->active_queries
)
1363 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1364 ctx
->prims_generated
+= prims
;
1366 if (!ctx
->streamout
.num_targets
)
1369 ctx
->tf_prims_generated
+= prims
;
1374 struct pipe_context
*pipe
,
1375 const struct pipe_draw_info
*info
)
1377 struct panfrost_context
*ctx
= pan_context(pipe
);
1379 /* First of all, check the scissor to see if anything is drawn at all.
1380 * If it's not, we drop the draw (mostly a conformance issue;
1381 * well-behaved apps shouldn't hit this) */
1383 if (panfrost_scissor_culls_everything(ctx
))
1386 int mode
= info
->mode
;
1388 /* Fallback unsupported restart index */
1389 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1391 if (info
->primitive_restart
&& info
->index_size
1392 && info
->restart_index
!= primitive_index
) {
1393 util_draw_vbo_without_prim_restart(pipe
, info
);
1397 /* Fallback for unsupported modes */
1399 assert(ctx
->rasterizer
!= NULL
);
1401 if (!(ctx
->draw_modes
& (1 << mode
))) {
1402 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1403 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1405 if (info
->count
< 4) {
1406 /* Degenerate case? */
1410 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1411 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1416 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1417 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1419 /* Now that we have a guaranteed terminating path, find the job.
1420 * Assignment commented out to prevent unused warning */
1422 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1424 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1426 /* Take into account a negative bias */
1427 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1428 ctx
->instance_count
= info
->instance_count
;
1429 ctx
->active_prim
= info
->mode
;
1431 /* For non-indexed draws, they're the same */
1432 unsigned vertex_count
= ctx
->vertex_count
;
1434 unsigned draw_flags
= 0;
1436 /* The draw flags interpret how primitive size is interpreted */
1438 if (panfrost_writes_point_size(ctx
))
1439 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1441 if (info
->primitive_restart
)
1442 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1444 /* These doesn't make much sense */
1446 draw_flags
|= 0x3000;
1448 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1449 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1451 panfrost_statistics_record(ctx
, info
);
1453 if (info
->index_size
) {
1454 unsigned min_index
= 0, max_index
= 0;
1455 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
=
1456 panfrost_get_index_buffer_bounded(ctx
, info
, &min_index
, &max_index
);
1458 /* Use the corresponding values */
1459 vertex_count
= max_index
- min_index
+ 1;
1460 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1461 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1463 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1464 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1466 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1468 /* Index count == vertex count, if no indexing is applied, as
1469 * if it is internally indexed in the expected order */
1471 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1472 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1474 /* Reverse index state */
1475 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
1478 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1479 * vertex_count, 1) */
1481 panfrost_pack_work_groups_fused(
1482 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1483 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1484 1, vertex_count
, info
->instance_count
,
1487 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1489 /* Encode the padded vertex count */
1491 if (info
->instance_count
> 1) {
1492 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1494 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1495 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1497 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1498 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1500 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1501 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1503 ctx
->padded_count
= vertex_count
;
1505 /* Reset instancing state */
1506 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1507 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1508 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1509 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1512 /* Fire off the draw itself */
1513 panfrost_queue_draw(ctx
);
1515 /* Increment transform feedback offsets */
1517 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1518 unsigned output_count
= u_stream_outputs_for_vertices(
1519 ctx
->active_prim
, ctx
->vertex_count
);
1521 ctx
->streamout
.offsets
[i
] += output_count
;
1528 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1534 panfrost_create_rasterizer_state(
1535 struct pipe_context
*pctx
,
1536 const struct pipe_rasterizer_state
*cso
)
1538 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1542 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1543 so
->tiler_gl_enables
= 0x7;
1546 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1548 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1549 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1551 if (cso
->cull_face
& PIPE_FACE_BACK
)
1552 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1558 panfrost_bind_rasterizer_state(
1559 struct pipe_context
*pctx
,
1562 struct panfrost_context
*ctx
= pan_context(pctx
);
1564 ctx
->rasterizer
= hwcso
;
1569 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1570 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1572 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1573 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1575 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1577 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1578 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1580 /* Point sprites are emulated */
1582 struct panfrost_shader_state
*variant
=
1583 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1585 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1586 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1590 panfrost_create_vertex_elements_state(
1591 struct pipe_context
*pctx
,
1592 unsigned num_elements
,
1593 const struct pipe_vertex_element
*elements
)
1595 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1597 so
->num_elements
= num_elements
;
1598 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1600 for (int i
= 0; i
< num_elements
; ++i
) {
1601 so
->hw
[i
].index
= i
;
1603 enum pipe_format fmt
= elements
[i
].src_format
;
1604 const struct util_format_description
*desc
= util_format_description(fmt
);
1605 so
->hw
[i
].unknown1
= 0x2;
1606 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1608 so
->hw
[i
].format
= panfrost_find_format(desc
);
1610 /* The field itself should probably be shifted over */
1611 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1618 panfrost_bind_vertex_elements_state(
1619 struct pipe_context
*pctx
,
1622 struct panfrost_context
*ctx
= pan_context(pctx
);
1623 ctx
->vertex
= hwcso
;
1627 panfrost_create_shader_state(
1628 struct pipe_context
*pctx
,
1629 const struct pipe_shader_state
*cso
,
1630 enum pipe_shader_type stage
)
1632 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1635 /* Token deep copy to prevent memory corruption */
1637 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1638 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1640 /* Precompile for shader-db if we need to */
1641 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1642 struct panfrost_context
*ctx
= pan_context(pctx
);
1644 struct mali_shader_meta meta
;
1645 struct panfrost_shader_state state
;
1646 uint64_t outputs_written
;
1648 panfrost_shader_compile(ctx
, &meta
,
1651 tgsi_processor_to_shader_stage(stage
), &state
,
1659 panfrost_delete_shader_state(
1660 struct pipe_context
*pctx
,
1663 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1665 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1666 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1669 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1670 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1671 panfrost_bo_unreference(shader_state
->bo
);
1672 shader_state
->bo
= NULL
;
1674 free(cso
->variants
);
1680 panfrost_create_sampler_state(
1681 struct pipe_context
*pctx
,
1682 const struct pipe_sampler_state
*cso
)
1684 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1687 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1689 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1690 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1691 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1693 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1694 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1695 unsigned mip_filter
= mip_linear
?
1696 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1697 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1699 struct mali_sampler_descriptor sampler_descriptor
= {
1700 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1701 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1702 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1703 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1704 .compare_func
= panfrost_flip_compare_func(
1705 panfrost_translate_compare_func(
1706 cso
->compare_func
)),
1708 cso
->border_color
.f
[0],
1709 cso
->border_color
.f
[1],
1710 cso
->border_color
.f
[2],
1711 cso
->border_color
.f
[3]
1713 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1714 .max_lod
= FIXED_16(cso
->max_lod
, false),
1715 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1716 .seamless_cube_map
= cso
->seamless_cube_map
,
1719 /* If necessary, we disable mipmapping in the sampler descriptor by
1720 * clamping the LOD as tight as possible (from 0 to epsilon,
1721 * essentially -- remember these are fixed point numbers, so
1724 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
1725 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1727 /* Enforce that there is something in the middle by adding epsilon*/
1729 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1730 sampler_descriptor
.max_lod
++;
1733 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1736 so
->hw
= sampler_descriptor
;
1742 panfrost_bind_sampler_states(
1743 struct pipe_context
*pctx
,
1744 enum pipe_shader_type shader
,
1745 unsigned start_slot
, unsigned num_sampler
,
1748 assert(start_slot
== 0);
1750 struct panfrost_context
*ctx
= pan_context(pctx
);
1752 /* XXX: Should upload, not just copy? */
1753 ctx
->sampler_count
[shader
] = num_sampler
;
1754 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1758 panfrost_variant_matches(
1759 struct panfrost_context
*ctx
,
1760 struct panfrost_shader_state
*variant
,
1761 enum pipe_shader_type type
)
1763 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1764 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1766 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1768 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1769 /* Make sure enable state is at least the same */
1770 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1774 /* Check that the contents of the test are the same */
1775 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1776 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1778 if (!(same_func
&& same_ref
)) {
1783 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1784 variant
->point_sprite_mask
)) {
1785 /* Ensure the same varyings are turned to point sprites */
1786 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1789 /* Ensure the orientation is correct */
1791 rasterizer
->sprite_coord_mode
==
1792 PIPE_SPRITE_COORD_UPPER_LEFT
;
1794 if (variant
->point_sprite_upper_left
!= upper_left
)
1798 /* Otherwise, we're good to go */
1803 * Fix an uncompiled shader's stream output info, and produce a bitmask
1804 * of which VARYING_SLOT_* are captured for stream output.
1806 * Core Gallium stores output->register_index as a "slot" number, where
1807 * slots are assigned consecutively to all outputs in info->outputs_written.
1808 * This naive packing of outputs doesn't work for us - we too have slots,
1809 * but the layout is defined by the VUE map, which we won't have until we
1810 * compile a specific shader variant. So, we remap these and simply store
1811 * VARYING_SLOT_* in our copy's output->register_index fields.
1813 * We then produce a bitmask of outputs which are used for SO.
1815 * Implementation from iris.
1819 update_so_info(struct pipe_stream_output_info
*so_info
,
1820 uint64_t outputs_written
)
1822 uint64_t so_outputs
= 0;
1823 uint8_t reverse_map
[64] = {0};
1826 while (outputs_written
)
1827 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1829 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1830 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1832 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1833 output
->register_index
= reverse_map
[output
->register_index
];
1835 so_outputs
|= 1ull << output
->register_index
;
1842 panfrost_bind_shader_state(
1843 struct pipe_context
*pctx
,
1845 enum pipe_shader_type type
)
1847 struct panfrost_context
*ctx
= pan_context(pctx
);
1848 ctx
->shader
[type
] = hwcso
;
1852 /* Match the appropriate variant */
1854 signed variant
= -1;
1855 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1857 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1858 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1864 if (variant
== -1) {
1865 /* No variant matched, so create a new one */
1866 variant
= variants
->variant_count
++;
1868 if (variants
->variant_count
> variants
->variant_space
) {
1869 unsigned old_space
= variants
->variant_space
;
1871 variants
->variant_space
*= 2;
1872 if (variants
->variant_space
== 0)
1873 variants
->variant_space
= 1;
1875 /* Arbitrary limit to stop runaway programs from
1876 * creating an unbounded number of shader variants. */
1877 assert(variants
->variant_space
< 1024);
1879 unsigned msize
= sizeof(struct panfrost_shader_state
);
1880 variants
->variants
= realloc(variants
->variants
,
1881 variants
->variant_space
* msize
);
1883 memset(&variants
->variants
[old_space
], 0,
1884 (variants
->variant_space
- old_space
) * msize
);
1887 struct panfrost_shader_state
*v
=
1888 &variants
->variants
[variant
];
1890 if (type
== PIPE_SHADER_FRAGMENT
) {
1891 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1893 if (ctx
->rasterizer
) {
1894 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1895 v
->point_sprite_upper_left
=
1896 ctx
->rasterizer
->base
.sprite_coord_mode
==
1897 PIPE_SPRITE_COORD_UPPER_LEFT
;
1901 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1905 /* Select this variant */
1906 variants
->active_variant
= variant
;
1908 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1909 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1911 /* We finally have a variant, so compile it */
1913 if (!shader_state
->compiled
) {
1914 uint64_t outputs_written
= 0;
1916 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1917 variants
->base
.type
,
1918 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1919 variants
->base
.ir
.nir
:
1920 variants
->base
.tokens
,
1921 tgsi_processor_to_shader_stage(type
), shader_state
,
1924 shader_state
->compiled
= true;
1926 /* Fixup the stream out information, since what Gallium returns
1927 * normally is mildly insane */
1929 shader_state
->stream_output
= variants
->base
.stream_output
;
1930 shader_state
->so_mask
=
1931 update_so_info(&shader_state
->stream_output
, outputs_written
);
1936 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1938 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1942 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1944 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1948 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1950 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1954 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1956 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1960 panfrost_set_vertex_buffers(
1961 struct pipe_context
*pctx
,
1962 unsigned start_slot
,
1963 unsigned num_buffers
,
1964 const struct pipe_vertex_buffer
*buffers
)
1966 struct panfrost_context
*ctx
= pan_context(pctx
);
1968 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1972 panfrost_set_constant_buffer(
1973 struct pipe_context
*pctx
,
1974 enum pipe_shader_type shader
, uint index
,
1975 const struct pipe_constant_buffer
*buf
)
1977 struct panfrost_context
*ctx
= pan_context(pctx
);
1978 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1980 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
1982 unsigned mask
= (1 << index
);
1984 if (unlikely(!buf
)) {
1985 pbuf
->enabled_mask
&= ~mask
;
1986 pbuf
->dirty_mask
&= ~mask
;
1990 pbuf
->enabled_mask
|= mask
;
1991 pbuf
->dirty_mask
|= mask
;
1995 panfrost_set_stencil_ref(
1996 struct pipe_context
*pctx
,
1997 const struct pipe_stencil_ref
*ref
)
1999 struct panfrost_context
*ctx
= pan_context(pctx
);
2000 ctx
->stencil_ref
= *ref
;
2003 static enum mali_texture_type
2004 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2008 case PIPE_TEXTURE_1D
:
2009 case PIPE_TEXTURE_1D_ARRAY
:
2012 case PIPE_TEXTURE_2D
:
2013 case PIPE_TEXTURE_2D_ARRAY
:
2014 case PIPE_TEXTURE_RECT
:
2017 case PIPE_TEXTURE_3D
:
2020 case PIPE_TEXTURE_CUBE
:
2021 case PIPE_TEXTURE_CUBE_ARRAY
:
2022 return MALI_TEX_CUBE
;
2025 unreachable("Unknown target");
2029 static struct pipe_sampler_view
*
2030 panfrost_create_sampler_view(
2031 struct pipe_context
*pctx
,
2032 struct pipe_resource
*texture
,
2033 const struct pipe_sampler_view
*template)
2035 struct panfrost_screen
*screen
= pan_screen(pctx
->screen
);
2036 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2038 pipe_reference(NULL
, &texture
->reference
);
2040 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2043 so
->base
= *template;
2044 so
->base
.texture
= texture
;
2045 so
->base
.reference
.count
= 1;
2046 so
->base
.context
= pctx
;
2048 unsigned char user_swizzle
[4] = {
2049 template->swizzle_r
,
2050 template->swizzle_g
,
2051 template->swizzle_b
,
2055 /* In the hardware, array_size refers specifically to array textures,
2056 * whereas in Gallium, it also covers cubemaps */
2058 unsigned array_size
= texture
->array_size
;
2060 if (template->target
== PIPE_TEXTURE_CUBE
) {
2061 /* TODO: Cubemap arrays */
2062 assert(array_size
== 6);
2066 enum mali_texture_type type
=
2067 panfrost_translate_texture_type(template->target
);
2069 unsigned size
= panfrost_estimate_texture_size(
2070 template->u
.tex
.first_level
,
2071 template->u
.tex
.last_level
,
2072 template->u
.tex
.first_layer
,
2073 template->u
.tex
.last_layer
,
2074 type
, prsrc
->layout
);
2076 so
->bo
= panfrost_bo_create(screen
, size
, 0);
2078 panfrost_new_texture(
2080 texture
->width0
, texture
->height0
,
2081 texture
->depth0
, array_size
,
2083 type
, prsrc
->layout
,
2084 template->u
.tex
.first_level
,
2085 template->u
.tex
.last_level
,
2086 template->u
.tex
.first_layer
,
2087 template->u
.tex
.last_layer
,
2088 prsrc
->cubemap_stride
,
2089 panfrost_translate_swizzle_4(user_swizzle
),
2093 return (struct pipe_sampler_view
*) so
;
2097 panfrost_set_sampler_views(
2098 struct pipe_context
*pctx
,
2099 enum pipe_shader_type shader
,
2100 unsigned start_slot
, unsigned num_views
,
2101 struct pipe_sampler_view
**views
)
2103 struct panfrost_context
*ctx
= pan_context(pctx
);
2104 unsigned new_nr
= 0;
2107 assert(start_slot
== 0);
2109 for (i
= 0; i
< num_views
; ++i
) {
2112 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2116 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2117 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2120 ctx
->sampler_view_count
[shader
] = new_nr
;
2124 panfrost_sampler_view_destroy(
2125 struct pipe_context
*pctx
,
2126 struct pipe_sampler_view
*pview
)
2128 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
2130 pipe_resource_reference(&pview
->texture
, NULL
);
2131 panfrost_bo_unreference(view
->bo
);
2136 panfrost_set_shader_buffers(
2137 struct pipe_context
*pctx
,
2138 enum pipe_shader_type shader
,
2139 unsigned start
, unsigned count
,
2140 const struct pipe_shader_buffer
*buffers
,
2141 unsigned writable_bitmask
)
2143 struct panfrost_context
*ctx
= pan_context(pctx
);
2145 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2146 buffers
, start
, count
);
2149 /* Hints that a framebuffer should use AFBC where possible */
2153 struct panfrost_screen
*screen
,
2154 const struct pipe_framebuffer_state
*fb
)
2156 /* AFBC implemenation incomplete; hide it */
2157 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2159 /* Hint AFBC to the resources bound to each color buffer */
2161 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2162 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2163 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2164 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
2167 /* Also hint it to the depth buffer */
2170 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2171 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
2176 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2177 const struct pipe_framebuffer_state
*fb
)
2179 struct panfrost_context
*ctx
= pan_context(pctx
);
2181 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2182 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2184 panfrost_invalidate_frame(ctx
);
2188 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2189 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2191 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2195 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2198 struct panfrost_context
*ctx
= pan_context(pipe
);
2199 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2200 ctx
->depth_stencil
= depth_stencil
;
2205 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2206 * emulated in the fragment shader */
2208 if (depth_stencil
->alpha
.enabled
) {
2209 /* We need to trigger a new shader (maybe) */
2210 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2214 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2216 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2217 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2219 /* If back-stencil is not enabled, use the front values */
2220 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2221 unsigned back_index
= back_enab
? 1 : 0;
2223 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2224 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2226 /* Depth state (TODO: Refactor) */
2227 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2228 depth_stencil
->depth
.writemask
);
2230 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2232 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2233 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2235 /* Bounds test not implemented */
2236 assert(!depth_stencil
->depth
.bounds_test
);
2240 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2246 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2247 unsigned sample_mask
)
2252 panfrost_set_clip_state(struct pipe_context
*pipe
,
2253 const struct pipe_clip_state
*clip
)
2255 //struct panfrost_context *panfrost = pan_context(pipe);
2259 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2260 unsigned start_slot
,
2261 unsigned num_viewports
,
2262 const struct pipe_viewport_state
*viewports
)
2264 struct panfrost_context
*ctx
= pan_context(pipe
);
2266 assert(start_slot
== 0);
2267 assert(num_viewports
== 1);
2269 ctx
->pipe_viewport
= *viewports
;
2273 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2274 unsigned start_slot
,
2275 unsigned num_scissors
,
2276 const struct pipe_scissor_state
*scissors
)
2278 struct panfrost_context
*ctx
= pan_context(pipe
);
2280 assert(start_slot
== 0);
2281 assert(num_scissors
== 1);
2283 ctx
->scissor
= *scissors
;
2287 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2288 const struct pipe_poly_stipple
*stipple
)
2290 //struct panfrost_context *panfrost = pan_context(pipe);
2294 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2297 struct panfrost_context
*ctx
= pan_context(pipe
);
2298 ctx
->active_queries
= enable
;
2302 panfrost_destroy(struct pipe_context
*pipe
)
2304 struct panfrost_context
*panfrost
= pan_context(pipe
);
2306 if (panfrost
->blitter
)
2307 util_blitter_destroy(panfrost
->blitter
);
2309 if (panfrost
->blitter_wallpaper
)
2310 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2312 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2313 u_upload_destroy(pipe
->stream_uploader
);
2318 static struct pipe_query
*
2319 panfrost_create_query(struct pipe_context
*pipe
,
2323 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2328 return (struct pipe_query
*) q
;
2332 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2334 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2337 panfrost_bo_unreference(query
->bo
);
2345 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2347 struct panfrost_context
*ctx
= pan_context(pipe
);
2348 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2350 switch (query
->type
) {
2351 case PIPE_QUERY_OCCLUSION_COUNTER
:
2352 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2353 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2354 /* Allocate a bo for the query results to be stored */
2356 query
->bo
= panfrost_bo_create(
2357 pan_screen(ctx
->base
.screen
),
2358 sizeof(unsigned), 0);
2361 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2362 *result
= 0; /* Default to 0 if nothing at all drawn. */
2363 ctx
->occlusion_query
= query
;
2366 /* Geometry statistics are computed in the driver. XXX: geom/tess
2369 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2370 query
->start
= ctx
->prims_generated
;
2372 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2373 query
->start
= ctx
->tf_prims_generated
;
2377 DBG("Skipping query %u\n", query
->type
);
2385 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2387 struct panfrost_context
*ctx
= pan_context(pipe
);
2388 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2390 switch (query
->type
) {
2391 case PIPE_QUERY_OCCLUSION_COUNTER
:
2392 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2393 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2394 ctx
->occlusion_query
= NULL
;
2396 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2397 query
->end
= ctx
->prims_generated
;
2399 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2400 query
->end
= ctx
->tf_prims_generated
;
2408 panfrost_get_query_result(struct pipe_context
*pipe
,
2409 struct pipe_query
*q
,
2411 union pipe_query_result
*vresult
)
2413 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2414 struct panfrost_context
*ctx
= pan_context(pipe
);
2417 switch (query
->type
) {
2418 case PIPE_QUERY_OCCLUSION_COUNTER
:
2419 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2420 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2422 panfrost_flush_all_batches(ctx
, true);
2424 /* Read back the query results */
2425 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2426 unsigned passed
= *result
;
2428 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2429 vresult
->u64
= passed
;
2431 vresult
->b
= !!passed
;
2436 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2437 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2438 panfrost_flush_all_batches(ctx
, true);
2439 vresult
->u64
= query
->end
- query
->start
;
2443 DBG("Skipped query get %u\n", query
->type
);
2450 static struct pipe_stream_output_target
*
2451 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2452 struct pipe_resource
*prsc
,
2453 unsigned buffer_offset
,
2454 unsigned buffer_size
)
2456 struct pipe_stream_output_target
*target
;
2458 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2463 pipe_reference_init(&target
->reference
, 1);
2464 pipe_resource_reference(&target
->buffer
, prsc
);
2466 target
->context
= pctx
;
2467 target
->buffer_offset
= buffer_offset
;
2468 target
->buffer_size
= buffer_size
;
2474 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2475 struct pipe_stream_output_target
*target
)
2477 pipe_resource_reference(&target
->buffer
, NULL
);
2478 ralloc_free(target
);
2482 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2483 unsigned num_targets
,
2484 struct pipe_stream_output_target
**targets
,
2485 const unsigned *offsets
)
2487 struct panfrost_context
*ctx
= pan_context(pctx
);
2488 struct panfrost_streamout
*so
= &ctx
->streamout
;
2490 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2492 for (unsigned i
= 0; i
< num_targets
; i
++) {
2493 if (offsets
[i
] != -1)
2494 so
->offsets
[i
] = offsets
[i
];
2496 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2499 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2500 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2502 so
->num_targets
= num_targets
;
2505 struct pipe_context
*
2506 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2508 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2509 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2511 gallium
->screen
= screen
;
2513 gallium
->destroy
= panfrost_destroy
;
2515 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2517 gallium
->flush
= panfrost_flush
;
2518 gallium
->clear
= panfrost_clear
;
2519 gallium
->draw_vbo
= panfrost_draw_vbo
;
2521 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2522 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2523 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2525 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2527 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2528 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2529 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2531 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2532 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2533 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2535 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2536 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2537 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2539 gallium
->create_fs_state
= panfrost_create_fs_state
;
2540 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2541 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2543 gallium
->create_vs_state
= panfrost_create_vs_state
;
2544 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2545 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2547 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2548 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2549 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2551 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2552 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2553 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2555 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2557 gallium
->set_clip_state
= panfrost_set_clip_state
;
2558 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2559 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2560 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2561 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2563 gallium
->create_query
= panfrost_create_query
;
2564 gallium
->destroy_query
= panfrost_destroy_query
;
2565 gallium
->begin_query
= panfrost_begin_query
;
2566 gallium
->end_query
= panfrost_end_query
;
2567 gallium
->get_query_result
= panfrost_get_query_result
;
2569 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2570 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2571 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2573 panfrost_resource_context_init(gallium
);
2574 panfrost_blend_context_init(gallium
);
2575 panfrost_compute_context_init(gallium
);
2578 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2579 gallium
->const_uploader
= gallium
->stream_uploader
;
2580 assert(gallium
->stream_uploader
);
2582 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2583 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2585 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2587 ctx
->blitter
= util_blitter_create(gallium
);
2588 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2590 assert(ctx
->blitter
);
2591 assert(ctx
->blitter_wallpaper
);
2593 /* Prepare for render! */
2595 panfrost_batch_init(ctx
);
2596 panfrost_emit_vertex_payload(ctx
);
2597 panfrost_invalidate_frame(ctx
);
2598 panfrost_default_shader_backend(ctx
);