2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
56 #include "pandecode/decode.h"
58 struct midgard_tiler_descriptor
59 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
61 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
62 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
63 struct midgard_tiler_descriptor t
= {0};
64 unsigned height
= batch
->key
.height
;
65 unsigned width
= batch
->key
.width
;
68 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
70 /* Compute the polygon header size and use that to offset the body */
72 unsigned header_size
= panfrost_tiler_header_size(
73 width
, height
, t
.hierarchy_mask
, hierarchy
);
75 t
.polygon_list_size
= panfrost_tiler_full_size(
76 width
, height
, t
.hierarchy_mask
, hierarchy
);
81 struct panfrost_bo
*tiler_heap
;
83 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
84 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
89 /* Allow the entire tiler heap */
90 t
.heap_start
= tiler_heap
->gpu
;
91 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
93 struct panfrost_bo
*tiler_dummy
;
95 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
96 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
98 /* The tiler is disabled, so don't allow the tiler heap */
99 t
.heap_start
= tiler_dummy
->gpu
;
100 t
.heap_end
= t
.heap_start
;
102 /* Use a dummy polygon list */
103 t
.polygon_list
= tiler_dummy
->gpu
;
105 /* Disable the tiler */
107 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
109 t
.hierarchy_mask
= MALI_TILER_USER
;
110 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
112 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
113 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
114 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
118 t
.polygon_list_body
=
119 t
.polygon_list
+ header_size
;
126 struct pipe_context
*pipe
,
128 const union pipe_color_union
*color
,
129 double depth
, unsigned stencil
)
131 struct panfrost_context
*ctx
= pan_context(pipe
);
133 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
134 * the existing batch targeting this FBO has draws. We could probably
135 * avoid that by replacing plain clears by quad-draws with a specific
136 * color/depth/stencil value, thus avoiding the generation of extra
139 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
141 panfrost_batch_add_fbo_bos(batch
);
142 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
145 /* Reset per-frame context, called on context initialisation as well as after
146 * flushing a frame */
149 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
151 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
152 ctx
->payloads
[i
].postfix
.shared_memory
= 0;
154 /* TODO: When does this need to be handled? */
155 ctx
->active_queries
= true;
158 /* In practice, every field of these payloads should be configurable
159 * arbitrarily, which means these functions are basically catch-all's for
160 * as-of-yet unwavering unknowns */
163 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
165 /* 0x2 bit clear on 32-bit T6XX */
167 struct midgard_payload_vertex_tiler payload
= {
168 .gl_enables
= 0x4 | 0x2,
171 /* Vertex and compute are closely coupled, so share a payload */
173 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
174 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
178 translate_tex_wrap(enum pipe_tex_wrap w
)
181 case PIPE_TEX_WRAP_REPEAT
:
182 return MALI_WRAP_REPEAT
;
184 case PIPE_TEX_WRAP_CLAMP
:
185 return MALI_WRAP_CLAMP
;
187 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
188 return MALI_WRAP_CLAMP_TO_EDGE
;
190 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
191 return MALI_WRAP_CLAMP_TO_BORDER
;
193 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
194 return MALI_WRAP_MIRRORED_REPEAT
;
196 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
197 return MALI_WRAP_MIRRORED_CLAMP
;
199 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
200 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
202 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
203 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
206 unreachable("Invalid wrap");
211 panfrost_writes_point_size(struct panfrost_context
*ctx
)
213 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
214 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
216 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
219 /* Stage the attribute descriptors so we can adjust src_offset
220 * to let BOs align nicely */
223 panfrost_stage_attributes(struct panfrost_context
*ctx
)
225 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
226 struct panfrost_vertex_state
*so
= ctx
->vertex
;
228 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
229 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
230 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
232 /* Copy as-is for the first pass */
233 memcpy(target
, so
->hw
, sz
);
235 /* Fixup offsets for the second pass. Recall that the hardware
236 * calculates attribute addresses as:
238 * addr = base + (stride * vtx) + src_offset;
240 * However, on Mali, base must be aligned to 64-bytes, so we
243 * base' = base & ~63 = base - (base & 63)
245 * To compensate when using base' (see emit_vertex_data), we have
246 * to adjust src_offset by the masked off piece:
248 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
249 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
250 * = base + (stride * vtx) + src_offset
256 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
258 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
259 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
260 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
261 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
262 mali_ptr addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
264 /* Adjust by the masked off bits of the offset. Make sure we
265 * read src_offset from so->hw (which is not GPU visible)
266 * rather than target (which is) due to caching effects */
268 unsigned src_offset
= so
->hw
[i
].src_offset
;
269 src_offset
+= (addr
& 63);
271 /* Also, somewhat obscurely per-instance data needs to be
272 * offset in response to a delayed start in an indexed draw */
274 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
275 src_offset
-= buf
->stride
* start
;
277 target
[i
].src_offset
= src_offset
;
280 /* Let's also include vertex builtins */
282 struct mali_attr_meta builtin
= {
283 .format
= MALI_R32UI
,
284 .swizzle
= panfrost_get_default_swizzle(1)
287 /* See mali_attr_meta specification for the magic number */
289 builtin
.index
= so
->vertexid_index
;
290 memcpy(&target
[PAN_VERTEX_ID
], &builtin
, 4);
292 builtin
.index
= so
->vertexid_index
+ 1;
293 memcpy(&target
[PAN_INSTANCE_ID
], &builtin
, 4);
295 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
299 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
301 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
302 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
304 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
307 if (ctx
->sampler_count
[t
]) {
308 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
310 struct panfrost_transfer transfer
=
311 panfrost_allocate_transient(batch
, transfer_size
);
313 struct mali_sampler_descriptor
*desc
=
314 (struct mali_sampler_descriptor
*) transfer
.cpu
;
316 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
317 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
319 upload
= transfer
.gpu
;
322 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
328 struct panfrost_context
*ctx
,
329 enum pipe_shader_type st
,
330 struct panfrost_sampler_view
*view
)
335 struct pipe_sampler_view
*pview
= &view
->base
;
336 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
338 /* Add the BO to the job so it's retained until the job is done. */
339 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
341 panfrost_batch_add_bo(batch
, rsrc
->bo
,
342 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
343 panfrost_bo_access_for_stage(st
));
345 panfrost_batch_add_bo(batch
, view
->bo
,
346 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
347 panfrost_bo_access_for_stage(st
));
349 return view
->bo
->gpu
;
353 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
355 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
357 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
358 mali_ptr trampoline
= 0;
360 if (ctx
->sampler_view_count
[t
]) {
361 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
363 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
365 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
367 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
370 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
374 /* Compute number of UBOs active (more specifically, compute the highest UBO
375 * number addressable -- if there are gaps, include them in the count anyway).
376 * We always include UBO #0 in the count, since we *need* uniforms enabled for
380 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
382 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
383 return 32 - __builtin_clz(mask
);
386 /* Go through dirty flags and actualise them in the cmdstream. */
389 panfrost_emit_for_draw(struct panfrost_context
*ctx
)
391 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
393 panfrost_batch_add_fbo_bos(batch
);
395 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
)
396 panfrost_vt_attach_framebuffer(ctx
, &ctx
->payloads
[i
]);
398 panfrost_emit_vertex_data(batch
);
400 /* Varyings emitted for -all- geometry */
401 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
402 panfrost_emit_varying_descriptor(ctx
, total_count
);
404 panfrost_batch_set_requirements(batch
);
406 panfrost_vt_update_rasterizer(ctx
, &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
407 panfrost_vt_update_occlusion_query(ctx
, &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
409 panfrost_emit_shader_meta(batch
, PIPE_SHADER_VERTEX
,
410 &ctx
->payloads
[PIPE_SHADER_VERTEX
]);
411 panfrost_emit_shader_meta(batch
, PIPE_SHADER_FRAGMENT
,
412 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
414 /* We stage to transient, so always dirty.. */
416 panfrost_stage_attributes(ctx
);
418 panfrost_upload_sampler_descriptors(ctx
);
419 panfrost_upload_texture_descriptors(ctx
);
421 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
)
422 panfrost_emit_const_buf(batch
, i
, &ctx
->payloads
[i
]);
424 /* TODO: Upload the viewport somewhere more appropriate */
426 panfrost_emit_viewport(batch
, &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
429 /* Corresponds to exactly one draw, but does not submit anything */
432 panfrost_queue_draw(struct panfrost_context
*ctx
)
434 /* Handle dirty flags now */
435 panfrost_emit_for_draw(ctx
);
437 /* If rasterizer discard is enable, only submit the vertex */
439 bool rasterizer_discard
= ctx
->rasterizer
440 && ctx
->rasterizer
->base
.rasterizer_discard
;
443 struct midgard_payload_vertex_tiler
*vertex_payload
= &ctx
->payloads
[PIPE_SHADER_VERTEX
];
444 struct midgard_payload_vertex_tiler
*tiler_payload
= &ctx
->payloads
[PIPE_SHADER_FRAGMENT
];
446 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
447 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->tiler_dep
;
450 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
451 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, batch
->job_index
+ 2, tiler_payload
, sizeof(*tiler_payload
), true);
452 panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), true);
454 unsigned vertex
= panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), false);
456 if (!rasterizer_discard
)
457 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, vertex
, tiler_payload
, sizeof(*tiler_payload
), false);
460 panfrost_batch_adjust_stack_size(batch
);
463 /* The entire frame is in memory -- send it off to the kernel! */
467 struct pipe_context
*pipe
,
468 struct pipe_fence_handle
**fence
,
471 struct panfrost_context
*ctx
= pan_context(pipe
);
472 struct util_dynarray fences
;
474 /* We must collect the fences before the flush is done, otherwise we'll
475 * lose track of them.
478 util_dynarray_init(&fences
, NULL
);
479 hash_table_foreach(ctx
->batches
, hentry
) {
480 struct panfrost_batch
*batch
= hentry
->data
;
482 panfrost_batch_fence_reference(batch
->out_sync
);
483 util_dynarray_append(&fences
,
484 struct panfrost_batch_fence
*,
489 /* Submit all pending jobs */
490 panfrost_flush_all_batches(ctx
, false);
493 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
494 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
495 *fence
= (struct pipe_fence_handle
*)f
;
497 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
498 panfrost_batch_fence_unreference(*fence
);
500 util_dynarray_fini(&fences
);
503 if (pan_debug
& PAN_DBG_TRACE
)
504 pandecode_next_frame();
507 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
510 g2m_draw_mode(enum pipe_prim_type mode
)
515 DEFINE_CASE(LINE_LOOP
);
516 DEFINE_CASE(LINE_STRIP
);
517 DEFINE_CASE(TRIANGLES
);
518 DEFINE_CASE(TRIANGLE_STRIP
);
519 DEFINE_CASE(TRIANGLE_FAN
);
521 DEFINE_CASE(QUAD_STRIP
);
522 DEFINE_CASE(POLYGON
);
525 unreachable("Invalid draw mode");
532 panfrost_translate_index_size(unsigned size
)
536 return MALI_DRAW_INDEXED_UINT8
;
539 return MALI_DRAW_INDEXED_UINT16
;
542 return MALI_DRAW_INDEXED_UINT32
;
545 unreachable("Invalid index size");
549 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
550 * good for the duration of the draw (transient), could last longer. Also get
551 * the bounds on the index buffer for the range accessed by the draw. We do
552 * these operations together because there are natural optimizations which
553 * require them to be together. */
556 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
, unsigned *min_index
, unsigned *max_index
)
558 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
560 off_t offset
= info
->start
* info
->index_size
;
561 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
564 bool needs_indices
= true;
566 if (info
->max_index
!= ~0u) {
567 *min_index
= info
->min_index
;
568 *max_index
= info
->max_index
;
569 needs_indices
= false;
572 if (!info
->has_user_indices
) {
573 /* Only resources can be directly mapped */
574 panfrost_batch_add_bo(batch
, rsrc
->bo
,
575 PAN_BO_ACCESS_SHARED
|
577 PAN_BO_ACCESS_VERTEX_TILER
);
578 out
= rsrc
->bo
->gpu
+ offset
;
580 /* Check the cache */
581 needs_indices
= !panfrost_minmax_cache_get(rsrc
->index_cache
, info
->start
, info
->count
,
582 min_index
, max_index
);
584 /* Otherwise, we need to upload to transient memory */
585 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
586 out
= panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
591 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
593 if (!info
->has_user_indices
) {
594 panfrost_minmax_cache_add(rsrc
->index_cache
, info
->start
, info
->count
,
595 *min_index
, *max_index
);
604 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
606 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
608 /* Check if we're scissoring at all */
610 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
613 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
616 /* Count generated primitives (when there is no geom/tess shaders) for
617 * transform feedback */
620 panfrost_statistics_record(
621 struct panfrost_context
*ctx
,
622 const struct pipe_draw_info
*info
)
624 if (!ctx
->active_queries
)
627 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
628 ctx
->prims_generated
+= prims
;
630 if (!ctx
->streamout
.num_targets
)
633 ctx
->tf_prims_generated
+= prims
;
638 struct pipe_context
*pipe
,
639 const struct pipe_draw_info
*info
)
641 struct panfrost_context
*ctx
= pan_context(pipe
);
643 /* First of all, check the scissor to see if anything is drawn at all.
644 * If it's not, we drop the draw (mostly a conformance issue;
645 * well-behaved apps shouldn't hit this) */
647 if (panfrost_scissor_culls_everything(ctx
))
650 int mode
= info
->mode
;
652 /* Fallback unsupported restart index */
653 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
655 if (info
->primitive_restart
&& info
->index_size
656 && info
->restart_index
!= primitive_index
) {
657 util_draw_vbo_without_prim_restart(pipe
, info
);
661 /* Fallback for unsupported modes */
663 assert(ctx
->rasterizer
!= NULL
);
665 if (!(ctx
->draw_modes
& (1 << mode
))) {
666 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
667 mode
= PIPE_PRIM_TRIANGLE_FAN
;
669 if (info
->count
< 4) {
670 /* Degenerate case? */
674 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
675 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
680 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
681 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
683 /* Now that we have a guaranteed terminating path, find the job.
684 * Assignment commented out to prevent unused warning */
686 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
688 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
690 /* Take into account a negative bias */
691 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
692 ctx
->instance_count
= info
->instance_count
;
693 ctx
->active_prim
= info
->mode
;
695 /* For non-indexed draws, they're the same */
696 unsigned vertex_count
= ctx
->vertex_count
;
698 unsigned draw_flags
= 0;
700 /* The draw flags interpret how primitive size is interpreted */
702 if (panfrost_writes_point_size(ctx
))
703 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
705 if (info
->primitive_restart
)
706 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
708 /* These doesn't make much sense */
710 draw_flags
|= 0x3000;
712 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
713 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
715 panfrost_statistics_record(ctx
, info
);
717 if (info
->index_size
) {
718 unsigned min_index
= 0, max_index
= 0;
719 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
=
720 panfrost_get_index_buffer_bounded(ctx
, info
, &min_index
, &max_index
);
722 /* Use the corresponding values */
723 vertex_count
= max_index
- min_index
+ 1;
724 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
725 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
727 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
728 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
730 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
732 /* Index count == vertex count, if no indexing is applied, as
733 * if it is internally indexed in the expected order */
735 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
736 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
738 /* Reverse index state */
739 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
742 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
743 * vertex_count, 1) */
745 panfrost_pack_work_groups_fused(
746 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
747 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
748 1, vertex_count
, info
->instance_count
,
751 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
753 /* Encode the padded vertex count */
755 if (info
->instance_count
> 1) {
756 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
758 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
759 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
761 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
762 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
764 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
765 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
767 ctx
->padded_count
= vertex_count
;
769 /* Reset instancing state */
770 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
771 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
772 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
773 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
776 /* Fire off the draw itself */
777 panfrost_queue_draw(ctx
);
779 /* Increment transform feedback offsets */
781 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
782 unsigned output_count
= u_stream_outputs_for_vertices(
783 ctx
->active_prim
, ctx
->vertex_count
);
785 ctx
->streamout
.offsets
[i
] += output_count
;
792 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
798 panfrost_create_rasterizer_state(
799 struct pipe_context
*pctx
,
800 const struct pipe_rasterizer_state
*cso
)
802 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
810 panfrost_bind_rasterizer_state(
811 struct pipe_context
*pctx
,
814 struct panfrost_context
*ctx
= pan_context(pctx
);
816 ctx
->rasterizer
= hwcso
;
821 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
822 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
824 /* Point sprites are emulated */
826 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
828 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
829 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
833 panfrost_create_vertex_elements_state(
834 struct pipe_context
*pctx
,
835 unsigned num_elements
,
836 const struct pipe_vertex_element
*elements
)
838 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
840 so
->num_elements
= num_elements
;
841 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
843 for (int i
= 0; i
< num_elements
; ++i
) {
846 enum pipe_format fmt
= elements
[i
].src_format
;
847 const struct util_format_description
*desc
= util_format_description(fmt
);
848 so
->hw
[i
].unknown1
= 0x2;
849 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
851 so
->hw
[i
].format
= panfrost_find_format(desc
);
853 /* The field itself should probably be shifted over */
854 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
861 panfrost_bind_vertex_elements_state(
862 struct pipe_context
*pctx
,
865 struct panfrost_context
*ctx
= pan_context(pctx
);
870 panfrost_create_shader_state(
871 struct pipe_context
*pctx
,
872 const struct pipe_shader_state
*cso
,
873 enum pipe_shader_type stage
)
875 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
878 /* Token deep copy to prevent memory corruption */
880 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
881 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
883 /* Precompile for shader-db if we need to */
884 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
885 struct panfrost_context
*ctx
= pan_context(pctx
);
887 struct panfrost_shader_state state
;
888 uint64_t outputs_written
;
890 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
892 tgsi_processor_to_shader_stage(stage
),
893 &state
, &outputs_written
);
900 panfrost_delete_shader_state(
901 struct pipe_context
*pctx
,
904 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
906 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
907 DBG("Deleting TGSI shader leaks duplicated tokens\n");
910 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
911 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
912 panfrost_bo_unreference(shader_state
->bo
);
913 shader_state
->bo
= NULL
;
921 panfrost_create_sampler_state(
922 struct pipe_context
*pctx
,
923 const struct pipe_sampler_state
*cso
)
925 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
928 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
930 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
931 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
932 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
934 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
935 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
936 unsigned mip_filter
= mip_linear
?
937 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
938 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
940 struct mali_sampler_descriptor sampler_descriptor
= {
941 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
942 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
943 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
944 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
945 .compare_func
= panfrost_flip_compare_func(
946 panfrost_translate_compare_func(
949 cso
->border_color
.f
[0],
950 cso
->border_color
.f
[1],
951 cso
->border_color
.f
[2],
952 cso
->border_color
.f
[3]
954 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
955 .max_lod
= FIXED_16(cso
->max_lod
, false),
956 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
957 .seamless_cube_map
= cso
->seamless_cube_map
,
960 /* If necessary, we disable mipmapping in the sampler descriptor by
961 * clamping the LOD as tight as possible (from 0 to epsilon,
962 * essentially -- remember these are fixed point numbers, so
965 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
966 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
968 /* Enforce that there is something in the middle by adding epsilon*/
970 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
971 sampler_descriptor
.max_lod
++;
974 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
977 so
->hw
= sampler_descriptor
;
983 panfrost_bind_sampler_states(
984 struct pipe_context
*pctx
,
985 enum pipe_shader_type shader
,
986 unsigned start_slot
, unsigned num_sampler
,
989 assert(start_slot
== 0);
991 struct panfrost_context
*ctx
= pan_context(pctx
);
993 /* XXX: Should upload, not just copy? */
994 ctx
->sampler_count
[shader
] = num_sampler
;
995 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
999 panfrost_variant_matches(
1000 struct panfrost_context
*ctx
,
1001 struct panfrost_shader_state
*variant
,
1002 enum pipe_shader_type type
)
1004 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1005 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1007 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1009 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1010 /* Make sure enable state is at least the same */
1011 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1015 /* Check that the contents of the test are the same */
1016 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1017 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1019 if (!(same_func
&& same_ref
)) {
1024 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1025 variant
->point_sprite_mask
)) {
1026 /* Ensure the same varyings are turned to point sprites */
1027 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1030 /* Ensure the orientation is correct */
1032 rasterizer
->sprite_coord_mode
==
1033 PIPE_SPRITE_COORD_UPPER_LEFT
;
1035 if (variant
->point_sprite_upper_left
!= upper_left
)
1039 /* Otherwise, we're good to go */
1044 * Fix an uncompiled shader's stream output info, and produce a bitmask
1045 * of which VARYING_SLOT_* are captured for stream output.
1047 * Core Gallium stores output->register_index as a "slot" number, where
1048 * slots are assigned consecutively to all outputs in info->outputs_written.
1049 * This naive packing of outputs doesn't work for us - we too have slots,
1050 * but the layout is defined by the VUE map, which we won't have until we
1051 * compile a specific shader variant. So, we remap these and simply store
1052 * VARYING_SLOT_* in our copy's output->register_index fields.
1054 * We then produce a bitmask of outputs which are used for SO.
1056 * Implementation from iris.
1060 update_so_info(struct pipe_stream_output_info
*so_info
,
1061 uint64_t outputs_written
)
1063 uint64_t so_outputs
= 0;
1064 uint8_t reverse_map
[64] = {0};
1067 while (outputs_written
)
1068 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1070 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1071 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1073 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1074 output
->register_index
= reverse_map
[output
->register_index
];
1076 so_outputs
|= 1ull << output
->register_index
;
1083 panfrost_bind_shader_state(
1084 struct pipe_context
*pctx
,
1086 enum pipe_shader_type type
)
1088 struct panfrost_context
*ctx
= pan_context(pctx
);
1089 ctx
->shader
[type
] = hwcso
;
1093 /* Match the appropriate variant */
1095 signed variant
= -1;
1096 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1098 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1099 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1105 if (variant
== -1) {
1106 /* No variant matched, so create a new one */
1107 variant
= variants
->variant_count
++;
1109 if (variants
->variant_count
> variants
->variant_space
) {
1110 unsigned old_space
= variants
->variant_space
;
1112 variants
->variant_space
*= 2;
1113 if (variants
->variant_space
== 0)
1114 variants
->variant_space
= 1;
1116 /* Arbitrary limit to stop runaway programs from
1117 * creating an unbounded number of shader variants. */
1118 assert(variants
->variant_space
< 1024);
1120 unsigned msize
= sizeof(struct panfrost_shader_state
);
1121 variants
->variants
= realloc(variants
->variants
,
1122 variants
->variant_space
* msize
);
1124 memset(&variants
->variants
[old_space
], 0,
1125 (variants
->variant_space
- old_space
) * msize
);
1128 struct panfrost_shader_state
*v
=
1129 &variants
->variants
[variant
];
1131 if (type
== PIPE_SHADER_FRAGMENT
) {
1132 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1134 if (ctx
->rasterizer
) {
1135 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1136 v
->point_sprite_upper_left
=
1137 ctx
->rasterizer
->base
.sprite_coord_mode
==
1138 PIPE_SPRITE_COORD_UPPER_LEFT
;
1143 /* Select this variant */
1144 variants
->active_variant
= variant
;
1146 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1147 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1149 /* We finally have a variant, so compile it */
1151 if (!shader_state
->compiled
) {
1152 uint64_t outputs_written
= 0;
1154 panfrost_shader_compile(ctx
, variants
->base
.type
,
1155 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1156 variants
->base
.ir
.nir
:
1157 variants
->base
.tokens
,
1158 tgsi_processor_to_shader_stage(type
),
1162 shader_state
->compiled
= true;
1164 /* Fixup the stream out information, since what Gallium returns
1165 * normally is mildly insane */
1167 shader_state
->stream_output
= variants
->base
.stream_output
;
1168 shader_state
->so_mask
=
1169 update_so_info(&shader_state
->stream_output
, outputs_written
);
1174 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1176 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1180 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1182 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1186 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1188 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1192 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1194 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1198 panfrost_set_vertex_buffers(
1199 struct pipe_context
*pctx
,
1200 unsigned start_slot
,
1201 unsigned num_buffers
,
1202 const struct pipe_vertex_buffer
*buffers
)
1204 struct panfrost_context
*ctx
= pan_context(pctx
);
1206 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1210 panfrost_set_constant_buffer(
1211 struct pipe_context
*pctx
,
1212 enum pipe_shader_type shader
, uint index
,
1213 const struct pipe_constant_buffer
*buf
)
1215 struct panfrost_context
*ctx
= pan_context(pctx
);
1216 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1218 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
1220 unsigned mask
= (1 << index
);
1222 if (unlikely(!buf
)) {
1223 pbuf
->enabled_mask
&= ~mask
;
1224 pbuf
->dirty_mask
&= ~mask
;
1228 pbuf
->enabled_mask
|= mask
;
1229 pbuf
->dirty_mask
|= mask
;
1233 panfrost_set_stencil_ref(
1234 struct pipe_context
*pctx
,
1235 const struct pipe_stencil_ref
*ref
)
1237 struct panfrost_context
*ctx
= pan_context(pctx
);
1238 ctx
->stencil_ref
= *ref
;
1241 static enum mali_texture_type
1242 panfrost_translate_texture_type(enum pipe_texture_target t
) {
1246 case PIPE_TEXTURE_1D
:
1247 case PIPE_TEXTURE_1D_ARRAY
:
1250 case PIPE_TEXTURE_2D
:
1251 case PIPE_TEXTURE_2D_ARRAY
:
1252 case PIPE_TEXTURE_RECT
:
1255 case PIPE_TEXTURE_3D
:
1258 case PIPE_TEXTURE_CUBE
:
1259 case PIPE_TEXTURE_CUBE_ARRAY
:
1260 return MALI_TEX_CUBE
;
1263 unreachable("Unknown target");
1267 static struct pipe_sampler_view
*
1268 panfrost_create_sampler_view(
1269 struct pipe_context
*pctx
,
1270 struct pipe_resource
*texture
,
1271 const struct pipe_sampler_view
*template)
1273 struct panfrost_screen
*screen
= pan_screen(pctx
->screen
);
1274 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
1276 pipe_reference(NULL
, &texture
->reference
);
1278 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1281 so
->base
= *template;
1282 so
->base
.texture
= texture
;
1283 so
->base
.reference
.count
= 1;
1284 so
->base
.context
= pctx
;
1286 unsigned char user_swizzle
[4] = {
1287 template->swizzle_r
,
1288 template->swizzle_g
,
1289 template->swizzle_b
,
1293 /* In the hardware, array_size refers specifically to array textures,
1294 * whereas in Gallium, it also covers cubemaps */
1296 unsigned array_size
= texture
->array_size
;
1298 if (template->target
== PIPE_TEXTURE_CUBE
) {
1299 /* TODO: Cubemap arrays */
1300 assert(array_size
== 6);
1304 enum mali_texture_type type
=
1305 panfrost_translate_texture_type(template->target
);
1307 unsigned size
= panfrost_estimate_texture_size(
1308 template->u
.tex
.first_level
,
1309 template->u
.tex
.last_level
,
1310 template->u
.tex
.first_layer
,
1311 template->u
.tex
.last_layer
,
1312 type
, prsrc
->layout
);
1314 so
->bo
= panfrost_bo_create(screen
, size
, 0);
1316 panfrost_new_texture(
1318 texture
->width0
, texture
->height0
,
1319 texture
->depth0
, array_size
,
1321 type
, prsrc
->layout
,
1322 template->u
.tex
.first_level
,
1323 template->u
.tex
.last_level
,
1324 template->u
.tex
.first_layer
,
1325 template->u
.tex
.last_layer
,
1326 prsrc
->cubemap_stride
,
1327 panfrost_translate_swizzle_4(user_swizzle
),
1331 return (struct pipe_sampler_view
*) so
;
1335 panfrost_set_sampler_views(
1336 struct pipe_context
*pctx
,
1337 enum pipe_shader_type shader
,
1338 unsigned start_slot
, unsigned num_views
,
1339 struct pipe_sampler_view
**views
)
1341 struct panfrost_context
*ctx
= pan_context(pctx
);
1342 unsigned new_nr
= 0;
1345 assert(start_slot
== 0);
1347 for (i
= 0; i
< num_views
; ++i
) {
1350 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1354 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1355 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1358 ctx
->sampler_view_count
[shader
] = new_nr
;
1362 panfrost_sampler_view_destroy(
1363 struct pipe_context
*pctx
,
1364 struct pipe_sampler_view
*pview
)
1366 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1368 pipe_resource_reference(&pview
->texture
, NULL
);
1369 panfrost_bo_unreference(view
->bo
);
1374 panfrost_set_shader_buffers(
1375 struct pipe_context
*pctx
,
1376 enum pipe_shader_type shader
,
1377 unsigned start
, unsigned count
,
1378 const struct pipe_shader_buffer
*buffers
,
1379 unsigned writable_bitmask
)
1381 struct panfrost_context
*ctx
= pan_context(pctx
);
1383 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1384 buffers
, start
, count
);
1387 /* Hints that a framebuffer should use AFBC where possible */
1391 struct panfrost_screen
*screen
,
1392 const struct pipe_framebuffer_state
*fb
)
1394 /* AFBC implemenation incomplete; hide it */
1395 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
1397 /* Hint AFBC to the resources bound to each color buffer */
1399 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
1400 struct pipe_surface
*surf
= fb
->cbufs
[i
];
1401 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1402 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1405 /* Also hint it to the depth buffer */
1408 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
1409 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1414 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1415 const struct pipe_framebuffer_state
*fb
)
1417 struct panfrost_context
*ctx
= pan_context(pctx
);
1419 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
1420 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1422 panfrost_invalidate_frame(ctx
);
1426 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1427 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
1429 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
1433 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1436 struct panfrost_context
*ctx
= pan_context(pipe
);
1437 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
1438 ctx
->depth_stencil
= depth_stencil
;
1443 /* Alpha does not exist in the hardware (it's not in ES3), so it's
1444 * emulated in the fragment shader */
1446 if (depth_stencil
->alpha
.enabled
) {
1447 /* We need to trigger a new shader (maybe) */
1448 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1451 /* Bounds test not implemented */
1452 assert(!depth_stencil
->depth
.bounds_test
);
1456 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1462 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1463 unsigned sample_mask
)
1468 panfrost_set_clip_state(struct pipe_context
*pipe
,
1469 const struct pipe_clip_state
*clip
)
1471 //struct panfrost_context *panfrost = pan_context(pipe);
1475 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1476 unsigned start_slot
,
1477 unsigned num_viewports
,
1478 const struct pipe_viewport_state
*viewports
)
1480 struct panfrost_context
*ctx
= pan_context(pipe
);
1482 assert(start_slot
== 0);
1483 assert(num_viewports
== 1);
1485 ctx
->pipe_viewport
= *viewports
;
1489 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1490 unsigned start_slot
,
1491 unsigned num_scissors
,
1492 const struct pipe_scissor_state
*scissors
)
1494 struct panfrost_context
*ctx
= pan_context(pipe
);
1496 assert(start_slot
== 0);
1497 assert(num_scissors
== 1);
1499 ctx
->scissor
= *scissors
;
1503 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1504 const struct pipe_poly_stipple
*stipple
)
1506 //struct panfrost_context *panfrost = pan_context(pipe);
1510 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1513 struct panfrost_context
*ctx
= pan_context(pipe
);
1514 ctx
->active_queries
= enable
;
1518 panfrost_destroy(struct pipe_context
*pipe
)
1520 struct panfrost_context
*panfrost
= pan_context(pipe
);
1522 if (panfrost
->blitter
)
1523 util_blitter_destroy(panfrost
->blitter
);
1525 if (panfrost
->blitter_wallpaper
)
1526 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1528 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1529 u_upload_destroy(pipe
->stream_uploader
);
1534 static struct pipe_query
*
1535 panfrost_create_query(struct pipe_context
*pipe
,
1539 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1544 return (struct pipe_query
*) q
;
1548 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1550 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1553 panfrost_bo_unreference(query
->bo
);
1561 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1563 struct panfrost_context
*ctx
= pan_context(pipe
);
1564 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1566 switch (query
->type
) {
1567 case PIPE_QUERY_OCCLUSION_COUNTER
:
1568 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1569 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1570 /* Allocate a bo for the query results to be stored */
1572 query
->bo
= panfrost_bo_create(
1573 pan_screen(ctx
->base
.screen
),
1574 sizeof(unsigned), 0);
1577 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1578 *result
= 0; /* Default to 0 if nothing at all drawn. */
1579 ctx
->occlusion_query
= query
;
1582 /* Geometry statistics are computed in the driver. XXX: geom/tess
1585 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1586 query
->start
= ctx
->prims_generated
;
1588 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1589 query
->start
= ctx
->tf_prims_generated
;
1593 DBG("Skipping query %u\n", query
->type
);
1601 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1603 struct panfrost_context
*ctx
= pan_context(pipe
);
1604 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1606 switch (query
->type
) {
1607 case PIPE_QUERY_OCCLUSION_COUNTER
:
1608 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1609 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1610 ctx
->occlusion_query
= NULL
;
1612 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1613 query
->end
= ctx
->prims_generated
;
1615 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1616 query
->end
= ctx
->tf_prims_generated
;
1624 panfrost_get_query_result(struct pipe_context
*pipe
,
1625 struct pipe_query
*q
,
1627 union pipe_query_result
*vresult
)
1629 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1630 struct panfrost_context
*ctx
= pan_context(pipe
);
1633 switch (query
->type
) {
1634 case PIPE_QUERY_OCCLUSION_COUNTER
:
1635 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1636 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1638 panfrost_flush_all_batches(ctx
, true);
1640 /* Read back the query results */
1641 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1642 unsigned passed
= *result
;
1644 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1645 vresult
->u64
= passed
;
1647 vresult
->b
= !!passed
;
1652 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1653 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1654 panfrost_flush_all_batches(ctx
, true);
1655 vresult
->u64
= query
->end
- query
->start
;
1659 DBG("Skipped query get %u\n", query
->type
);
1666 static struct pipe_stream_output_target
*
1667 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1668 struct pipe_resource
*prsc
,
1669 unsigned buffer_offset
,
1670 unsigned buffer_size
)
1672 struct pipe_stream_output_target
*target
;
1674 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1679 pipe_reference_init(&target
->reference
, 1);
1680 pipe_resource_reference(&target
->buffer
, prsc
);
1682 target
->context
= pctx
;
1683 target
->buffer_offset
= buffer_offset
;
1684 target
->buffer_size
= buffer_size
;
1690 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1691 struct pipe_stream_output_target
*target
)
1693 pipe_resource_reference(&target
->buffer
, NULL
);
1694 ralloc_free(target
);
1698 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1699 unsigned num_targets
,
1700 struct pipe_stream_output_target
**targets
,
1701 const unsigned *offsets
)
1703 struct panfrost_context
*ctx
= pan_context(pctx
);
1704 struct panfrost_streamout
*so
= &ctx
->streamout
;
1706 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1708 for (unsigned i
= 0; i
< num_targets
; i
++) {
1709 if (offsets
[i
] != -1)
1710 so
->offsets
[i
] = offsets
[i
];
1712 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1715 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1716 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1718 so
->num_targets
= num_targets
;
1721 struct pipe_context
*
1722 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1724 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1725 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1727 gallium
->screen
= screen
;
1729 gallium
->destroy
= panfrost_destroy
;
1731 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1733 gallium
->flush
= panfrost_flush
;
1734 gallium
->clear
= panfrost_clear
;
1735 gallium
->draw_vbo
= panfrost_draw_vbo
;
1737 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1738 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1739 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1741 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1743 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1744 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1745 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1747 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1748 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1749 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1751 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1752 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1753 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1755 gallium
->create_fs_state
= panfrost_create_fs_state
;
1756 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1757 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1759 gallium
->create_vs_state
= panfrost_create_vs_state
;
1760 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1761 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1763 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1764 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1765 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1767 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1768 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1769 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1771 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1773 gallium
->set_clip_state
= panfrost_set_clip_state
;
1774 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1775 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1776 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1777 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1779 gallium
->create_query
= panfrost_create_query
;
1780 gallium
->destroy_query
= panfrost_destroy_query
;
1781 gallium
->begin_query
= panfrost_begin_query
;
1782 gallium
->end_query
= panfrost_end_query
;
1783 gallium
->get_query_result
= panfrost_get_query_result
;
1785 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1786 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1787 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1789 panfrost_resource_context_init(gallium
);
1790 panfrost_blend_context_init(gallium
);
1791 panfrost_compute_context_init(gallium
);
1794 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1795 gallium
->const_uploader
= gallium
->stream_uploader
;
1796 assert(gallium
->stream_uploader
);
1798 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
1799 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
1801 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1803 ctx
->blitter
= util_blitter_create(gallium
);
1804 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1806 assert(ctx
->blitter
);
1807 assert(ctx
->blitter_wallpaper
);
1809 /* Prepare for render! */
1811 panfrost_batch_init(ctx
);
1812 panfrost_emit_vertex_payload(ctx
);
1813 panfrost_invalidate_frame(ctx
);