2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
55 #include "pandecode/decode.h"
57 struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
61 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
62 struct midgard_tiler_descriptor t
= {0};
63 unsigned height
= batch
->key
.height
;
64 unsigned width
= batch
->key
.width
;
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
, hierarchy
);
74 t
.polygon_list_size
= panfrost_tiler_full_size(
75 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 struct panfrost_bo
*tiler_heap
;
82 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
83 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
88 /* Allow the entire tiler heap */
89 t
.heap_start
= tiler_heap
->gpu
;
90 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
92 struct panfrost_bo
*tiler_dummy
;
94 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
95 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
97 /* The tiler is disabled, so don't allow the tiler heap */
98 t
.heap_start
= tiler_dummy
->gpu
;
99 t
.heap_end
= t
.heap_start
;
101 /* Use a dummy polygon list */
102 t
.polygon_list
= tiler_dummy
->gpu
;
104 /* Disable the tiler */
106 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
108 t
.hierarchy_mask
= MALI_TILER_USER
;
109 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
111 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
112 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
113 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
117 t
.polygon_list_body
=
118 t
.polygon_list
+ header_size
;
125 struct pipe_context
*pipe
,
127 const union pipe_color_union
*color
,
128 double depth
, unsigned stencil
)
130 struct panfrost_context
*ctx
= pan_context(pipe
);
132 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
133 * the existing batch targeting this FBO has draws. We could probably
134 * avoid that by replacing plain clears by quad-draws with a specific
135 * color/depth/stencil value, thus avoiding the generation of extra
138 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
140 panfrost_batch_add_fbo_bos(batch
);
141 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
144 /* TODO: Bifrost requires just a mali_shared_memory, without the rest of the
148 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
150 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
151 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
153 /* If we haven't, reserve space for the framebuffer */
155 if (!batch
->framebuffer
.gpu
) {
156 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
157 sizeof(struct mali_single_framebuffer
) :
158 sizeof(struct mali_framebuffer
);
160 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
162 /* Tag the pointer */
163 if (!(screen
->quirks
& MIDGARD_SFBD
))
164 batch
->framebuffer
.gpu
|= MALI_MFBD
;
167 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
168 ctx
->payloads
[i
].postfix
.shared_memory
= batch
->framebuffer
.gpu
;
171 /* Reset per-frame context, called on context initialisation as well as after
172 * flushing a frame */
175 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
177 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
178 ctx
->payloads
[i
].postfix
.shared_memory
= 0;
180 /* TODO: When does this need to be handled? */
181 ctx
->active_queries
= true;
184 /* In practice, every field of these payloads should be configurable
185 * arbitrarily, which means these functions are basically catch-all's for
186 * as-of-yet unwavering unknowns */
189 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
191 /* 0x2 bit clear on 32-bit T6XX */
193 struct midgard_payload_vertex_tiler payload
= {
194 .gl_enables
= 0x4 | 0x2,
197 /* Vertex and compute are closely coupled, so share a payload */
199 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
200 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
204 translate_tex_wrap(enum pipe_tex_wrap w
)
207 case PIPE_TEX_WRAP_REPEAT
:
208 return MALI_WRAP_REPEAT
;
210 case PIPE_TEX_WRAP_CLAMP
:
211 return MALI_WRAP_CLAMP
;
213 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
214 return MALI_WRAP_CLAMP_TO_EDGE
;
216 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
217 return MALI_WRAP_CLAMP_TO_BORDER
;
219 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
220 return MALI_WRAP_MIRRORED_REPEAT
;
222 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
223 return MALI_WRAP_MIRRORED_CLAMP
;
225 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
226 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
228 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
229 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
232 unreachable("Invalid wrap");
237 panfrost_translate_compare_func(enum pipe_compare_func in
)
240 case PIPE_FUNC_NEVER
:
241 return MALI_FUNC_NEVER
;
244 return MALI_FUNC_LESS
;
246 case PIPE_FUNC_EQUAL
:
247 return MALI_FUNC_EQUAL
;
249 case PIPE_FUNC_LEQUAL
:
250 return MALI_FUNC_LEQUAL
;
252 case PIPE_FUNC_GREATER
:
253 return MALI_FUNC_GREATER
;
255 case PIPE_FUNC_NOTEQUAL
:
256 return MALI_FUNC_NOTEQUAL
;
258 case PIPE_FUNC_GEQUAL
:
259 return MALI_FUNC_GEQUAL
;
261 case PIPE_FUNC_ALWAYS
:
262 return MALI_FUNC_ALWAYS
;
265 unreachable("Invalid func");
270 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
273 case PIPE_STENCIL_OP_KEEP
:
274 return MALI_STENCIL_KEEP
;
276 case PIPE_STENCIL_OP_ZERO
:
277 return MALI_STENCIL_ZERO
;
279 case PIPE_STENCIL_OP_REPLACE
:
280 return MALI_STENCIL_REPLACE
;
282 case PIPE_STENCIL_OP_INCR
:
283 return MALI_STENCIL_INCR
;
285 case PIPE_STENCIL_OP_DECR
:
286 return MALI_STENCIL_DECR
;
288 case PIPE_STENCIL_OP_INCR_WRAP
:
289 return MALI_STENCIL_INCR_WRAP
;
291 case PIPE_STENCIL_OP_DECR_WRAP
:
292 return MALI_STENCIL_DECR_WRAP
;
294 case PIPE_STENCIL_OP_INVERT
:
295 return MALI_STENCIL_INVERT
;
298 unreachable("Invalid stencil op");
303 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
305 out
->ref
= 0; /* Gallium gets it from elsewhere */
307 out
->mask
= in
->valuemask
;
308 out
->func
= panfrost_translate_compare_func(in
->func
);
309 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
310 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
311 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
315 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
317 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
318 struct mali_shader_meta shader
= {
319 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
321 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
322 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
325 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
326 * required (independent of 32-bit/64-bit descriptors), or why it's not
327 * used on later GPU revisions. Otherwise, all shader jobs fault on
328 * these earlier chips (perhaps this is a chicken bit of some kind).
329 * More investigation is needed. */
331 if (screen
->quirks
& MIDGARD_SFBD
)
332 shader
.unknown2_4
|= 0x10;
334 struct pipe_stencil_state default_stencil
= {
336 .func
= PIPE_FUNC_ALWAYS
,
337 .fail_op
= MALI_STENCIL_KEEP
,
338 .zfail_op
= MALI_STENCIL_KEEP
,
339 .zpass_op
= MALI_STENCIL_KEEP
,
344 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
345 shader
.stencil_mask_front
= default_stencil
.writemask
;
347 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
348 shader
.stencil_mask_back
= default_stencil
.writemask
;
350 if (default_stencil
.enabled
)
351 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
353 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
357 panfrost_writes_point_size(struct panfrost_context
*ctx
)
359 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
360 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
362 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
365 /* Stage the attribute descriptors so we can adjust src_offset
366 * to let BOs align nicely */
369 panfrost_stage_attributes(struct panfrost_context
*ctx
)
371 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
372 struct panfrost_vertex_state
*so
= ctx
->vertex
;
374 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
375 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
376 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
378 /* Copy as-is for the first pass */
379 memcpy(target
, so
->hw
, sz
);
381 /* Fixup offsets for the second pass. Recall that the hardware
382 * calculates attribute addresses as:
384 * addr = base + (stride * vtx) + src_offset;
386 * However, on Mali, base must be aligned to 64-bytes, so we
389 * base' = base & ~63 = base - (base & 63)
391 * To compensate when using base' (see emit_vertex_data), we have
392 * to adjust src_offset by the masked off piece:
394 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
395 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
396 * = base + (stride * vtx) + src_offset
402 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
404 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
405 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
406 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
407 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
408 mali_ptr addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
410 /* Adjust by the masked off bits of the offset. Make sure we
411 * read src_offset from so->hw (which is not GPU visible)
412 * rather than target (which is) due to caching effects */
414 unsigned src_offset
= so
->hw
[i
].src_offset
;
415 src_offset
+= (addr
& 63);
417 /* Also, somewhat obscurely per-instance data needs to be
418 * offset in response to a delayed start in an indexed draw */
420 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
421 src_offset
-= buf
->stride
* start
;
423 target
[i
].src_offset
= src_offset
;
426 /* Let's also include vertex builtins */
428 struct mali_attr_meta builtin
= {
429 .format
= MALI_R32UI
,
430 .swizzle
= panfrost_get_default_swizzle(1)
433 /* See mali_attr_meta specification for the magic number */
435 builtin
.index
= so
->vertexid_index
;
436 memcpy(&target
[PAN_VERTEX_ID
], &builtin
, 4);
438 builtin
.index
= so
->vertexid_index
+ 1;
439 memcpy(&target
[PAN_INSTANCE_ID
], &builtin
, 4);
441 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
445 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
447 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
448 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
450 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
453 if (ctx
->sampler_count
[t
]) {
454 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
456 struct panfrost_transfer transfer
=
457 panfrost_allocate_transient(batch
, transfer_size
);
459 struct mali_sampler_descriptor
*desc
=
460 (struct mali_sampler_descriptor
*) transfer
.cpu
;
462 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
463 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
465 upload
= transfer
.gpu
;
468 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
474 struct panfrost_context
*ctx
,
475 enum pipe_shader_type st
,
476 struct panfrost_sampler_view
*view
)
481 struct pipe_sampler_view
*pview
= &view
->base
;
482 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
484 /* Add the BO to the job so it's retained until the job is done. */
485 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
487 panfrost_batch_add_bo(batch
, rsrc
->bo
,
488 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
489 panfrost_bo_access_for_stage(st
));
491 panfrost_batch_add_bo(batch
, view
->bo
,
492 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
493 panfrost_bo_access_for_stage(st
));
495 return view
->bo
->gpu
;
499 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
501 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
503 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
504 mali_ptr trampoline
= 0;
506 if (ctx
->sampler_view_count
[t
]) {
507 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
509 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
511 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
513 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
516 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
520 struct sysval_uniform
{
529 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
530 struct sysval_uniform
*uniform
)
532 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
534 uniform
->f
[0] = vp
->scale
[0];
535 uniform
->f
[1] = vp
->scale
[1];
536 uniform
->f
[2] = vp
->scale
[2];
539 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
540 struct sysval_uniform
*uniform
)
542 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
544 uniform
->f
[0] = vp
->translate
[0];
545 uniform
->f
[1] = vp
->translate
[1];
546 uniform
->f
[2] = vp
->translate
[2];
549 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
550 enum pipe_shader_type st
,
551 unsigned int sysvalid
,
552 struct sysval_uniform
*uniform
)
554 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
555 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
556 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
557 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
560 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
563 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
564 tex
->u
.tex
.first_level
);
567 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
568 tex
->u
.tex
.first_level
);
571 uniform
->i
[dim
] = tex
->texture
->array_size
;
574 static void panfrost_upload_ssbo_sysval(
575 struct panfrost_context
*ctx
,
576 enum pipe_shader_type st
,
578 struct sysval_uniform
*uniform
)
580 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
581 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
583 /* Compute address */
584 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
585 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
587 panfrost_batch_add_bo(batch
, bo
,
588 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
589 panfrost_bo_access_for_stage(st
));
591 /* Upload address and size as sysval */
592 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
593 uniform
->u
[2] = sb
.buffer_size
;
597 panfrost_upload_sampler_sysval(
598 struct panfrost_context
*ctx
,
599 enum pipe_shader_type st
,
600 unsigned sampler_index
,
601 struct sysval_uniform
*uniform
)
603 struct pipe_sampler_state
*sampl
=
604 &ctx
->samplers
[st
][sampler_index
]->base
;
606 uniform
->f
[0] = sampl
->min_lod
;
607 uniform
->f
[1] = sampl
->max_lod
;
608 uniform
->f
[2] = sampl
->lod_bias
;
610 /* Even without any errata, Midgard represents "no mipmapping" as
611 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
612 * panfrost_create_sampler_state which also explains our choice of
613 * epsilon value (again to keep behaviour consistent) */
615 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
616 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
619 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
620 struct sysval_uniform
*uniform
)
622 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
623 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
624 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
627 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
628 struct panfrost_shader_state
*ss
,
629 enum pipe_shader_type st
)
631 struct sysval_uniform
*uniforms
= (void *)buf
;
633 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
634 int sysval
= ss
->sysval
[i
];
636 switch (PAN_SYSVAL_TYPE(sysval
)) {
637 case PAN_SYSVAL_VIEWPORT_SCALE
:
638 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
640 case PAN_SYSVAL_VIEWPORT_OFFSET
:
641 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
643 case PAN_SYSVAL_TEXTURE_SIZE
:
644 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
647 case PAN_SYSVAL_SSBO
:
648 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
651 case PAN_SYSVAL_NUM_WORK_GROUPS
:
652 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
654 case PAN_SYSVAL_SAMPLER
:
655 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
665 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
667 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
668 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
671 return rsrc
->bo
->cpu
;
672 else if (cb
->user_buffer
)
673 return cb
->user_buffer
;
675 unreachable("No constant buffer");
679 panfrost_map_constant_buffer_gpu(
680 struct panfrost_context
*ctx
,
681 enum pipe_shader_type st
,
682 struct panfrost_constant_buffer
*buf
,
685 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
686 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
687 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
690 panfrost_batch_add_bo(batch
, rsrc
->bo
,
691 PAN_BO_ACCESS_SHARED
|
693 panfrost_bo_access_for_stage(st
));
695 /* Alignment gauranteed by PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
696 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
697 } else if (cb
->user_buffer
) {
698 return panfrost_upload_transient(batch
, cb
->user_buffer
+ cb
->buffer_offset
, cb
->buffer_size
);
700 unreachable("No constant buffer");
704 /* Compute number of UBOs active (more specifically, compute the highest UBO
705 * number addressable -- if there are gaps, include them in the count anyway).
706 * We always include UBO #0 in the count, since we *need* uniforms enabled for
710 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
712 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
713 return 32 - __builtin_clz(mask
);
716 /* Fixes up a shader state with current state */
719 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
720 enum pipe_shader_type stage
)
722 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, stage
);
725 ctx
->payloads
[stage
].postfix
.shader
= 0;
729 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
730 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
732 ss
->tripipe
->midgard1
.flags_lo
= 0x220;
734 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
735 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
737 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
739 /* Add the shader BO to the batch. */
740 panfrost_batch_add_bo(batch
, ss
->bo
,
741 PAN_BO_ACCESS_PRIVATE
|
743 panfrost_bo_access_for_stage(stage
));
745 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
747 sizeof(struct mali_shader_meta
));
750 /* Go through dirty flags and actualise them in the cmdstream. */
753 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
755 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
756 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
758 panfrost_batch_add_fbo_bos(batch
);
759 panfrost_attach_vt_framebuffer(ctx
);
761 if (with_vertex_data
) {
762 panfrost_emit_vertex_data(batch
);
764 /* Varyings emitted for -all- geometry */
765 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
766 panfrost_emit_varying_descriptor(ctx
, total_count
);
770 if (ctx
->rasterizer
) {
771 bool msaa
= ctx
->rasterizer
->base
.multisample
;
772 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
774 /* TODO: Sample size */
775 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
776 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
779 panfrost_batch_set_requirements(batch
);
781 if (ctx
->occlusion_query
) {
782 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
783 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
786 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
787 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
789 if (ctx
->shader
[PIPE_SHADER_VERTEX
] && ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
790 /* Check if we need to link the gl_PointSize varying */
791 if (!panfrost_writes_point_size(ctx
)) {
792 /* If the size is constant, write it out. Otherwise,
793 * don't touch primitive_size (since we would clobber
794 * the pointer there) */
796 bool points
= ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
798 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= points
?
799 ctx
->rasterizer
->base
.point_size
:
800 ctx
->rasterizer
->base
.line_width
;
804 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
805 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
807 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
809 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
812 COPY(attribute_count
);
816 COPY(midgard1
.uniform_count
);
817 COPY(midgard1
.uniform_buffer_count
);
818 COPY(midgard1
.work_count
);
819 COPY(midgard1
.flags_lo
);
820 COPY(midgard1
.flags_hi
);
824 /* Get blending setup */
825 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
827 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
828 unsigned shader_offset
= 0;
829 struct panfrost_bo
*shader_bo
= NULL
;
831 for (unsigned c
= 0; c
< rt_count
; ++c
) {
832 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
835 /* If there is a blend shader, work registers are shared. XXX: opt */
837 for (unsigned c
= 0; c
< rt_count
; ++c
) {
838 if (blend
[c
].is_shader
)
839 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
842 /* Depending on whether it's legal to in the given shader, we
843 * try to enable early-z testing (or forward-pixel kill?) */
845 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_EARLY_Z
,
846 !variant
->can_discard
&& !variant
->writes_depth
);
848 /* Add the writes Z/S flags if needed. */
849 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
,
850 MALI_WRITES_Z
, variant
->writes_depth
);
851 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_hi
,
852 MALI_WRITES_S
, variant
->writes_stencil
);
854 /* Any time texturing is used, derivatives are implicitly
855 * calculated, so we need to enable helper invocations */
857 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
859 /* Assign the stencil refs late */
861 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
862 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
863 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
865 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
866 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
868 /* CAN_DISCARD should be set if the fragment shader possibly
869 * contains a 'discard' instruction. It is likely this is
870 * related to optimizations related to forward-pixel kill, as
871 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
872 * thing?" by Peter Harris
875 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
876 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, 0x400, variant
->can_discard
);
878 /* Even on MFBD, the shader descriptor gets blend shaders. It's
879 * *also* copied to the blend_meta appended (by convention),
880 * but this is the field actually read by the hardware. (Or
881 * maybe both are read...?). Specify the last RTi with a blend
884 ctx
->fragment_shader_core
.blend
.shader
= 0;
886 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
887 if (blend
[rt
].is_shader
) {
888 ctx
->fragment_shader_core
.blend
.shader
=
889 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
894 if (screen
->quirks
& MIDGARD_SFBD
) {
895 /* When only a single render target platform is used, the blend
896 * information is inside the shader meta itself. We
897 * additionally need to signal CAN_DISCARD for nontrivial blend
898 * modes (so we're able to read back the destination buffer) */
900 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
902 if (!blend
[0].is_shader
) {
903 ctx
->fragment_shader_core
.blend
.equation
=
904 *blend
[0].equation
.equation
;
905 ctx
->fragment_shader_core
.blend
.constant
=
906 blend
[0].equation
.constant
;
909 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
912 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
913 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
914 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
916 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
918 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
919 /* Additional blend descriptor tacked on for jobs using MFBD */
921 struct midgard_blend_rt rts
[4];
923 for (unsigned i
= 0; i
< rt_count
; ++i
) {
924 rts
[i
].flags
= 0x200;
927 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
928 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
929 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
931 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
932 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
933 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
934 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
936 if (blend
[i
].is_shader
) {
937 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
939 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
940 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
944 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
948 /* We stage to transient, so always dirty.. */
950 panfrost_stage_attributes(ctx
);
952 panfrost_upload_sampler_descriptors(ctx
);
953 panfrost_upload_texture_descriptors(ctx
);
955 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
957 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
958 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
963 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
965 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
967 /* Uniforms are implicitly UBO #0 */
968 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
970 /* Allocate room for the sysval and the uniforms */
971 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
972 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
973 size_t size
= sys_size
+ uniform_size
;
974 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
976 /* Upload sysvals requested by the shader */
977 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
979 /* Upload uniforms */
980 if (has_uniforms
&& uniform_size
) {
981 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
982 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
986 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
988 struct mali_vertex_tiler_postfix
*postfix
=
989 &ctx
->payloads
[i
].postfix
;
991 /* Next up, attach UBOs. UBO #0 is the uniforms we just
994 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
995 assert(ubo_count
>= 1);
997 size_t sz
= sizeof(uint64_t) * ubo_count
;
998 uint64_t ubos
[PAN_MAX_CONST_BUFFERS
];
1000 /* Upload uniforms as a UBO */
1001 ubos
[0] = MALI_MAKE_UBO(2 + uniform_count
, transfer
.gpu
);
1003 /* The rest are honest-to-goodness UBOs */
1005 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1006 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1008 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1009 bool empty
= usz
== 0;
1011 if (!enabled
|| empty
) {
1012 /* Stub out disabled UBOs to catch accesses */
1013 ubos
[ubo
] = MALI_MAKE_UBO(0, 0xDEAD0000);
1017 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1019 unsigned bytes_per_field
= 16;
1020 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1021 ubos
[ubo
] = MALI_MAKE_UBO(aligned
/ bytes_per_field
, gpu
);
1024 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1025 postfix
->uniforms
= transfer
.gpu
;
1026 postfix
->uniform_buffers
= ubufs
;
1028 buf
->dirty_mask
= 0;
1031 /* TODO: Upload the viewport somewhere more appropriate */
1033 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1034 * (somewhat) asymmetric ints. */
1035 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1037 struct mali_viewport view
= {
1038 /* By default, do no viewport clipping, i.e. clip to (-inf,
1039 * inf) in each direction. Clipping to the viewport in theory
1040 * should work, but in practice causes issues when we're not
1041 * explicitly trying to scissor */
1043 .clip_minx
= -INFINITY
,
1044 .clip_miny
= -INFINITY
,
1045 .clip_maxx
= INFINITY
,
1046 .clip_maxy
= INFINITY
,
1049 /* Always scissor to the viewport by default. */
1050 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1051 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1053 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1054 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1056 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1057 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1059 /* Apply the scissor test */
1061 unsigned minx
, miny
, maxx
, maxy
;
1063 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1064 minx
= MAX2(ss
->minx
, vp_minx
);
1065 miny
= MAX2(ss
->miny
, vp_miny
);
1066 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1067 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1075 /* Hardware needs the min/max to be strictly ordered, so flip if we
1076 * need to. The viewport transformation in the vertex shader will
1077 * handle the negatives if we don't */
1080 unsigned temp
= miny
;
1086 unsigned temp
= minx
;
1097 /* Clamp to the framebuffer size as a last check */
1099 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1100 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1102 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1103 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1105 /* Update the job, unless we're doing wallpapering (whose lack of
1106 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1107 * just... be faster :) */
1109 if (!ctx
->wallpaper_batch
)
1110 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1114 view
.viewport0
[0] = minx
;
1115 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1117 view
.viewport0
[1] = miny
;
1118 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1120 view
.clip_minz
= minz
;
1121 view
.clip_maxz
= maxz
;
1123 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1124 panfrost_upload_transient(batch
,
1126 sizeof(struct mali_viewport
));
1129 /* Corresponds to exactly one draw, but does not submit anything */
1132 panfrost_queue_draw(struct panfrost_context
*ctx
)
1134 /* Handle dirty flags now */
1135 panfrost_emit_for_draw(ctx
, true);
1137 /* If rasterizer discard is enable, only submit the vertex */
1139 bool rasterizer_discard
= ctx
->rasterizer
1140 && ctx
->rasterizer
->base
.rasterizer_discard
;
1143 struct midgard_payload_vertex_tiler
*vertex_payload
= &ctx
->payloads
[PIPE_SHADER_VERTEX
];
1144 struct midgard_payload_vertex_tiler
*tiler_payload
= &ctx
->payloads
[PIPE_SHADER_FRAGMENT
];
1146 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1147 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->tiler_dep
;
1150 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
1151 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, batch
->job_index
+ 2, tiler_payload
, sizeof(*tiler_payload
), true);
1152 panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), true);
1154 unsigned vertex
= panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), false);
1156 if (!rasterizer_discard
)
1157 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, vertex
, tiler_payload
, sizeof(*tiler_payload
), false);
1160 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1161 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, i
);
1166 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1170 /* The entire frame is in memory -- send it off to the kernel! */
1174 struct pipe_context
*pipe
,
1175 struct pipe_fence_handle
**fence
,
1178 struct panfrost_context
*ctx
= pan_context(pipe
);
1179 struct util_dynarray fences
;
1181 /* We must collect the fences before the flush is done, otherwise we'll
1182 * lose track of them.
1185 util_dynarray_init(&fences
, NULL
);
1186 hash_table_foreach(ctx
->batches
, hentry
) {
1187 struct panfrost_batch
*batch
= hentry
->data
;
1189 panfrost_batch_fence_reference(batch
->out_sync
);
1190 util_dynarray_append(&fences
,
1191 struct panfrost_batch_fence
*,
1196 /* Submit all pending jobs */
1197 panfrost_flush_all_batches(ctx
, false);
1200 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1201 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1202 *fence
= (struct pipe_fence_handle
*)f
;
1204 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1205 panfrost_batch_fence_unreference(*fence
);
1207 util_dynarray_fini(&fences
);
1210 if (pan_debug
& PAN_DBG_TRACE
)
1211 pandecode_next_frame();
1214 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1217 g2m_draw_mode(enum pipe_prim_type mode
)
1220 DEFINE_CASE(POINTS
);
1222 DEFINE_CASE(LINE_LOOP
);
1223 DEFINE_CASE(LINE_STRIP
);
1224 DEFINE_CASE(TRIANGLES
);
1225 DEFINE_CASE(TRIANGLE_STRIP
);
1226 DEFINE_CASE(TRIANGLE_FAN
);
1228 DEFINE_CASE(QUAD_STRIP
);
1229 DEFINE_CASE(POLYGON
);
1232 unreachable("Invalid draw mode");
1239 panfrost_translate_index_size(unsigned size
)
1243 return MALI_DRAW_INDEXED_UINT8
;
1246 return MALI_DRAW_INDEXED_UINT16
;
1249 return MALI_DRAW_INDEXED_UINT32
;
1252 unreachable("Invalid index size");
1256 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1257 * good for the duration of the draw (transient), could last longer. Also get
1258 * the bounds on the index buffer for the range accessed by the draw. We do
1259 * these operations together because there are natural optimizations which
1260 * require them to be together. */
1263 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
, unsigned *min_index
, unsigned *max_index
)
1265 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1267 off_t offset
= info
->start
* info
->index_size
;
1268 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1271 bool needs_indices
= true;
1273 if (info
->max_index
!= ~0u) {
1274 *min_index
= info
->min_index
;
1275 *max_index
= info
->max_index
;
1276 needs_indices
= false;
1279 if (!info
->has_user_indices
) {
1280 /* Only resources can be directly mapped */
1281 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1282 PAN_BO_ACCESS_SHARED
|
1283 PAN_BO_ACCESS_READ
|
1284 PAN_BO_ACCESS_VERTEX_TILER
);
1285 out
= rsrc
->bo
->gpu
+ offset
;
1287 /* Check the cache */
1288 needs_indices
= !panfrost_minmax_cache_get(rsrc
->index_cache
, info
->start
, info
->count
,
1289 min_index
, max_index
);
1291 /* Otherwise, we need to upload to transient memory */
1292 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1293 out
= panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1296 if (needs_indices
) {
1298 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
1300 if (!info
->has_user_indices
) {
1301 panfrost_minmax_cache_add(rsrc
->index_cache
, info
->start
, info
->count
,
1302 *min_index
, *max_index
);
1311 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1313 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1315 /* Check if we're scissoring at all */
1317 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1320 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1323 /* Count generated primitives (when there is no geom/tess shaders) for
1324 * transform feedback */
1327 panfrost_statistics_record(
1328 struct panfrost_context
*ctx
,
1329 const struct pipe_draw_info
*info
)
1331 if (!ctx
->active_queries
)
1334 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1335 ctx
->prims_generated
+= prims
;
1337 if (!ctx
->streamout
.num_targets
)
1340 ctx
->tf_prims_generated
+= prims
;
1345 struct pipe_context
*pipe
,
1346 const struct pipe_draw_info
*info
)
1348 struct panfrost_context
*ctx
= pan_context(pipe
);
1350 /* First of all, check the scissor to see if anything is drawn at all.
1351 * If it's not, we drop the draw (mostly a conformance issue;
1352 * well-behaved apps shouldn't hit this) */
1354 if (panfrost_scissor_culls_everything(ctx
))
1357 int mode
= info
->mode
;
1359 /* Fallback unsupported restart index */
1360 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1362 if (info
->primitive_restart
&& info
->index_size
1363 && info
->restart_index
!= primitive_index
) {
1364 util_draw_vbo_without_prim_restart(pipe
, info
);
1368 /* Fallback for unsupported modes */
1370 assert(ctx
->rasterizer
!= NULL
);
1372 if (!(ctx
->draw_modes
& (1 << mode
))) {
1373 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1374 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1376 if (info
->count
< 4) {
1377 /* Degenerate case? */
1381 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1382 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1387 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1388 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1390 /* Now that we have a guaranteed terminating path, find the job.
1391 * Assignment commented out to prevent unused warning */
1393 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1395 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1397 /* Take into account a negative bias */
1398 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1399 ctx
->instance_count
= info
->instance_count
;
1400 ctx
->active_prim
= info
->mode
;
1402 /* For non-indexed draws, they're the same */
1403 unsigned vertex_count
= ctx
->vertex_count
;
1405 unsigned draw_flags
= 0;
1407 /* The draw flags interpret how primitive size is interpreted */
1409 if (panfrost_writes_point_size(ctx
))
1410 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1412 if (info
->primitive_restart
)
1413 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1415 /* These doesn't make much sense */
1417 draw_flags
|= 0x3000;
1419 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1420 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1422 panfrost_statistics_record(ctx
, info
);
1424 if (info
->index_size
) {
1425 unsigned min_index
= 0, max_index
= 0;
1426 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
=
1427 panfrost_get_index_buffer_bounded(ctx
, info
, &min_index
, &max_index
);
1429 /* Use the corresponding values */
1430 vertex_count
= max_index
- min_index
+ 1;
1431 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1432 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1434 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1435 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1437 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1439 /* Index count == vertex count, if no indexing is applied, as
1440 * if it is internally indexed in the expected order */
1442 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1443 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1445 /* Reverse index state */
1446 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
1449 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1450 * vertex_count, 1) */
1452 panfrost_pack_work_groups_fused(
1453 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1454 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1455 1, vertex_count
, info
->instance_count
,
1458 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1460 /* Encode the padded vertex count */
1462 if (info
->instance_count
> 1) {
1463 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1465 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1466 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1468 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1469 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1471 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1472 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1474 ctx
->padded_count
= vertex_count
;
1476 /* Reset instancing state */
1477 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1478 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1479 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1480 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1483 /* Fire off the draw itself */
1484 panfrost_queue_draw(ctx
);
1486 /* Increment transform feedback offsets */
1488 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1489 unsigned output_count
= u_stream_outputs_for_vertices(
1490 ctx
->active_prim
, ctx
->vertex_count
);
1492 ctx
->streamout
.offsets
[i
] += output_count
;
1499 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1505 panfrost_create_rasterizer_state(
1506 struct pipe_context
*pctx
,
1507 const struct pipe_rasterizer_state
*cso
)
1509 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1513 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1514 so
->tiler_gl_enables
= 0x7;
1517 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1519 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1520 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1522 if (cso
->cull_face
& PIPE_FACE_BACK
)
1523 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1529 panfrost_bind_rasterizer_state(
1530 struct pipe_context
*pctx
,
1533 struct panfrost_context
*ctx
= pan_context(pctx
);
1535 ctx
->rasterizer
= hwcso
;
1540 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1541 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1543 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1544 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1546 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1548 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1549 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1551 /* Point sprites are emulated */
1553 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
1555 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1556 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1560 panfrost_create_vertex_elements_state(
1561 struct pipe_context
*pctx
,
1562 unsigned num_elements
,
1563 const struct pipe_vertex_element
*elements
)
1565 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1567 so
->num_elements
= num_elements
;
1568 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1570 for (int i
= 0; i
< num_elements
; ++i
) {
1571 so
->hw
[i
].index
= i
;
1573 enum pipe_format fmt
= elements
[i
].src_format
;
1574 const struct util_format_description
*desc
= util_format_description(fmt
);
1575 so
->hw
[i
].unknown1
= 0x2;
1576 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1578 so
->hw
[i
].format
= panfrost_find_format(desc
);
1580 /* The field itself should probably be shifted over */
1581 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1588 panfrost_bind_vertex_elements_state(
1589 struct pipe_context
*pctx
,
1592 struct panfrost_context
*ctx
= pan_context(pctx
);
1593 ctx
->vertex
= hwcso
;
1597 panfrost_create_shader_state(
1598 struct pipe_context
*pctx
,
1599 const struct pipe_shader_state
*cso
,
1600 enum pipe_shader_type stage
)
1602 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1605 /* Token deep copy to prevent memory corruption */
1607 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1608 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1610 /* Precompile for shader-db if we need to */
1611 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1612 struct panfrost_context
*ctx
= pan_context(pctx
);
1614 struct mali_shader_meta meta
;
1615 struct panfrost_shader_state state
;
1616 uint64_t outputs_written
;
1618 panfrost_shader_compile(ctx
, &meta
,
1621 tgsi_processor_to_shader_stage(stage
), &state
,
1629 panfrost_delete_shader_state(
1630 struct pipe_context
*pctx
,
1633 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1635 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1636 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1639 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1640 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1641 panfrost_bo_unreference(shader_state
->bo
);
1642 shader_state
->bo
= NULL
;
1644 free(cso
->variants
);
1650 panfrost_create_sampler_state(
1651 struct pipe_context
*pctx
,
1652 const struct pipe_sampler_state
*cso
)
1654 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1657 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1659 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1660 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1661 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1663 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1664 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1665 unsigned mip_filter
= mip_linear
?
1666 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1667 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1669 struct mali_sampler_descriptor sampler_descriptor
= {
1670 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1671 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1672 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1673 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1674 .compare_func
= panfrost_flip_compare_func(
1675 panfrost_translate_compare_func(
1676 cso
->compare_func
)),
1678 cso
->border_color
.f
[0],
1679 cso
->border_color
.f
[1],
1680 cso
->border_color
.f
[2],
1681 cso
->border_color
.f
[3]
1683 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1684 .max_lod
= FIXED_16(cso
->max_lod
, false),
1685 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1686 .seamless_cube_map
= cso
->seamless_cube_map
,
1689 /* If necessary, we disable mipmapping in the sampler descriptor by
1690 * clamping the LOD as tight as possible (from 0 to epsilon,
1691 * essentially -- remember these are fixed point numbers, so
1694 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
1695 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1697 /* Enforce that there is something in the middle by adding epsilon*/
1699 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1700 sampler_descriptor
.max_lod
++;
1703 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1706 so
->hw
= sampler_descriptor
;
1712 panfrost_bind_sampler_states(
1713 struct pipe_context
*pctx
,
1714 enum pipe_shader_type shader
,
1715 unsigned start_slot
, unsigned num_sampler
,
1718 assert(start_slot
== 0);
1720 struct panfrost_context
*ctx
= pan_context(pctx
);
1722 /* XXX: Should upload, not just copy? */
1723 ctx
->sampler_count
[shader
] = num_sampler
;
1724 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1728 panfrost_variant_matches(
1729 struct panfrost_context
*ctx
,
1730 struct panfrost_shader_state
*variant
,
1731 enum pipe_shader_type type
)
1733 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1734 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1736 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1738 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1739 /* Make sure enable state is at least the same */
1740 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1744 /* Check that the contents of the test are the same */
1745 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1746 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1748 if (!(same_func
&& same_ref
)) {
1753 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1754 variant
->point_sprite_mask
)) {
1755 /* Ensure the same varyings are turned to point sprites */
1756 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1759 /* Ensure the orientation is correct */
1761 rasterizer
->sprite_coord_mode
==
1762 PIPE_SPRITE_COORD_UPPER_LEFT
;
1764 if (variant
->point_sprite_upper_left
!= upper_left
)
1768 /* Otherwise, we're good to go */
1773 * Fix an uncompiled shader's stream output info, and produce a bitmask
1774 * of which VARYING_SLOT_* are captured for stream output.
1776 * Core Gallium stores output->register_index as a "slot" number, where
1777 * slots are assigned consecutively to all outputs in info->outputs_written.
1778 * This naive packing of outputs doesn't work for us - we too have slots,
1779 * but the layout is defined by the VUE map, which we won't have until we
1780 * compile a specific shader variant. So, we remap these and simply store
1781 * VARYING_SLOT_* in our copy's output->register_index fields.
1783 * We then produce a bitmask of outputs which are used for SO.
1785 * Implementation from iris.
1789 update_so_info(struct pipe_stream_output_info
*so_info
,
1790 uint64_t outputs_written
)
1792 uint64_t so_outputs
= 0;
1793 uint8_t reverse_map
[64] = {0};
1796 while (outputs_written
)
1797 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1799 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1800 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1802 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1803 output
->register_index
= reverse_map
[output
->register_index
];
1805 so_outputs
|= 1ull << output
->register_index
;
1812 panfrost_bind_shader_state(
1813 struct pipe_context
*pctx
,
1815 enum pipe_shader_type type
)
1817 struct panfrost_context
*ctx
= pan_context(pctx
);
1818 ctx
->shader
[type
] = hwcso
;
1822 /* Match the appropriate variant */
1824 signed variant
= -1;
1825 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1827 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1828 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1834 if (variant
== -1) {
1835 /* No variant matched, so create a new one */
1836 variant
= variants
->variant_count
++;
1838 if (variants
->variant_count
> variants
->variant_space
) {
1839 unsigned old_space
= variants
->variant_space
;
1841 variants
->variant_space
*= 2;
1842 if (variants
->variant_space
== 0)
1843 variants
->variant_space
= 1;
1845 /* Arbitrary limit to stop runaway programs from
1846 * creating an unbounded number of shader variants. */
1847 assert(variants
->variant_space
< 1024);
1849 unsigned msize
= sizeof(struct panfrost_shader_state
);
1850 variants
->variants
= realloc(variants
->variants
,
1851 variants
->variant_space
* msize
);
1853 memset(&variants
->variants
[old_space
], 0,
1854 (variants
->variant_space
- old_space
) * msize
);
1857 struct panfrost_shader_state
*v
=
1858 &variants
->variants
[variant
];
1860 if (type
== PIPE_SHADER_FRAGMENT
) {
1861 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1863 if (ctx
->rasterizer
) {
1864 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1865 v
->point_sprite_upper_left
=
1866 ctx
->rasterizer
->base
.sprite_coord_mode
==
1867 PIPE_SPRITE_COORD_UPPER_LEFT
;
1871 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1875 /* Select this variant */
1876 variants
->active_variant
= variant
;
1878 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1879 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1881 /* We finally have a variant, so compile it */
1883 if (!shader_state
->compiled
) {
1884 uint64_t outputs_written
= 0;
1886 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1887 variants
->base
.type
,
1888 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1889 variants
->base
.ir
.nir
:
1890 variants
->base
.tokens
,
1891 tgsi_processor_to_shader_stage(type
), shader_state
,
1894 shader_state
->compiled
= true;
1896 /* Fixup the stream out information, since what Gallium returns
1897 * normally is mildly insane */
1899 shader_state
->stream_output
= variants
->base
.stream_output
;
1900 shader_state
->so_mask
=
1901 update_so_info(&shader_state
->stream_output
, outputs_written
);
1906 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1908 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1912 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1914 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1918 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1920 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1924 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1926 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1930 panfrost_set_vertex_buffers(
1931 struct pipe_context
*pctx
,
1932 unsigned start_slot
,
1933 unsigned num_buffers
,
1934 const struct pipe_vertex_buffer
*buffers
)
1936 struct panfrost_context
*ctx
= pan_context(pctx
);
1938 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1942 panfrost_set_constant_buffer(
1943 struct pipe_context
*pctx
,
1944 enum pipe_shader_type shader
, uint index
,
1945 const struct pipe_constant_buffer
*buf
)
1947 struct panfrost_context
*ctx
= pan_context(pctx
);
1948 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1950 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
1952 unsigned mask
= (1 << index
);
1954 if (unlikely(!buf
)) {
1955 pbuf
->enabled_mask
&= ~mask
;
1956 pbuf
->dirty_mask
&= ~mask
;
1960 pbuf
->enabled_mask
|= mask
;
1961 pbuf
->dirty_mask
|= mask
;
1965 panfrost_set_stencil_ref(
1966 struct pipe_context
*pctx
,
1967 const struct pipe_stencil_ref
*ref
)
1969 struct panfrost_context
*ctx
= pan_context(pctx
);
1970 ctx
->stencil_ref
= *ref
;
1973 static enum mali_texture_type
1974 panfrost_translate_texture_type(enum pipe_texture_target t
) {
1978 case PIPE_TEXTURE_1D
:
1979 case PIPE_TEXTURE_1D_ARRAY
:
1982 case PIPE_TEXTURE_2D
:
1983 case PIPE_TEXTURE_2D_ARRAY
:
1984 case PIPE_TEXTURE_RECT
:
1987 case PIPE_TEXTURE_3D
:
1990 case PIPE_TEXTURE_CUBE
:
1991 case PIPE_TEXTURE_CUBE_ARRAY
:
1992 return MALI_TEX_CUBE
;
1995 unreachable("Unknown target");
1999 static struct pipe_sampler_view
*
2000 panfrost_create_sampler_view(
2001 struct pipe_context
*pctx
,
2002 struct pipe_resource
*texture
,
2003 const struct pipe_sampler_view
*template)
2005 struct panfrost_screen
*screen
= pan_screen(pctx
->screen
);
2006 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2008 pipe_reference(NULL
, &texture
->reference
);
2010 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2013 so
->base
= *template;
2014 so
->base
.texture
= texture
;
2015 so
->base
.reference
.count
= 1;
2016 so
->base
.context
= pctx
;
2018 unsigned char user_swizzle
[4] = {
2019 template->swizzle_r
,
2020 template->swizzle_g
,
2021 template->swizzle_b
,
2025 /* In the hardware, array_size refers specifically to array textures,
2026 * whereas in Gallium, it also covers cubemaps */
2028 unsigned array_size
= texture
->array_size
;
2030 if (template->target
== PIPE_TEXTURE_CUBE
) {
2031 /* TODO: Cubemap arrays */
2032 assert(array_size
== 6);
2036 enum mali_texture_type type
=
2037 panfrost_translate_texture_type(template->target
);
2039 unsigned size
= panfrost_estimate_texture_size(
2040 template->u
.tex
.first_level
,
2041 template->u
.tex
.last_level
,
2042 template->u
.tex
.first_layer
,
2043 template->u
.tex
.last_layer
,
2044 type
, prsrc
->layout
);
2046 so
->bo
= panfrost_bo_create(screen
, size
, 0);
2048 panfrost_new_texture(
2050 texture
->width0
, texture
->height0
,
2051 texture
->depth0
, array_size
,
2053 type
, prsrc
->layout
,
2054 template->u
.tex
.first_level
,
2055 template->u
.tex
.last_level
,
2056 template->u
.tex
.first_layer
,
2057 template->u
.tex
.last_layer
,
2058 prsrc
->cubemap_stride
,
2059 panfrost_translate_swizzle_4(user_swizzle
),
2063 return (struct pipe_sampler_view
*) so
;
2067 panfrost_set_sampler_views(
2068 struct pipe_context
*pctx
,
2069 enum pipe_shader_type shader
,
2070 unsigned start_slot
, unsigned num_views
,
2071 struct pipe_sampler_view
**views
)
2073 struct panfrost_context
*ctx
= pan_context(pctx
);
2074 unsigned new_nr
= 0;
2077 assert(start_slot
== 0);
2079 for (i
= 0; i
< num_views
; ++i
) {
2082 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2086 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2087 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2090 ctx
->sampler_view_count
[shader
] = new_nr
;
2094 panfrost_sampler_view_destroy(
2095 struct pipe_context
*pctx
,
2096 struct pipe_sampler_view
*pview
)
2098 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
2100 pipe_resource_reference(&pview
->texture
, NULL
);
2101 panfrost_bo_unreference(view
->bo
);
2106 panfrost_set_shader_buffers(
2107 struct pipe_context
*pctx
,
2108 enum pipe_shader_type shader
,
2109 unsigned start
, unsigned count
,
2110 const struct pipe_shader_buffer
*buffers
,
2111 unsigned writable_bitmask
)
2113 struct panfrost_context
*ctx
= pan_context(pctx
);
2115 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2116 buffers
, start
, count
);
2119 /* Hints that a framebuffer should use AFBC where possible */
2123 struct panfrost_screen
*screen
,
2124 const struct pipe_framebuffer_state
*fb
)
2126 /* AFBC implemenation incomplete; hide it */
2127 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2129 /* Hint AFBC to the resources bound to each color buffer */
2131 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2132 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2133 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2134 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
2137 /* Also hint it to the depth buffer */
2140 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2141 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
2146 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2147 const struct pipe_framebuffer_state
*fb
)
2149 struct panfrost_context
*ctx
= pan_context(pctx
);
2151 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2152 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2154 panfrost_invalidate_frame(ctx
);
2158 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2159 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2161 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2165 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2168 struct panfrost_context
*ctx
= pan_context(pipe
);
2169 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2170 ctx
->depth_stencil
= depth_stencil
;
2175 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2176 * emulated in the fragment shader */
2178 if (depth_stencil
->alpha
.enabled
) {
2179 /* We need to trigger a new shader (maybe) */
2180 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2184 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2186 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2187 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2189 /* If back-stencil is not enabled, use the front values */
2190 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2191 unsigned back_index
= back_enab
? 1 : 0;
2193 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2194 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2196 /* Depth state (TODO: Refactor) */
2197 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2198 depth_stencil
->depth
.writemask
);
2200 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2202 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2203 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2205 /* Bounds test not implemented */
2206 assert(!depth_stencil
->depth
.bounds_test
);
2210 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2216 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2217 unsigned sample_mask
)
2222 panfrost_set_clip_state(struct pipe_context
*pipe
,
2223 const struct pipe_clip_state
*clip
)
2225 //struct panfrost_context *panfrost = pan_context(pipe);
2229 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2230 unsigned start_slot
,
2231 unsigned num_viewports
,
2232 const struct pipe_viewport_state
*viewports
)
2234 struct panfrost_context
*ctx
= pan_context(pipe
);
2236 assert(start_slot
== 0);
2237 assert(num_viewports
== 1);
2239 ctx
->pipe_viewport
= *viewports
;
2243 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2244 unsigned start_slot
,
2245 unsigned num_scissors
,
2246 const struct pipe_scissor_state
*scissors
)
2248 struct panfrost_context
*ctx
= pan_context(pipe
);
2250 assert(start_slot
== 0);
2251 assert(num_scissors
== 1);
2253 ctx
->scissor
= *scissors
;
2257 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2258 const struct pipe_poly_stipple
*stipple
)
2260 //struct panfrost_context *panfrost = pan_context(pipe);
2264 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2267 struct panfrost_context
*ctx
= pan_context(pipe
);
2268 ctx
->active_queries
= enable
;
2272 panfrost_destroy(struct pipe_context
*pipe
)
2274 struct panfrost_context
*panfrost
= pan_context(pipe
);
2276 if (panfrost
->blitter
)
2277 util_blitter_destroy(panfrost
->blitter
);
2279 if (panfrost
->blitter_wallpaper
)
2280 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2282 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2283 u_upload_destroy(pipe
->stream_uploader
);
2288 static struct pipe_query
*
2289 panfrost_create_query(struct pipe_context
*pipe
,
2293 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2298 return (struct pipe_query
*) q
;
2302 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2304 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2307 panfrost_bo_unreference(query
->bo
);
2315 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2317 struct panfrost_context
*ctx
= pan_context(pipe
);
2318 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2320 switch (query
->type
) {
2321 case PIPE_QUERY_OCCLUSION_COUNTER
:
2322 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2323 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2324 /* Allocate a bo for the query results to be stored */
2326 query
->bo
= panfrost_bo_create(
2327 pan_screen(ctx
->base
.screen
),
2328 sizeof(unsigned), 0);
2331 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2332 *result
= 0; /* Default to 0 if nothing at all drawn. */
2333 ctx
->occlusion_query
= query
;
2336 /* Geometry statistics are computed in the driver. XXX: geom/tess
2339 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2340 query
->start
= ctx
->prims_generated
;
2342 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2343 query
->start
= ctx
->tf_prims_generated
;
2347 DBG("Skipping query %u\n", query
->type
);
2355 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2357 struct panfrost_context
*ctx
= pan_context(pipe
);
2358 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2360 switch (query
->type
) {
2361 case PIPE_QUERY_OCCLUSION_COUNTER
:
2362 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2363 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2364 ctx
->occlusion_query
= NULL
;
2366 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2367 query
->end
= ctx
->prims_generated
;
2369 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2370 query
->end
= ctx
->tf_prims_generated
;
2378 panfrost_get_query_result(struct pipe_context
*pipe
,
2379 struct pipe_query
*q
,
2381 union pipe_query_result
*vresult
)
2383 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2384 struct panfrost_context
*ctx
= pan_context(pipe
);
2387 switch (query
->type
) {
2388 case PIPE_QUERY_OCCLUSION_COUNTER
:
2389 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2390 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2392 panfrost_flush_all_batches(ctx
, true);
2394 /* Read back the query results */
2395 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2396 unsigned passed
= *result
;
2398 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2399 vresult
->u64
= passed
;
2401 vresult
->b
= !!passed
;
2406 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2407 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2408 panfrost_flush_all_batches(ctx
, true);
2409 vresult
->u64
= query
->end
- query
->start
;
2413 DBG("Skipped query get %u\n", query
->type
);
2420 static struct pipe_stream_output_target
*
2421 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2422 struct pipe_resource
*prsc
,
2423 unsigned buffer_offset
,
2424 unsigned buffer_size
)
2426 struct pipe_stream_output_target
*target
;
2428 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2433 pipe_reference_init(&target
->reference
, 1);
2434 pipe_resource_reference(&target
->buffer
, prsc
);
2436 target
->context
= pctx
;
2437 target
->buffer_offset
= buffer_offset
;
2438 target
->buffer_size
= buffer_size
;
2444 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2445 struct pipe_stream_output_target
*target
)
2447 pipe_resource_reference(&target
->buffer
, NULL
);
2448 ralloc_free(target
);
2452 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2453 unsigned num_targets
,
2454 struct pipe_stream_output_target
**targets
,
2455 const unsigned *offsets
)
2457 struct panfrost_context
*ctx
= pan_context(pctx
);
2458 struct panfrost_streamout
*so
= &ctx
->streamout
;
2460 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2462 for (unsigned i
= 0; i
< num_targets
; i
++) {
2463 if (offsets
[i
] != -1)
2464 so
->offsets
[i
] = offsets
[i
];
2466 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2469 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2470 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2472 so
->num_targets
= num_targets
;
2475 struct pipe_context
*
2476 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2478 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2479 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2481 gallium
->screen
= screen
;
2483 gallium
->destroy
= panfrost_destroy
;
2485 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2487 gallium
->flush
= panfrost_flush
;
2488 gallium
->clear
= panfrost_clear
;
2489 gallium
->draw_vbo
= panfrost_draw_vbo
;
2491 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2492 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2493 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2495 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2497 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2498 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2499 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2501 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2502 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2503 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2505 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2506 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2507 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2509 gallium
->create_fs_state
= panfrost_create_fs_state
;
2510 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2511 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2513 gallium
->create_vs_state
= panfrost_create_vs_state
;
2514 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2515 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2517 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2518 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2519 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2521 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2522 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2523 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2525 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2527 gallium
->set_clip_state
= panfrost_set_clip_state
;
2528 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2529 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2530 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2531 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2533 gallium
->create_query
= panfrost_create_query
;
2534 gallium
->destroy_query
= panfrost_destroy_query
;
2535 gallium
->begin_query
= panfrost_begin_query
;
2536 gallium
->end_query
= panfrost_end_query
;
2537 gallium
->get_query_result
= panfrost_get_query_result
;
2539 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2540 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2541 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2543 panfrost_resource_context_init(gallium
);
2544 panfrost_blend_context_init(gallium
);
2545 panfrost_compute_context_init(gallium
);
2548 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2549 gallium
->const_uploader
= gallium
->stream_uploader
;
2550 assert(gallium
->stream_uploader
);
2552 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2553 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2555 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2557 ctx
->blitter
= util_blitter_create(gallium
);
2558 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2560 assert(ctx
->blitter
);
2561 assert(ctx
->blitter_wallpaper
);
2563 /* Prepare for render! */
2565 panfrost_batch_init(ctx
);
2566 panfrost_emit_vertex_payload(ctx
);
2567 panfrost_invalidate_frame(ctx
);
2568 panfrost_default_shader_backend(ctx
);