2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
56 #include "pandecode/decode.h"
58 struct midgard_tiler_descriptor
59 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
61 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
62 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
63 struct midgard_tiler_descriptor t
= {0};
64 unsigned height
= batch
->key
.height
;
65 unsigned width
= batch
->key
.width
;
68 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
70 /* Compute the polygon header size and use that to offset the body */
72 unsigned header_size
= panfrost_tiler_header_size(
73 width
, height
, t
.hierarchy_mask
, hierarchy
);
75 t
.polygon_list_size
= panfrost_tiler_full_size(
76 width
, height
, t
.hierarchy_mask
, hierarchy
);
81 struct panfrost_bo
*tiler_heap
;
83 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
84 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
89 /* Allow the entire tiler heap */
90 t
.heap_start
= tiler_heap
->gpu
;
91 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
93 struct panfrost_bo
*tiler_dummy
;
95 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
96 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
98 /* The tiler is disabled, so don't allow the tiler heap */
99 t
.heap_start
= tiler_dummy
->gpu
;
100 t
.heap_end
= t
.heap_start
;
102 /* Use a dummy polygon list */
103 t
.polygon_list
= tiler_dummy
->gpu
;
105 /* Disable the tiler */
107 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
109 t
.hierarchy_mask
= MALI_TILER_USER
;
110 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
112 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
113 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
114 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
118 t
.polygon_list_body
=
119 t
.polygon_list
+ header_size
;
126 struct pipe_context
*pipe
,
128 const union pipe_color_union
*color
,
129 double depth
, unsigned stencil
)
131 struct panfrost_context
*ctx
= pan_context(pipe
);
133 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
134 * the existing batch targeting this FBO has draws. We could probably
135 * avoid that by replacing plain clears by quad-draws with a specific
136 * color/depth/stencil value, thus avoiding the generation of extra
139 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
141 panfrost_batch_add_fbo_bos(batch
);
142 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
145 /* Reset per-frame context, called on context initialisation as well as after
146 * flushing a frame */
149 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
151 /* TODO: When does this need to be handled? */
152 ctx
->active_queries
= true;
156 panfrost_writes_point_size(struct panfrost_context
*ctx
)
158 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
159 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
161 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
165 panfrost_vertex_state_upd_attr_offs(struct panfrost_context
*ctx
,
166 struct mali_vertex_tiler_postfix
*vertex_postfix
)
171 struct panfrost_vertex_state
*so
= ctx
->vertex
;
173 /* Fixup offsets for the second pass. Recall that the hardware
174 * calculates attribute addresses as:
176 * addr = base + (stride * vtx) + src_offset;
178 * However, on Mali, base must be aligned to 64-bytes, so we
181 * base' = base & ~63 = base - (base & 63)
183 * To compensate when using base' (see emit_vertex_data), we have
184 * to adjust src_offset by the masked off piece:
186 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
187 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
188 * = base + (stride * vtx) + src_offset
194 unsigned start
= vertex_postfix
->offset_start
;
196 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
197 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
198 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
200 /* Adjust by the masked off bits of the offset. Make sure we
201 * read src_offset from so->hw (which is not GPU visible)
202 * rather than target (which is) due to caching effects */
204 unsigned src_offset
= so
->pipe
[i
].src_offset
;
206 /* BOs aligned to 4k so guaranteed aligned to 64 */
207 src_offset
+= (buf
->buffer_offset
& 63);
209 /* Also, somewhat obscurely per-instance data needs to be
210 * offset in response to a delayed start in an indexed draw */
212 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
213 src_offset
-= buf
->stride
* start
;
215 so
->hw
[i
].src_offset
= src_offset
;
219 /* Compute number of UBOs active (more specifically, compute the highest UBO
220 * number addressable -- if there are gaps, include them in the count anyway).
221 * We always include UBO #0 in the count, since we *need* uniforms enabled for
225 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
227 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
228 return 32 - __builtin_clz(mask
);
231 /* The entire frame is in memory -- send it off to the kernel! */
235 struct pipe_context
*pipe
,
236 struct pipe_fence_handle
**fence
,
239 struct panfrost_context
*ctx
= pan_context(pipe
);
240 struct util_dynarray fences
;
242 /* We must collect the fences before the flush is done, otherwise we'll
243 * lose track of them.
246 util_dynarray_init(&fences
, NULL
);
247 hash_table_foreach(ctx
->batches
, hentry
) {
248 struct panfrost_batch
*batch
= hentry
->data
;
250 panfrost_batch_fence_reference(batch
->out_sync
);
251 util_dynarray_append(&fences
,
252 struct panfrost_batch_fence
*,
257 /* Submit all pending jobs */
258 panfrost_flush_all_batches(ctx
, false);
261 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
262 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
263 *fence
= (struct pipe_fence_handle
*)f
;
265 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
266 panfrost_batch_fence_unreference(*fence
);
268 util_dynarray_fini(&fences
);
271 if (pan_debug
& PAN_DBG_TRACE
)
272 pandecode_next_frame();
275 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
278 g2m_draw_mode(enum pipe_prim_type mode
)
283 DEFINE_CASE(LINE_LOOP
);
284 DEFINE_CASE(LINE_STRIP
);
285 DEFINE_CASE(TRIANGLES
);
286 DEFINE_CASE(TRIANGLE_STRIP
);
287 DEFINE_CASE(TRIANGLE_FAN
);
289 DEFINE_CASE(QUAD_STRIP
);
290 DEFINE_CASE(POLYGON
);
293 unreachable("Invalid draw mode");
300 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
302 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
304 /* Check if we're scissoring at all */
306 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
309 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
312 /* Count generated primitives (when there is no geom/tess shaders) for
313 * transform feedback */
316 panfrost_statistics_record(
317 struct panfrost_context
*ctx
,
318 const struct pipe_draw_info
*info
)
320 if (!ctx
->active_queries
)
323 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
324 ctx
->prims_generated
+= prims
;
326 if (!ctx
->streamout
.num_targets
)
329 ctx
->tf_prims_generated
+= prims
;
333 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
335 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
338 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
340 ctx
->streamout
.offsets
[i
] += count
;
346 struct pipe_context
*pipe
,
347 const struct pipe_draw_info
*info
)
349 struct panfrost_context
*ctx
= pan_context(pipe
);
351 /* First of all, check the scissor to see if anything is drawn at all.
352 * If it's not, we drop the draw (mostly a conformance issue;
353 * well-behaved apps shouldn't hit this) */
355 if (panfrost_scissor_culls_everything(ctx
))
358 int mode
= info
->mode
;
360 /* Fallback unsupported restart index */
361 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
363 if (info
->primitive_restart
&& info
->index_size
364 && info
->restart_index
!= primitive_index
) {
365 util_draw_vbo_without_prim_restart(pipe
, info
);
369 /* Fallback for unsupported modes */
371 assert(ctx
->rasterizer
!= NULL
);
373 if (!(ctx
->draw_modes
& (1 << mode
))) {
374 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
375 mode
= PIPE_PRIM_TRIANGLE_FAN
;
377 if (info
->count
< 4) {
378 /* Degenerate case? */
382 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
383 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
388 /* Now that we have a guaranteed terminating path, find the job.
389 * Assignment commented out to prevent unused warning */
391 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
393 panfrost_batch_add_fbo_bos(batch
);
394 panfrost_batch_set_requirements(batch
);
396 /* Take into account a negative bias */
397 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
398 ctx
->instance_count
= info
->instance_count
;
399 ctx
->active_prim
= info
->mode
;
401 struct mali_vertex_tiler_prefix vertex_prefix
, tiler_prefix
;
402 struct mali_vertex_tiler_postfix vertex_postfix
, tiler_postfix
;
403 union midgard_primitive_size primitive_size
;
404 unsigned vertex_count
;
406 panfrost_vt_init(ctx
, PIPE_SHADER_VERTEX
, &vertex_prefix
, &vertex_postfix
);
407 panfrost_vt_init(ctx
, PIPE_SHADER_FRAGMENT
, &tiler_prefix
, &tiler_postfix
);
409 panfrost_vt_set_draw_info(ctx
, info
, g2m_draw_mode(mode
),
410 &vertex_postfix
, &tiler_prefix
,
411 &tiler_postfix
, &vertex_count
,
414 panfrost_statistics_record(ctx
, info
);
416 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
417 * vertex_count, 1) */
419 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
420 1, vertex_count
, info
->instance_count
,
423 /* Emit all sort of descriptors. */
424 panfrost_emit_vertex_data(batch
, &vertex_postfix
);
425 panfrost_emit_varying_descriptor(batch
,
428 &vertex_postfix
, &tiler_postfix
,
430 panfrost_emit_shader_meta(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
431 panfrost_emit_shader_meta(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
432 panfrost_emit_vertex_attr_meta(batch
, &vertex_postfix
);
433 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
434 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
435 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
436 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
437 panfrost_emit_const_buf(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
438 panfrost_emit_const_buf(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
439 panfrost_emit_viewport(batch
, &tiler_postfix
);
441 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
443 /* Fire off the draw itself */
444 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
445 &tiler_prefix
, &tiler_postfix
,
448 /* Adjust the batch stack size based on the new shader stack sizes. */
449 panfrost_batch_adjust_stack_size(batch
);
451 /* Increment transform feedback offsets */
452 panfrost_update_streamout_offsets(ctx
);
458 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
464 panfrost_create_rasterizer_state(
465 struct pipe_context
*pctx
,
466 const struct pipe_rasterizer_state
*cso
)
468 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
476 panfrost_bind_rasterizer_state(
477 struct pipe_context
*pctx
,
480 struct panfrost_context
*ctx
= pan_context(pctx
);
482 ctx
->rasterizer
= hwcso
;
487 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
488 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
490 /* Point sprites are emulated */
492 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
494 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
495 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
499 panfrost_create_vertex_elements_state(
500 struct pipe_context
*pctx
,
501 unsigned num_elements
,
502 const struct pipe_vertex_element
*elements
)
504 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
506 so
->num_elements
= num_elements
;
507 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
509 for (int i
= 0; i
< num_elements
; ++i
) {
512 enum pipe_format fmt
= elements
[i
].src_format
;
513 const struct util_format_description
*desc
= util_format_description(fmt
);
514 so
->hw
[i
].unknown1
= 0x2;
515 so
->hw
[i
].swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
517 so
->hw
[i
].format
= panfrost_find_format(desc
);
520 /* Let's also prepare vertex builtins */
521 so
->hw
[PAN_VERTEX_ID
].format
= MALI_R32UI
;
522 so
->hw
[PAN_VERTEX_ID
].swizzle
= panfrost_get_default_swizzle(1);
523 so
->hw
[PAN_INSTANCE_ID
].format
= MALI_R32UI
;
524 so
->hw
[PAN_INSTANCE_ID
].swizzle
= panfrost_get_default_swizzle(1);
530 panfrost_bind_vertex_elements_state(
531 struct pipe_context
*pctx
,
534 struct panfrost_context
*ctx
= pan_context(pctx
);
539 panfrost_create_shader_state(
540 struct pipe_context
*pctx
,
541 const struct pipe_shader_state
*cso
,
542 enum pipe_shader_type stage
)
544 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
547 /* Token deep copy to prevent memory corruption */
549 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
550 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
552 /* Precompile for shader-db if we need to */
553 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
554 struct panfrost_context
*ctx
= pan_context(pctx
);
556 struct panfrost_shader_state state
;
557 uint64_t outputs_written
;
559 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
561 tgsi_processor_to_shader_stage(stage
),
562 &state
, &outputs_written
);
569 panfrost_delete_shader_state(
570 struct pipe_context
*pctx
,
573 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
575 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
576 DBG("Deleting TGSI shader leaks duplicated tokens\n");
579 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
580 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
581 panfrost_bo_unreference(shader_state
->bo
);
582 shader_state
->bo
= NULL
;
590 panfrost_create_sampler_state(
591 struct pipe_context
*pctx
,
592 const struct pipe_sampler_state
*cso
)
594 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
595 struct panfrost_device
*device
= pan_device(pctx
->screen
);
599 if (device
->quirks
& IS_BIFROST
)
600 panfrost_sampler_desc_init_bifrost(cso
, &so
->bifrost_hw
);
602 panfrost_sampler_desc_init(cso
, &so
->midgard_hw
);
608 panfrost_bind_sampler_states(
609 struct pipe_context
*pctx
,
610 enum pipe_shader_type shader
,
611 unsigned start_slot
, unsigned num_sampler
,
614 assert(start_slot
== 0);
616 struct panfrost_context
*ctx
= pan_context(pctx
);
618 /* XXX: Should upload, not just copy? */
619 ctx
->sampler_count
[shader
] = num_sampler
;
620 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
624 panfrost_variant_matches(
625 struct panfrost_context
*ctx
,
626 struct panfrost_shader_state
*variant
,
627 enum pipe_shader_type type
)
629 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
630 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
632 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
634 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
635 /* Make sure enable state is at least the same */
636 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
640 /* Check that the contents of the test are the same */
641 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
642 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
644 if (!(same_func
&& same_ref
)) {
649 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
650 variant
->point_sprite_mask
)) {
651 /* Ensure the same varyings are turned to point sprites */
652 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
655 /* Ensure the orientation is correct */
657 rasterizer
->sprite_coord_mode
==
658 PIPE_SPRITE_COORD_UPPER_LEFT
;
660 if (variant
->point_sprite_upper_left
!= upper_left
)
664 /* Otherwise, we're good to go */
669 * Fix an uncompiled shader's stream output info, and produce a bitmask
670 * of which VARYING_SLOT_* are captured for stream output.
672 * Core Gallium stores output->register_index as a "slot" number, where
673 * slots are assigned consecutively to all outputs in info->outputs_written.
674 * This naive packing of outputs doesn't work for us - we too have slots,
675 * but the layout is defined by the VUE map, which we won't have until we
676 * compile a specific shader variant. So, we remap these and simply store
677 * VARYING_SLOT_* in our copy's output->register_index fields.
679 * We then produce a bitmask of outputs which are used for SO.
681 * Implementation from iris.
685 update_so_info(struct pipe_stream_output_info
*so_info
,
686 uint64_t outputs_written
)
688 uint64_t so_outputs
= 0;
689 uint8_t reverse_map
[64] = {0};
692 while (outputs_written
)
693 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
695 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
696 struct pipe_stream_output
*output
= &so_info
->output
[i
];
698 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
699 output
->register_index
= reverse_map
[output
->register_index
];
701 so_outputs
|= 1ull << output
->register_index
;
708 panfrost_bind_shader_state(
709 struct pipe_context
*pctx
,
711 enum pipe_shader_type type
)
713 struct panfrost_context
*ctx
= pan_context(pctx
);
714 ctx
->shader
[type
] = hwcso
;
718 /* Match the appropriate variant */
721 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
723 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
724 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
731 /* No variant matched, so create a new one */
732 variant
= variants
->variant_count
++;
734 if (variants
->variant_count
> variants
->variant_space
) {
735 unsigned old_space
= variants
->variant_space
;
737 variants
->variant_space
*= 2;
738 if (variants
->variant_space
== 0)
739 variants
->variant_space
= 1;
741 /* Arbitrary limit to stop runaway programs from
742 * creating an unbounded number of shader variants. */
743 assert(variants
->variant_space
< 1024);
745 unsigned msize
= sizeof(struct panfrost_shader_state
);
746 variants
->variants
= realloc(variants
->variants
,
747 variants
->variant_space
* msize
);
749 memset(&variants
->variants
[old_space
], 0,
750 (variants
->variant_space
- old_space
) * msize
);
753 struct panfrost_shader_state
*v
=
754 &variants
->variants
[variant
];
756 if (type
== PIPE_SHADER_FRAGMENT
) {
757 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
759 if (ctx
->rasterizer
) {
760 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
761 v
->point_sprite_upper_left
=
762 ctx
->rasterizer
->base
.sprite_coord_mode
==
763 PIPE_SPRITE_COORD_UPPER_LEFT
;
768 /* Select this variant */
769 variants
->active_variant
= variant
;
771 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
772 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
774 /* We finally have a variant, so compile it */
776 if (!shader_state
->compiled
) {
777 uint64_t outputs_written
= 0;
779 panfrost_shader_compile(ctx
, variants
->base
.type
,
780 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
781 variants
->base
.ir
.nir
:
782 variants
->base
.tokens
,
783 tgsi_processor_to_shader_stage(type
),
787 shader_state
->compiled
= true;
789 /* Fixup the stream out information, since what Gallium returns
790 * normally is mildly insane */
792 shader_state
->stream_output
= variants
->base
.stream_output
;
793 shader_state
->so_mask
=
794 update_so_info(&shader_state
->stream_output
, outputs_written
);
799 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
801 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
805 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
807 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
811 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
813 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
817 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
819 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
823 panfrost_set_vertex_buffers(
824 struct pipe_context
*pctx
,
826 unsigned num_buffers
,
827 const struct pipe_vertex_buffer
*buffers
)
829 struct panfrost_context
*ctx
= pan_context(pctx
);
831 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
835 panfrost_set_constant_buffer(
836 struct pipe_context
*pctx
,
837 enum pipe_shader_type shader
, uint index
,
838 const struct pipe_constant_buffer
*buf
)
840 struct panfrost_context
*ctx
= pan_context(pctx
);
841 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
843 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
845 unsigned mask
= (1 << index
);
847 if (unlikely(!buf
)) {
848 pbuf
->enabled_mask
&= ~mask
;
849 pbuf
->dirty_mask
&= ~mask
;
853 pbuf
->enabled_mask
|= mask
;
854 pbuf
->dirty_mask
|= mask
;
858 panfrost_set_stencil_ref(
859 struct pipe_context
*pctx
,
860 const struct pipe_stencil_ref
*ref
)
862 struct panfrost_context
*ctx
= pan_context(pctx
);
863 ctx
->stencil_ref
= *ref
;
866 static enum mali_texture_type
867 panfrost_translate_texture_type(enum pipe_texture_target t
) {
871 case PIPE_TEXTURE_1D
:
872 case PIPE_TEXTURE_1D_ARRAY
:
875 case PIPE_TEXTURE_2D
:
876 case PIPE_TEXTURE_2D_ARRAY
:
877 case PIPE_TEXTURE_RECT
:
880 case PIPE_TEXTURE_3D
:
883 case PIPE_TEXTURE_CUBE
:
884 case PIPE_TEXTURE_CUBE_ARRAY
:
885 return MALI_TEX_CUBE
;
888 unreachable("Unknown target");
892 static struct pipe_sampler_view
*
893 panfrost_create_sampler_view(
894 struct pipe_context
*pctx
,
895 struct pipe_resource
*texture
,
896 const struct pipe_sampler_view
*template)
898 struct panfrost_device
*device
= pan_device(pctx
->screen
);
899 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
901 pipe_reference(NULL
, &texture
->reference
);
903 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
906 so
->base
= *template;
907 so
->base
.texture
= texture
;
908 so
->base
.reference
.count
= 1;
909 so
->base
.context
= pctx
;
911 unsigned char user_swizzle
[4] = {
918 /* In the hardware, array_size refers specifically to array textures,
919 * whereas in Gallium, it also covers cubemaps */
921 unsigned array_size
= texture
->array_size
;
923 if (template->target
== PIPE_TEXTURE_CUBE
) {
924 /* TODO: Cubemap arrays */
925 assert(array_size
== 6);
929 enum mali_texture_type type
=
930 panfrost_translate_texture_type(template->target
);
932 if (device
->quirks
& IS_BIFROST
) {
933 const struct util_format_description
*desc
=
934 util_format_description(template->format
);
935 unsigned char composed_swizzle
[4];
936 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
938 unsigned size
= panfrost_estimate_texture_payload_size(
939 template->u
.tex
.first_level
,
940 template->u
.tex
.last_level
,
941 template->u
.tex
.first_layer
,
942 template->u
.tex
.last_layer
,
943 type
, prsrc
->layout
);
945 so
->bifrost_bo
= pan_bo_create(device
, size
, 0);
947 so
->bifrost_descriptor
= rzalloc(pctx
, struct bifrost_texture_descriptor
);
948 panfrost_new_texture_bifrost(
949 so
->bifrost_descriptor
,
950 texture
->width0
, texture
->height0
,
951 texture
->depth0
, array_size
,
954 template->u
.tex
.first_level
,
955 template->u
.tex
.last_level
,
956 template->u
.tex
.first_layer
,
957 template->u
.tex
.last_layer
,
958 prsrc
->cubemap_stride
,
959 panfrost_translate_swizzle_4(composed_swizzle
),
964 unsigned size
= panfrost_estimate_texture_payload_size(
965 template->u
.tex
.first_level
,
966 template->u
.tex
.last_level
,
967 template->u
.tex
.first_layer
,
968 template->u
.tex
.last_layer
,
969 type
, prsrc
->layout
);
970 size
+= sizeof(struct mali_texture_descriptor
);
972 so
->midgard_bo
= pan_bo_create(device
, size
, 0);
974 panfrost_new_texture(
976 texture
->width0
, texture
->height0
,
977 texture
->depth0
, array_size
,
980 template->u
.tex
.first_level
,
981 template->u
.tex
.last_level
,
982 template->u
.tex
.first_layer
,
983 template->u
.tex
.last_layer
,
984 prsrc
->cubemap_stride
,
985 panfrost_translate_swizzle_4(user_swizzle
),
990 return (struct pipe_sampler_view
*) so
;
994 panfrost_set_sampler_views(
995 struct pipe_context
*pctx
,
996 enum pipe_shader_type shader
,
997 unsigned start_slot
, unsigned num_views
,
998 struct pipe_sampler_view
**views
)
1000 struct panfrost_context
*ctx
= pan_context(pctx
);
1001 unsigned new_nr
= 0;
1004 assert(start_slot
== 0);
1006 for (i
= 0; i
< num_views
; ++i
) {
1009 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1013 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1014 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1017 ctx
->sampler_view_count
[shader
] = new_nr
;
1021 panfrost_sampler_view_destroy(
1022 struct pipe_context
*pctx
,
1023 struct pipe_sampler_view
*pview
)
1025 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1027 pipe_resource_reference(&pview
->texture
, NULL
);
1028 panfrost_bo_unreference(view
->midgard_bo
);
1029 panfrost_bo_unreference(view
->bifrost_bo
);
1030 if (view
->bifrost_descriptor
)
1031 ralloc_free(view
->bifrost_descriptor
);
1036 panfrost_set_shader_buffers(
1037 struct pipe_context
*pctx
,
1038 enum pipe_shader_type shader
,
1039 unsigned start
, unsigned count
,
1040 const struct pipe_shader_buffer
*buffers
,
1041 unsigned writable_bitmask
)
1043 struct panfrost_context
*ctx
= pan_context(pctx
);
1045 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1046 buffers
, start
, count
);
1049 /* Hints that a framebuffer should use AFBC where possible */
1053 struct panfrost_device
*device
,
1054 const struct pipe_framebuffer_state
*fb
)
1056 /* AFBC implemenation incomplete; hide it */
1057 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
1059 /* Hint AFBC to the resources bound to each color buffer */
1061 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
1062 struct pipe_surface
*surf
= fb
->cbufs
[i
];
1063 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1064 panfrost_resource_hint_layout(device
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1067 /* Also hint it to the depth buffer */
1070 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
1071 panfrost_resource_hint_layout(device
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1076 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1077 const struct pipe_framebuffer_state
*fb
)
1079 struct panfrost_context
*ctx
= pan_context(pctx
);
1081 panfrost_hint_afbc(pan_device(pctx
->screen
), fb
);
1082 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1084 panfrost_invalidate_frame(ctx
);
1088 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1089 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
1091 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
1095 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1098 struct panfrost_context
*ctx
= pan_context(pipe
);
1099 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
1100 ctx
->depth_stencil
= depth_stencil
;
1105 /* Alpha does not exist in the hardware (it's not in ES3), so it's
1106 * emulated in the fragment shader */
1108 if (depth_stencil
->alpha
.enabled
) {
1109 /* We need to trigger a new shader (maybe) */
1110 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1113 /* Bounds test not implemented */
1114 assert(!depth_stencil
->depth
.bounds_test
);
1118 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1124 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1125 unsigned sample_mask
)
1130 panfrost_set_clip_state(struct pipe_context
*pipe
,
1131 const struct pipe_clip_state
*clip
)
1133 //struct panfrost_context *panfrost = pan_context(pipe);
1137 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1138 unsigned start_slot
,
1139 unsigned num_viewports
,
1140 const struct pipe_viewport_state
*viewports
)
1142 struct panfrost_context
*ctx
= pan_context(pipe
);
1144 assert(start_slot
== 0);
1145 assert(num_viewports
== 1);
1147 ctx
->pipe_viewport
= *viewports
;
1151 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1152 unsigned start_slot
,
1153 unsigned num_scissors
,
1154 const struct pipe_scissor_state
*scissors
)
1156 struct panfrost_context
*ctx
= pan_context(pipe
);
1158 assert(start_slot
== 0);
1159 assert(num_scissors
== 1);
1161 ctx
->scissor
= *scissors
;
1165 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1166 const struct pipe_poly_stipple
*stipple
)
1168 //struct panfrost_context *panfrost = pan_context(pipe);
1172 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1175 struct panfrost_context
*ctx
= pan_context(pipe
);
1176 ctx
->active_queries
= enable
;
1180 panfrost_destroy(struct pipe_context
*pipe
)
1182 struct panfrost_context
*panfrost
= pan_context(pipe
);
1184 if (panfrost
->blitter
)
1185 util_blitter_destroy(panfrost
->blitter
);
1187 if (panfrost
->blitter_wallpaper
)
1188 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1190 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1191 u_upload_destroy(pipe
->stream_uploader
);
1196 static struct pipe_query
*
1197 panfrost_create_query(struct pipe_context
*pipe
,
1201 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1206 return (struct pipe_query
*) q
;
1210 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1212 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1215 panfrost_bo_unreference(query
->bo
);
1223 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1225 struct panfrost_context
*ctx
= pan_context(pipe
);
1226 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1228 switch (query
->type
) {
1229 case PIPE_QUERY_OCCLUSION_COUNTER
:
1230 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1231 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1232 /* Allocate a bo for the query results to be stored */
1234 query
->bo
= pan_bo_create(
1235 pan_device(ctx
->base
.screen
),
1236 sizeof(unsigned), 0);
1239 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1240 *result
= 0; /* Default to 0 if nothing at all drawn. */
1241 ctx
->occlusion_query
= query
;
1244 /* Geometry statistics are computed in the driver. XXX: geom/tess
1247 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1248 query
->start
= ctx
->prims_generated
;
1250 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1251 query
->start
= ctx
->tf_prims_generated
;
1255 DBG("Skipping query %u\n", query
->type
);
1263 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1265 struct panfrost_context
*ctx
= pan_context(pipe
);
1266 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1268 switch (query
->type
) {
1269 case PIPE_QUERY_OCCLUSION_COUNTER
:
1270 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1271 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1272 ctx
->occlusion_query
= NULL
;
1274 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1275 query
->end
= ctx
->prims_generated
;
1277 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1278 query
->end
= ctx
->tf_prims_generated
;
1286 panfrost_get_query_result(struct pipe_context
*pipe
,
1287 struct pipe_query
*q
,
1289 union pipe_query_result
*vresult
)
1291 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1292 struct panfrost_context
*ctx
= pan_context(pipe
);
1295 switch (query
->type
) {
1296 case PIPE_QUERY_OCCLUSION_COUNTER
:
1297 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1298 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1300 panfrost_flush_all_batches(ctx
, true);
1302 /* Read back the query results */
1303 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1304 unsigned passed
= *result
;
1306 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1307 vresult
->u64
= passed
;
1309 vresult
->b
= !!passed
;
1314 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1315 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1316 panfrost_flush_all_batches(ctx
, true);
1317 vresult
->u64
= query
->end
- query
->start
;
1321 DBG("Skipped query get %u\n", query
->type
);
1328 static struct pipe_stream_output_target
*
1329 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1330 struct pipe_resource
*prsc
,
1331 unsigned buffer_offset
,
1332 unsigned buffer_size
)
1334 struct pipe_stream_output_target
*target
;
1336 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1341 pipe_reference_init(&target
->reference
, 1);
1342 pipe_resource_reference(&target
->buffer
, prsc
);
1344 target
->context
= pctx
;
1345 target
->buffer_offset
= buffer_offset
;
1346 target
->buffer_size
= buffer_size
;
1352 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1353 struct pipe_stream_output_target
*target
)
1355 pipe_resource_reference(&target
->buffer
, NULL
);
1356 ralloc_free(target
);
1360 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1361 unsigned num_targets
,
1362 struct pipe_stream_output_target
**targets
,
1363 const unsigned *offsets
)
1365 struct panfrost_context
*ctx
= pan_context(pctx
);
1366 struct panfrost_streamout
*so
= &ctx
->streamout
;
1368 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1370 for (unsigned i
= 0; i
< num_targets
; i
++) {
1371 if (offsets
[i
] != -1)
1372 so
->offsets
[i
] = offsets
[i
];
1374 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1377 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1378 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1380 so
->num_targets
= num_targets
;
1383 struct pipe_context
*
1384 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1386 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1387 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1389 gallium
->screen
= screen
;
1391 gallium
->destroy
= panfrost_destroy
;
1393 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1395 gallium
->flush
= panfrost_flush
;
1396 gallium
->clear
= panfrost_clear
;
1397 gallium
->draw_vbo
= panfrost_draw_vbo
;
1399 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1400 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1401 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1403 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1405 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1406 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1407 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1409 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1410 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1411 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1413 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1414 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1415 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1417 gallium
->create_fs_state
= panfrost_create_fs_state
;
1418 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1419 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1421 gallium
->create_vs_state
= panfrost_create_vs_state
;
1422 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1423 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1425 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1426 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1427 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1429 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1430 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1431 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1433 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1435 gallium
->set_clip_state
= panfrost_set_clip_state
;
1436 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1437 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1438 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1439 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1441 gallium
->create_query
= panfrost_create_query
;
1442 gallium
->destroy_query
= panfrost_destroy_query
;
1443 gallium
->begin_query
= panfrost_begin_query
;
1444 gallium
->end_query
= panfrost_end_query
;
1445 gallium
->get_query_result
= panfrost_get_query_result
;
1447 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1448 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1449 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1451 panfrost_resource_context_init(gallium
);
1452 panfrost_blend_context_init(gallium
);
1453 panfrost_compute_context_init(gallium
);
1456 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1457 gallium
->const_uploader
= gallium
->stream_uploader
;
1458 assert(gallium
->stream_uploader
);
1460 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
1461 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
1463 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1465 ctx
->blitter
= util_blitter_create(gallium
);
1466 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1468 assert(ctx
->blitter
);
1469 assert(ctx
->blitter_wallpaper
);
1471 /* Prepare for render! */
1473 panfrost_batch_init(ctx
);
1474 panfrost_invalidate_frame(ctx
);