2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
56 #include "pandecode/decode.h"
58 struct midgard_tiler_descriptor
59 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
61 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
62 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
63 struct midgard_tiler_descriptor t
= {0};
64 unsigned height
= batch
->key
.height
;
65 unsigned width
= batch
->key
.width
;
68 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
70 /* Compute the polygon header size and use that to offset the body */
72 unsigned header_size
= panfrost_tiler_header_size(
73 width
, height
, t
.hierarchy_mask
, hierarchy
);
75 t
.polygon_list_size
= panfrost_tiler_full_size(
76 width
, height
, t
.hierarchy_mask
, hierarchy
);
81 struct panfrost_bo
*tiler_heap
;
83 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
84 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
89 /* Allow the entire tiler heap */
90 t
.heap_start
= tiler_heap
->gpu
;
91 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
93 struct panfrost_bo
*tiler_dummy
;
95 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
96 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
98 /* The tiler is disabled, so don't allow the tiler heap */
99 t
.heap_start
= tiler_dummy
->gpu
;
100 t
.heap_end
= t
.heap_start
;
102 /* Use a dummy polygon list */
103 t
.polygon_list
= tiler_dummy
->gpu
;
105 /* Disable the tiler */
107 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
109 t
.hierarchy_mask
= MALI_TILER_USER
;
110 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
112 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
113 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
114 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
118 t
.polygon_list_body
=
119 t
.polygon_list
+ header_size
;
126 struct pipe_context
*pipe
,
128 const union pipe_color_union
*color
,
129 double depth
, unsigned stencil
)
131 struct panfrost_context
*ctx
= pan_context(pipe
);
133 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
134 * the existing batch targeting this FBO has draws. We could probably
135 * avoid that by replacing plain clears by quad-draws with a specific
136 * color/depth/stencil value, thus avoiding the generation of extra
139 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
141 panfrost_batch_add_fbo_bos(batch
);
142 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
145 /* Reset per-frame context, called on context initialisation as well as after
146 * flushing a frame */
149 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
151 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
152 ctx
->payloads
[i
].postfix
.shared_memory
= 0;
154 /* TODO: When does this need to be handled? */
155 ctx
->active_queries
= true;
158 /* In practice, every field of these payloads should be configurable
159 * arbitrarily, which means these functions are basically catch-all's for
160 * as-of-yet unwavering unknowns */
163 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
165 /* 0x2 bit clear on 32-bit T6XX */
167 struct midgard_payload_vertex_tiler payload
= {
168 .gl_enables
= 0x4 | 0x2,
171 /* Vertex and compute are closely coupled, so share a payload */
173 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
174 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
178 translate_tex_wrap(enum pipe_tex_wrap w
)
181 case PIPE_TEX_WRAP_REPEAT
:
182 return MALI_WRAP_REPEAT
;
184 case PIPE_TEX_WRAP_CLAMP
:
185 return MALI_WRAP_CLAMP
;
187 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
188 return MALI_WRAP_CLAMP_TO_EDGE
;
190 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
191 return MALI_WRAP_CLAMP_TO_BORDER
;
193 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
194 return MALI_WRAP_MIRRORED_REPEAT
;
196 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
197 return MALI_WRAP_MIRRORED_CLAMP
;
199 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
200 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
202 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
203 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
206 unreachable("Invalid wrap");
211 panfrost_translate_compare_func(enum pipe_compare_func in
)
214 case PIPE_FUNC_NEVER
:
215 return MALI_FUNC_NEVER
;
218 return MALI_FUNC_LESS
;
220 case PIPE_FUNC_EQUAL
:
221 return MALI_FUNC_EQUAL
;
223 case PIPE_FUNC_LEQUAL
:
224 return MALI_FUNC_LEQUAL
;
226 case PIPE_FUNC_GREATER
:
227 return MALI_FUNC_GREATER
;
229 case PIPE_FUNC_NOTEQUAL
:
230 return MALI_FUNC_NOTEQUAL
;
232 case PIPE_FUNC_GEQUAL
:
233 return MALI_FUNC_GEQUAL
;
235 case PIPE_FUNC_ALWAYS
:
236 return MALI_FUNC_ALWAYS
;
239 unreachable("Invalid func");
244 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
247 case PIPE_STENCIL_OP_KEEP
:
248 return MALI_STENCIL_KEEP
;
250 case PIPE_STENCIL_OP_ZERO
:
251 return MALI_STENCIL_ZERO
;
253 case PIPE_STENCIL_OP_REPLACE
:
254 return MALI_STENCIL_REPLACE
;
256 case PIPE_STENCIL_OP_INCR
:
257 return MALI_STENCIL_INCR
;
259 case PIPE_STENCIL_OP_DECR
:
260 return MALI_STENCIL_DECR
;
262 case PIPE_STENCIL_OP_INCR_WRAP
:
263 return MALI_STENCIL_INCR_WRAP
;
265 case PIPE_STENCIL_OP_DECR_WRAP
:
266 return MALI_STENCIL_DECR_WRAP
;
268 case PIPE_STENCIL_OP_INVERT
:
269 return MALI_STENCIL_INVERT
;
272 unreachable("Invalid stencil op");
277 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
279 out
->ref
= 0; /* Gallium gets it from elsewhere */
281 out
->mask
= in
->valuemask
;
282 out
->func
= panfrost_translate_compare_func(in
->func
);
283 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
284 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
285 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
289 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
291 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
292 struct mali_shader_meta shader
= {
293 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
295 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
296 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
299 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
300 * required (independent of 32-bit/64-bit descriptors), or why it's not
301 * used on later GPU revisions. Otherwise, all shader jobs fault on
302 * these earlier chips (perhaps this is a chicken bit of some kind).
303 * More investigation is needed. */
305 if (screen
->quirks
& MIDGARD_SFBD
)
306 shader
.unknown2_4
|= 0x10;
308 struct pipe_stencil_state default_stencil
= {
310 .func
= PIPE_FUNC_ALWAYS
,
311 .fail_op
= MALI_STENCIL_KEEP
,
312 .zfail_op
= MALI_STENCIL_KEEP
,
313 .zpass_op
= MALI_STENCIL_KEEP
,
318 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
319 shader
.stencil_mask_front
= default_stencil
.writemask
;
321 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
322 shader
.stencil_mask_back
= default_stencil
.writemask
;
324 if (default_stencil
.enabled
)
325 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
327 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
331 panfrost_writes_point_size(struct panfrost_context
*ctx
)
333 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
334 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
336 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
339 /* Stage the attribute descriptors so we can adjust src_offset
340 * to let BOs align nicely */
343 panfrost_stage_attributes(struct panfrost_context
*ctx
)
345 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
346 struct panfrost_vertex_state
*so
= ctx
->vertex
;
348 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
349 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
350 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
352 /* Copy as-is for the first pass */
353 memcpy(target
, so
->hw
, sz
);
355 /* Fixup offsets for the second pass. Recall that the hardware
356 * calculates attribute addresses as:
358 * addr = base + (stride * vtx) + src_offset;
360 * However, on Mali, base must be aligned to 64-bytes, so we
363 * base' = base & ~63 = base - (base & 63)
365 * To compensate when using base' (see emit_vertex_data), we have
366 * to adjust src_offset by the masked off piece:
368 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
369 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
370 * = base + (stride * vtx) + src_offset
376 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
378 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
379 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
380 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
381 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
382 mali_ptr addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
384 /* Adjust by the masked off bits of the offset. Make sure we
385 * read src_offset from so->hw (which is not GPU visible)
386 * rather than target (which is) due to caching effects */
388 unsigned src_offset
= so
->hw
[i
].src_offset
;
389 src_offset
+= (addr
& 63);
391 /* Also, somewhat obscurely per-instance data needs to be
392 * offset in response to a delayed start in an indexed draw */
394 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
395 src_offset
-= buf
->stride
* start
;
397 target
[i
].src_offset
= src_offset
;
400 /* Let's also include vertex builtins */
402 struct mali_attr_meta builtin
= {
403 .format
= MALI_R32UI
,
404 .swizzle
= panfrost_get_default_swizzle(1)
407 /* See mali_attr_meta specification for the magic number */
409 builtin
.index
= so
->vertexid_index
;
410 memcpy(&target
[PAN_VERTEX_ID
], &builtin
, 4);
412 builtin
.index
= so
->vertexid_index
+ 1;
413 memcpy(&target
[PAN_INSTANCE_ID
], &builtin
, 4);
415 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
419 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
421 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
422 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
424 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
427 if (ctx
->sampler_count
[t
]) {
428 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
430 struct panfrost_transfer transfer
=
431 panfrost_allocate_transient(batch
, transfer_size
);
433 struct mali_sampler_descriptor
*desc
=
434 (struct mali_sampler_descriptor
*) transfer
.cpu
;
436 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
437 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
439 upload
= transfer
.gpu
;
442 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
448 struct panfrost_context
*ctx
,
449 enum pipe_shader_type st
,
450 struct panfrost_sampler_view
*view
)
455 struct pipe_sampler_view
*pview
= &view
->base
;
456 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
458 /* Add the BO to the job so it's retained until the job is done. */
459 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
461 panfrost_batch_add_bo(batch
, rsrc
->bo
,
462 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
463 panfrost_bo_access_for_stage(st
));
465 panfrost_batch_add_bo(batch
, view
->bo
,
466 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
467 panfrost_bo_access_for_stage(st
));
469 return view
->bo
->gpu
;
473 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
475 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
477 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
478 mali_ptr trampoline
= 0;
480 if (ctx
->sampler_view_count
[t
]) {
481 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
483 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
485 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
487 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
490 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
494 /* Compute number of UBOs active (more specifically, compute the highest UBO
495 * number addressable -- if there are gaps, include them in the count anyway).
496 * We always include UBO #0 in the count, since we *need* uniforms enabled for
500 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
502 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
503 return 32 - __builtin_clz(mask
);
506 /* Fixes up a shader state with current state */
509 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
510 enum pipe_shader_type stage
)
512 struct panfrost_shader_state
*ss
= panfrost_get_shader_state(ctx
, stage
);
517 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
518 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
520 ss
->tripipe
->midgard1
.flags_lo
= 0x220;
522 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
523 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
526 /* Go through dirty flags and actualise them in the cmdstream. */
529 panfrost_emit_for_draw(struct panfrost_context
*ctx
)
531 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
532 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
534 panfrost_batch_add_fbo_bos(batch
);
536 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
)
537 panfrost_vt_attach_framebuffer(ctx
, &ctx
->payloads
[i
]);
539 panfrost_emit_vertex_data(batch
);
541 /* Varyings emitted for -all- geometry */
542 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
543 panfrost_emit_varying_descriptor(ctx
, total_count
);
545 if (ctx
->rasterizer
) {
546 bool msaa
= ctx
->rasterizer
->base
.multisample
;
548 /* TODO: Sample size */
549 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
550 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
553 panfrost_batch_set_requirements(batch
);
555 panfrost_vt_update_rasterizer(ctx
, &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
556 panfrost_vt_update_occlusion_query(ctx
, &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
558 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
559 panfrost_emit_shader_meta(batch
, PIPE_SHADER_VERTEX
,
560 &ctx
->payloads
[PIPE_SHADER_VERTEX
]);
562 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
563 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
565 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
567 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
570 COPY(attribute_count
);
574 COPY(midgard1
.uniform_count
);
575 COPY(midgard1
.uniform_buffer_count
);
576 COPY(midgard1
.work_count
);
577 COPY(midgard1
.flags_lo
);
578 COPY(midgard1
.flags_hi
);
582 /* Get blending setup */
583 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
585 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
586 unsigned shader_offset
= 0;
587 struct panfrost_bo
*shader_bo
= NULL
;
589 for (unsigned c
= 0; c
< rt_count
; ++c
) {
590 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
593 /* If there is a blend shader, work registers are shared. XXX: opt */
595 for (unsigned c
= 0; c
< rt_count
; ++c
) {
596 if (blend
[c
].is_shader
)
597 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
600 /* Depending on whether it's legal to in the given shader, we
601 * try to enable early-z testing (or forward-pixel kill?) */
603 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_EARLY_Z
,
604 !variant
->can_discard
&& !variant
->writes_depth
);
606 /* Add the writes Z/S flags if needed. */
607 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
,
608 MALI_WRITES_Z
, variant
->writes_depth
);
609 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_hi
,
610 MALI_WRITES_S
, variant
->writes_stencil
);
612 /* Any time texturing is used, derivatives are implicitly
613 * calculated, so we need to enable helper invocations */
615 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
617 /* Assign the stencil refs late */
619 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
620 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
621 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
623 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
624 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
626 /* CAN_DISCARD should be set if the fragment shader possibly
627 * contains a 'discard' instruction. It is likely this is
628 * related to optimizations related to forward-pixel kill, as
629 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
630 * thing?" by Peter Harris
633 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
634 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, 0x400, variant
->can_discard
);
636 /* Even on MFBD, the shader descriptor gets blend shaders. It's
637 * *also* copied to the blend_meta appended (by convention),
638 * but this is the field actually read by the hardware. (Or
639 * maybe both are read...?). Specify the last RTi with a blend
642 ctx
->fragment_shader_core
.blend
.shader
= 0;
644 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
645 if (blend
[rt
].is_shader
) {
646 ctx
->fragment_shader_core
.blend
.shader
=
647 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
652 if (screen
->quirks
& MIDGARD_SFBD
) {
653 /* When only a single render target platform is used, the blend
654 * information is inside the shader meta itself. We
655 * additionally need to signal CAN_DISCARD for nontrivial blend
656 * modes (so we're able to read back the destination buffer) */
658 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
660 if (!blend
[0].is_shader
) {
661 ctx
->fragment_shader_core
.blend
.equation
=
662 *blend
[0].equation
.equation
;
663 ctx
->fragment_shader_core
.blend
.constant
=
664 blend
[0].equation
.constant
;
667 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
670 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
671 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
672 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
674 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
676 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
677 /* Additional blend descriptor tacked on for jobs using MFBD */
679 struct midgard_blend_rt rts
[4];
681 for (unsigned i
= 0; i
< rt_count
; ++i
) {
682 rts
[i
].flags
= 0x200;
685 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
686 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
687 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
689 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
690 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
691 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
692 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
694 if (blend
[i
].is_shader
) {
695 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
697 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
698 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
702 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
706 /* We stage to transient, so always dirty.. */
708 panfrost_stage_attributes(ctx
);
710 panfrost_upload_sampler_descriptors(ctx
);
711 panfrost_upload_texture_descriptors(ctx
);
713 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
)
714 panfrost_emit_const_buf(batch
, i
, &ctx
->payloads
[i
]);
716 /* TODO: Upload the viewport somewhere more appropriate */
718 panfrost_emit_viewport(batch
, &ctx
->payloads
[PIPE_SHADER_FRAGMENT
]);
721 /* Corresponds to exactly one draw, but does not submit anything */
724 panfrost_queue_draw(struct panfrost_context
*ctx
)
726 /* Handle dirty flags now */
727 panfrost_emit_for_draw(ctx
);
729 /* If rasterizer discard is enable, only submit the vertex */
731 bool rasterizer_discard
= ctx
->rasterizer
732 && ctx
->rasterizer
->base
.rasterizer_discard
;
735 struct midgard_payload_vertex_tiler
*vertex_payload
= &ctx
->payloads
[PIPE_SHADER_VERTEX
];
736 struct midgard_payload_vertex_tiler
*tiler_payload
= &ctx
->payloads
[PIPE_SHADER_FRAGMENT
];
738 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
739 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->tiler_dep
;
742 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
743 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, batch
->job_index
+ 2, tiler_payload
, sizeof(*tiler_payload
), true);
744 panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), true);
746 unsigned vertex
= panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), false);
748 if (!rasterizer_discard
)
749 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, vertex
, tiler_payload
, sizeof(*tiler_payload
), false);
752 panfrost_batch_adjust_stack_size(batch
);
755 /* The entire frame is in memory -- send it off to the kernel! */
759 struct pipe_context
*pipe
,
760 struct pipe_fence_handle
**fence
,
763 struct panfrost_context
*ctx
= pan_context(pipe
);
764 struct util_dynarray fences
;
766 /* We must collect the fences before the flush is done, otherwise we'll
767 * lose track of them.
770 util_dynarray_init(&fences
, NULL
);
771 hash_table_foreach(ctx
->batches
, hentry
) {
772 struct panfrost_batch
*batch
= hentry
->data
;
774 panfrost_batch_fence_reference(batch
->out_sync
);
775 util_dynarray_append(&fences
,
776 struct panfrost_batch_fence
*,
781 /* Submit all pending jobs */
782 panfrost_flush_all_batches(ctx
, false);
785 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
786 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
787 *fence
= (struct pipe_fence_handle
*)f
;
789 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
790 panfrost_batch_fence_unreference(*fence
);
792 util_dynarray_fini(&fences
);
795 if (pan_debug
& PAN_DBG_TRACE
)
796 pandecode_next_frame();
799 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
802 g2m_draw_mode(enum pipe_prim_type mode
)
807 DEFINE_CASE(LINE_LOOP
);
808 DEFINE_CASE(LINE_STRIP
);
809 DEFINE_CASE(TRIANGLES
);
810 DEFINE_CASE(TRIANGLE_STRIP
);
811 DEFINE_CASE(TRIANGLE_FAN
);
813 DEFINE_CASE(QUAD_STRIP
);
814 DEFINE_CASE(POLYGON
);
817 unreachable("Invalid draw mode");
824 panfrost_translate_index_size(unsigned size
)
828 return MALI_DRAW_INDEXED_UINT8
;
831 return MALI_DRAW_INDEXED_UINT16
;
834 return MALI_DRAW_INDEXED_UINT32
;
837 unreachable("Invalid index size");
841 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
842 * good for the duration of the draw (transient), could last longer. Also get
843 * the bounds on the index buffer for the range accessed by the draw. We do
844 * these operations together because there are natural optimizations which
845 * require them to be together. */
848 panfrost_get_index_buffer_bounded(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
, unsigned *min_index
, unsigned *max_index
)
850 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
852 off_t offset
= info
->start
* info
->index_size
;
853 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
856 bool needs_indices
= true;
858 if (info
->max_index
!= ~0u) {
859 *min_index
= info
->min_index
;
860 *max_index
= info
->max_index
;
861 needs_indices
= false;
864 if (!info
->has_user_indices
) {
865 /* Only resources can be directly mapped */
866 panfrost_batch_add_bo(batch
, rsrc
->bo
,
867 PAN_BO_ACCESS_SHARED
|
869 PAN_BO_ACCESS_VERTEX_TILER
);
870 out
= rsrc
->bo
->gpu
+ offset
;
872 /* Check the cache */
873 needs_indices
= !panfrost_minmax_cache_get(rsrc
->index_cache
, info
->start
, info
->count
,
874 min_index
, max_index
);
876 /* Otherwise, we need to upload to transient memory */
877 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
878 out
= panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
883 u_vbuf_get_minmax_index(&ctx
->base
, info
, min_index
, max_index
);
885 if (!info
->has_user_indices
) {
886 panfrost_minmax_cache_add(rsrc
->index_cache
, info
->start
, info
->count
,
887 *min_index
, *max_index
);
896 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
898 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
900 /* Check if we're scissoring at all */
902 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
905 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
908 /* Count generated primitives (when there is no geom/tess shaders) for
909 * transform feedback */
912 panfrost_statistics_record(
913 struct panfrost_context
*ctx
,
914 const struct pipe_draw_info
*info
)
916 if (!ctx
->active_queries
)
919 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
920 ctx
->prims_generated
+= prims
;
922 if (!ctx
->streamout
.num_targets
)
925 ctx
->tf_prims_generated
+= prims
;
930 struct pipe_context
*pipe
,
931 const struct pipe_draw_info
*info
)
933 struct panfrost_context
*ctx
= pan_context(pipe
);
935 /* First of all, check the scissor to see if anything is drawn at all.
936 * If it's not, we drop the draw (mostly a conformance issue;
937 * well-behaved apps shouldn't hit this) */
939 if (panfrost_scissor_culls_everything(ctx
))
942 int mode
= info
->mode
;
944 /* Fallback unsupported restart index */
945 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
947 if (info
->primitive_restart
&& info
->index_size
948 && info
->restart_index
!= primitive_index
) {
949 util_draw_vbo_without_prim_restart(pipe
, info
);
953 /* Fallback for unsupported modes */
955 assert(ctx
->rasterizer
!= NULL
);
957 if (!(ctx
->draw_modes
& (1 << mode
))) {
958 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
959 mode
= PIPE_PRIM_TRIANGLE_FAN
;
961 if (info
->count
< 4) {
962 /* Degenerate case? */
966 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
967 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
972 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
973 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
975 /* Now that we have a guaranteed terminating path, find the job.
976 * Assignment commented out to prevent unused warning */
978 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
980 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
982 /* Take into account a negative bias */
983 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
984 ctx
->instance_count
= info
->instance_count
;
985 ctx
->active_prim
= info
->mode
;
987 /* For non-indexed draws, they're the same */
988 unsigned vertex_count
= ctx
->vertex_count
;
990 unsigned draw_flags
= 0;
992 /* The draw flags interpret how primitive size is interpreted */
994 if (panfrost_writes_point_size(ctx
))
995 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
997 if (info
->primitive_restart
)
998 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1000 /* These doesn't make much sense */
1002 draw_flags
|= 0x3000;
1004 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1005 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1007 panfrost_statistics_record(ctx
, info
);
1009 if (info
->index_size
) {
1010 unsigned min_index
= 0, max_index
= 0;
1011 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
=
1012 panfrost_get_index_buffer_bounded(ctx
, info
, &min_index
, &max_index
);
1014 /* Use the corresponding values */
1015 vertex_count
= max_index
- min_index
+ 1;
1016 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1017 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1019 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1020 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1022 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1024 /* Index count == vertex count, if no indexing is applied, as
1025 * if it is internally indexed in the expected order */
1027 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1028 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1030 /* Reverse index state */
1031 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
1034 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1035 * vertex_count, 1) */
1037 panfrost_pack_work_groups_fused(
1038 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1039 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1040 1, vertex_count
, info
->instance_count
,
1043 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1045 /* Encode the padded vertex count */
1047 if (info
->instance_count
> 1) {
1048 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1050 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1051 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1053 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1054 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1056 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1057 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1059 ctx
->padded_count
= vertex_count
;
1061 /* Reset instancing state */
1062 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1063 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1064 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1065 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1068 /* Fire off the draw itself */
1069 panfrost_queue_draw(ctx
);
1071 /* Increment transform feedback offsets */
1073 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1074 unsigned output_count
= u_stream_outputs_for_vertices(
1075 ctx
->active_prim
, ctx
->vertex_count
);
1077 ctx
->streamout
.offsets
[i
] += output_count
;
1084 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1090 panfrost_create_rasterizer_state(
1091 struct pipe_context
*pctx
,
1092 const struct pipe_rasterizer_state
*cso
)
1094 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1102 panfrost_bind_rasterizer_state(
1103 struct pipe_context
*pctx
,
1106 struct panfrost_context
*ctx
= pan_context(pctx
);
1108 ctx
->rasterizer
= hwcso
;
1113 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1114 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1116 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1117 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1119 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1121 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1122 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1124 /* Point sprites are emulated */
1126 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
1128 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1129 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1133 panfrost_create_vertex_elements_state(
1134 struct pipe_context
*pctx
,
1135 unsigned num_elements
,
1136 const struct pipe_vertex_element
*elements
)
1138 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1140 so
->num_elements
= num_elements
;
1141 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1143 for (int i
= 0; i
< num_elements
; ++i
) {
1144 so
->hw
[i
].index
= i
;
1146 enum pipe_format fmt
= elements
[i
].src_format
;
1147 const struct util_format_description
*desc
= util_format_description(fmt
);
1148 so
->hw
[i
].unknown1
= 0x2;
1149 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1151 so
->hw
[i
].format
= panfrost_find_format(desc
);
1153 /* The field itself should probably be shifted over */
1154 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1161 panfrost_bind_vertex_elements_state(
1162 struct pipe_context
*pctx
,
1165 struct panfrost_context
*ctx
= pan_context(pctx
);
1166 ctx
->vertex
= hwcso
;
1170 panfrost_create_shader_state(
1171 struct pipe_context
*pctx
,
1172 const struct pipe_shader_state
*cso
,
1173 enum pipe_shader_type stage
)
1175 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1178 /* Token deep copy to prevent memory corruption */
1180 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1181 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1183 /* Precompile for shader-db if we need to */
1184 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1185 struct panfrost_context
*ctx
= pan_context(pctx
);
1187 struct mali_shader_meta meta
;
1188 struct panfrost_shader_state state
;
1189 uint64_t outputs_written
;
1191 panfrost_shader_compile(ctx
, &meta
,
1194 tgsi_processor_to_shader_stage(stage
), &state
,
1202 panfrost_delete_shader_state(
1203 struct pipe_context
*pctx
,
1206 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1208 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1209 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1212 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1213 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1214 panfrost_bo_unreference(shader_state
->bo
);
1215 shader_state
->bo
= NULL
;
1217 free(cso
->variants
);
1223 panfrost_create_sampler_state(
1224 struct pipe_context
*pctx
,
1225 const struct pipe_sampler_state
*cso
)
1227 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1230 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1232 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1233 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1234 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1236 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1237 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1238 unsigned mip_filter
= mip_linear
?
1239 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1240 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1242 struct mali_sampler_descriptor sampler_descriptor
= {
1243 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1244 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1245 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1246 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1247 .compare_func
= panfrost_flip_compare_func(
1248 panfrost_translate_compare_func(
1249 cso
->compare_func
)),
1251 cso
->border_color
.f
[0],
1252 cso
->border_color
.f
[1],
1253 cso
->border_color
.f
[2],
1254 cso
->border_color
.f
[3]
1256 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1257 .max_lod
= FIXED_16(cso
->max_lod
, false),
1258 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1259 .seamless_cube_map
= cso
->seamless_cube_map
,
1262 /* If necessary, we disable mipmapping in the sampler descriptor by
1263 * clamping the LOD as tight as possible (from 0 to epsilon,
1264 * essentially -- remember these are fixed point numbers, so
1267 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
1268 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1270 /* Enforce that there is something in the middle by adding epsilon*/
1272 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1273 sampler_descriptor
.max_lod
++;
1276 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1279 so
->hw
= sampler_descriptor
;
1285 panfrost_bind_sampler_states(
1286 struct pipe_context
*pctx
,
1287 enum pipe_shader_type shader
,
1288 unsigned start_slot
, unsigned num_sampler
,
1291 assert(start_slot
== 0);
1293 struct panfrost_context
*ctx
= pan_context(pctx
);
1295 /* XXX: Should upload, not just copy? */
1296 ctx
->sampler_count
[shader
] = num_sampler
;
1297 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1301 panfrost_variant_matches(
1302 struct panfrost_context
*ctx
,
1303 struct panfrost_shader_state
*variant
,
1304 enum pipe_shader_type type
)
1306 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1307 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1309 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1311 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1312 /* Make sure enable state is at least the same */
1313 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1317 /* Check that the contents of the test are the same */
1318 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1319 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1321 if (!(same_func
&& same_ref
)) {
1326 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1327 variant
->point_sprite_mask
)) {
1328 /* Ensure the same varyings are turned to point sprites */
1329 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1332 /* Ensure the orientation is correct */
1334 rasterizer
->sprite_coord_mode
==
1335 PIPE_SPRITE_COORD_UPPER_LEFT
;
1337 if (variant
->point_sprite_upper_left
!= upper_left
)
1341 /* Otherwise, we're good to go */
1346 * Fix an uncompiled shader's stream output info, and produce a bitmask
1347 * of which VARYING_SLOT_* are captured for stream output.
1349 * Core Gallium stores output->register_index as a "slot" number, where
1350 * slots are assigned consecutively to all outputs in info->outputs_written.
1351 * This naive packing of outputs doesn't work for us - we too have slots,
1352 * but the layout is defined by the VUE map, which we won't have until we
1353 * compile a specific shader variant. So, we remap these and simply store
1354 * VARYING_SLOT_* in our copy's output->register_index fields.
1356 * We then produce a bitmask of outputs which are used for SO.
1358 * Implementation from iris.
1362 update_so_info(struct pipe_stream_output_info
*so_info
,
1363 uint64_t outputs_written
)
1365 uint64_t so_outputs
= 0;
1366 uint8_t reverse_map
[64] = {0};
1369 while (outputs_written
)
1370 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1372 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1373 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1375 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1376 output
->register_index
= reverse_map
[output
->register_index
];
1378 so_outputs
|= 1ull << output
->register_index
;
1385 panfrost_bind_shader_state(
1386 struct pipe_context
*pctx
,
1388 enum pipe_shader_type type
)
1390 struct panfrost_context
*ctx
= pan_context(pctx
);
1391 ctx
->shader
[type
] = hwcso
;
1395 /* Match the appropriate variant */
1397 signed variant
= -1;
1398 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1400 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1401 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1407 if (variant
== -1) {
1408 /* No variant matched, so create a new one */
1409 variant
= variants
->variant_count
++;
1411 if (variants
->variant_count
> variants
->variant_space
) {
1412 unsigned old_space
= variants
->variant_space
;
1414 variants
->variant_space
*= 2;
1415 if (variants
->variant_space
== 0)
1416 variants
->variant_space
= 1;
1418 /* Arbitrary limit to stop runaway programs from
1419 * creating an unbounded number of shader variants. */
1420 assert(variants
->variant_space
< 1024);
1422 unsigned msize
= sizeof(struct panfrost_shader_state
);
1423 variants
->variants
= realloc(variants
->variants
,
1424 variants
->variant_space
* msize
);
1426 memset(&variants
->variants
[old_space
], 0,
1427 (variants
->variant_space
- old_space
) * msize
);
1430 struct panfrost_shader_state
*v
=
1431 &variants
->variants
[variant
];
1433 if (type
== PIPE_SHADER_FRAGMENT
) {
1434 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1436 if (ctx
->rasterizer
) {
1437 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1438 v
->point_sprite_upper_left
=
1439 ctx
->rasterizer
->base
.sprite_coord_mode
==
1440 PIPE_SPRITE_COORD_UPPER_LEFT
;
1444 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1448 /* Select this variant */
1449 variants
->active_variant
= variant
;
1451 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1452 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1454 /* We finally have a variant, so compile it */
1456 if (!shader_state
->compiled
) {
1457 uint64_t outputs_written
= 0;
1459 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1460 variants
->base
.type
,
1461 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1462 variants
->base
.ir
.nir
:
1463 variants
->base
.tokens
,
1464 tgsi_processor_to_shader_stage(type
), shader_state
,
1467 shader_state
->compiled
= true;
1469 /* Fixup the stream out information, since what Gallium returns
1470 * normally is mildly insane */
1472 shader_state
->stream_output
= variants
->base
.stream_output
;
1473 shader_state
->so_mask
=
1474 update_so_info(&shader_state
->stream_output
, outputs_written
);
1479 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1481 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1485 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1487 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1491 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1493 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1497 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1499 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1503 panfrost_set_vertex_buffers(
1504 struct pipe_context
*pctx
,
1505 unsigned start_slot
,
1506 unsigned num_buffers
,
1507 const struct pipe_vertex_buffer
*buffers
)
1509 struct panfrost_context
*ctx
= pan_context(pctx
);
1511 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1515 panfrost_set_constant_buffer(
1516 struct pipe_context
*pctx
,
1517 enum pipe_shader_type shader
, uint index
,
1518 const struct pipe_constant_buffer
*buf
)
1520 struct panfrost_context
*ctx
= pan_context(pctx
);
1521 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1523 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
1525 unsigned mask
= (1 << index
);
1527 if (unlikely(!buf
)) {
1528 pbuf
->enabled_mask
&= ~mask
;
1529 pbuf
->dirty_mask
&= ~mask
;
1533 pbuf
->enabled_mask
|= mask
;
1534 pbuf
->dirty_mask
|= mask
;
1538 panfrost_set_stencil_ref(
1539 struct pipe_context
*pctx
,
1540 const struct pipe_stencil_ref
*ref
)
1542 struct panfrost_context
*ctx
= pan_context(pctx
);
1543 ctx
->stencil_ref
= *ref
;
1546 static enum mali_texture_type
1547 panfrost_translate_texture_type(enum pipe_texture_target t
) {
1551 case PIPE_TEXTURE_1D
:
1552 case PIPE_TEXTURE_1D_ARRAY
:
1555 case PIPE_TEXTURE_2D
:
1556 case PIPE_TEXTURE_2D_ARRAY
:
1557 case PIPE_TEXTURE_RECT
:
1560 case PIPE_TEXTURE_3D
:
1563 case PIPE_TEXTURE_CUBE
:
1564 case PIPE_TEXTURE_CUBE_ARRAY
:
1565 return MALI_TEX_CUBE
;
1568 unreachable("Unknown target");
1572 static struct pipe_sampler_view
*
1573 panfrost_create_sampler_view(
1574 struct pipe_context
*pctx
,
1575 struct pipe_resource
*texture
,
1576 const struct pipe_sampler_view
*template)
1578 struct panfrost_screen
*screen
= pan_screen(pctx
->screen
);
1579 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
1581 pipe_reference(NULL
, &texture
->reference
);
1583 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1586 so
->base
= *template;
1587 so
->base
.texture
= texture
;
1588 so
->base
.reference
.count
= 1;
1589 so
->base
.context
= pctx
;
1591 unsigned char user_swizzle
[4] = {
1592 template->swizzle_r
,
1593 template->swizzle_g
,
1594 template->swizzle_b
,
1598 /* In the hardware, array_size refers specifically to array textures,
1599 * whereas in Gallium, it also covers cubemaps */
1601 unsigned array_size
= texture
->array_size
;
1603 if (template->target
== PIPE_TEXTURE_CUBE
) {
1604 /* TODO: Cubemap arrays */
1605 assert(array_size
== 6);
1609 enum mali_texture_type type
=
1610 panfrost_translate_texture_type(template->target
);
1612 unsigned size
= panfrost_estimate_texture_size(
1613 template->u
.tex
.first_level
,
1614 template->u
.tex
.last_level
,
1615 template->u
.tex
.first_layer
,
1616 template->u
.tex
.last_layer
,
1617 type
, prsrc
->layout
);
1619 so
->bo
= panfrost_bo_create(screen
, size
, 0);
1621 panfrost_new_texture(
1623 texture
->width0
, texture
->height0
,
1624 texture
->depth0
, array_size
,
1626 type
, prsrc
->layout
,
1627 template->u
.tex
.first_level
,
1628 template->u
.tex
.last_level
,
1629 template->u
.tex
.first_layer
,
1630 template->u
.tex
.last_layer
,
1631 prsrc
->cubemap_stride
,
1632 panfrost_translate_swizzle_4(user_swizzle
),
1636 return (struct pipe_sampler_view
*) so
;
1640 panfrost_set_sampler_views(
1641 struct pipe_context
*pctx
,
1642 enum pipe_shader_type shader
,
1643 unsigned start_slot
, unsigned num_views
,
1644 struct pipe_sampler_view
**views
)
1646 struct panfrost_context
*ctx
= pan_context(pctx
);
1647 unsigned new_nr
= 0;
1650 assert(start_slot
== 0);
1652 for (i
= 0; i
< num_views
; ++i
) {
1655 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1659 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1660 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1663 ctx
->sampler_view_count
[shader
] = new_nr
;
1667 panfrost_sampler_view_destroy(
1668 struct pipe_context
*pctx
,
1669 struct pipe_sampler_view
*pview
)
1671 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1673 pipe_resource_reference(&pview
->texture
, NULL
);
1674 panfrost_bo_unreference(view
->bo
);
1679 panfrost_set_shader_buffers(
1680 struct pipe_context
*pctx
,
1681 enum pipe_shader_type shader
,
1682 unsigned start
, unsigned count
,
1683 const struct pipe_shader_buffer
*buffers
,
1684 unsigned writable_bitmask
)
1686 struct panfrost_context
*ctx
= pan_context(pctx
);
1688 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1689 buffers
, start
, count
);
1692 /* Hints that a framebuffer should use AFBC where possible */
1696 struct panfrost_screen
*screen
,
1697 const struct pipe_framebuffer_state
*fb
)
1699 /* AFBC implemenation incomplete; hide it */
1700 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
1702 /* Hint AFBC to the resources bound to each color buffer */
1704 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
1705 struct pipe_surface
*surf
= fb
->cbufs
[i
];
1706 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1707 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1710 /* Also hint it to the depth buffer */
1713 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
1714 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1719 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1720 const struct pipe_framebuffer_state
*fb
)
1722 struct panfrost_context
*ctx
= pan_context(pctx
);
1724 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
1725 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1727 panfrost_invalidate_frame(ctx
);
1731 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1732 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
1734 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
1738 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1741 struct panfrost_context
*ctx
= pan_context(pipe
);
1742 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
1743 ctx
->depth_stencil
= depth_stencil
;
1748 /* Alpha does not exist in the hardware (it's not in ES3), so it's
1749 * emulated in the fragment shader */
1751 if (depth_stencil
->alpha
.enabled
) {
1752 /* We need to trigger a new shader (maybe) */
1753 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1757 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
1759 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
1760 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
1762 /* If back-stencil is not enabled, use the front values */
1763 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1764 unsigned back_index
= back_enab
? 1 : 0;
1766 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
1767 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
1769 /* Depth state (TODO: Refactor) */
1770 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
1771 depth_stencil
->depth
.writemask
);
1773 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
1775 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
1776 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
1778 /* Bounds test not implemented */
1779 assert(!depth_stencil
->depth
.bounds_test
);
1783 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1789 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1790 unsigned sample_mask
)
1795 panfrost_set_clip_state(struct pipe_context
*pipe
,
1796 const struct pipe_clip_state
*clip
)
1798 //struct panfrost_context *panfrost = pan_context(pipe);
1802 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1803 unsigned start_slot
,
1804 unsigned num_viewports
,
1805 const struct pipe_viewport_state
*viewports
)
1807 struct panfrost_context
*ctx
= pan_context(pipe
);
1809 assert(start_slot
== 0);
1810 assert(num_viewports
== 1);
1812 ctx
->pipe_viewport
= *viewports
;
1816 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1817 unsigned start_slot
,
1818 unsigned num_scissors
,
1819 const struct pipe_scissor_state
*scissors
)
1821 struct panfrost_context
*ctx
= pan_context(pipe
);
1823 assert(start_slot
== 0);
1824 assert(num_scissors
== 1);
1826 ctx
->scissor
= *scissors
;
1830 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1831 const struct pipe_poly_stipple
*stipple
)
1833 //struct panfrost_context *panfrost = pan_context(pipe);
1837 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1840 struct panfrost_context
*ctx
= pan_context(pipe
);
1841 ctx
->active_queries
= enable
;
1845 panfrost_destroy(struct pipe_context
*pipe
)
1847 struct panfrost_context
*panfrost
= pan_context(pipe
);
1849 if (panfrost
->blitter
)
1850 util_blitter_destroy(panfrost
->blitter
);
1852 if (panfrost
->blitter_wallpaper
)
1853 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1855 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1856 u_upload_destroy(pipe
->stream_uploader
);
1861 static struct pipe_query
*
1862 panfrost_create_query(struct pipe_context
*pipe
,
1866 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1871 return (struct pipe_query
*) q
;
1875 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1877 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1880 panfrost_bo_unreference(query
->bo
);
1888 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1890 struct panfrost_context
*ctx
= pan_context(pipe
);
1891 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1893 switch (query
->type
) {
1894 case PIPE_QUERY_OCCLUSION_COUNTER
:
1895 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1896 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1897 /* Allocate a bo for the query results to be stored */
1899 query
->bo
= panfrost_bo_create(
1900 pan_screen(ctx
->base
.screen
),
1901 sizeof(unsigned), 0);
1904 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1905 *result
= 0; /* Default to 0 if nothing at all drawn. */
1906 ctx
->occlusion_query
= query
;
1909 /* Geometry statistics are computed in the driver. XXX: geom/tess
1912 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1913 query
->start
= ctx
->prims_generated
;
1915 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1916 query
->start
= ctx
->tf_prims_generated
;
1920 DBG("Skipping query %u\n", query
->type
);
1928 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1930 struct panfrost_context
*ctx
= pan_context(pipe
);
1931 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1933 switch (query
->type
) {
1934 case PIPE_QUERY_OCCLUSION_COUNTER
:
1935 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1936 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1937 ctx
->occlusion_query
= NULL
;
1939 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1940 query
->end
= ctx
->prims_generated
;
1942 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1943 query
->end
= ctx
->tf_prims_generated
;
1951 panfrost_get_query_result(struct pipe_context
*pipe
,
1952 struct pipe_query
*q
,
1954 union pipe_query_result
*vresult
)
1956 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1957 struct panfrost_context
*ctx
= pan_context(pipe
);
1960 switch (query
->type
) {
1961 case PIPE_QUERY_OCCLUSION_COUNTER
:
1962 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1963 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1965 panfrost_flush_all_batches(ctx
, true);
1967 /* Read back the query results */
1968 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1969 unsigned passed
= *result
;
1971 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1972 vresult
->u64
= passed
;
1974 vresult
->b
= !!passed
;
1979 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1980 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1981 panfrost_flush_all_batches(ctx
, true);
1982 vresult
->u64
= query
->end
- query
->start
;
1986 DBG("Skipped query get %u\n", query
->type
);
1993 static struct pipe_stream_output_target
*
1994 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1995 struct pipe_resource
*prsc
,
1996 unsigned buffer_offset
,
1997 unsigned buffer_size
)
1999 struct pipe_stream_output_target
*target
;
2001 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2006 pipe_reference_init(&target
->reference
, 1);
2007 pipe_resource_reference(&target
->buffer
, prsc
);
2009 target
->context
= pctx
;
2010 target
->buffer_offset
= buffer_offset
;
2011 target
->buffer_size
= buffer_size
;
2017 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2018 struct pipe_stream_output_target
*target
)
2020 pipe_resource_reference(&target
->buffer
, NULL
);
2021 ralloc_free(target
);
2025 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2026 unsigned num_targets
,
2027 struct pipe_stream_output_target
**targets
,
2028 const unsigned *offsets
)
2030 struct panfrost_context
*ctx
= pan_context(pctx
);
2031 struct panfrost_streamout
*so
= &ctx
->streamout
;
2033 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2035 for (unsigned i
= 0; i
< num_targets
; i
++) {
2036 if (offsets
[i
] != -1)
2037 so
->offsets
[i
] = offsets
[i
];
2039 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2042 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2043 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2045 so
->num_targets
= num_targets
;
2048 struct pipe_context
*
2049 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2051 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2052 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2054 gallium
->screen
= screen
;
2056 gallium
->destroy
= panfrost_destroy
;
2058 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2060 gallium
->flush
= panfrost_flush
;
2061 gallium
->clear
= panfrost_clear
;
2062 gallium
->draw_vbo
= panfrost_draw_vbo
;
2064 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2065 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2066 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2068 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2070 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2071 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2072 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2074 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2075 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2076 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2078 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2079 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2080 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2082 gallium
->create_fs_state
= panfrost_create_fs_state
;
2083 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2084 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2086 gallium
->create_vs_state
= panfrost_create_vs_state
;
2087 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2088 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2090 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2091 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2092 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2094 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2095 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2096 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2098 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2100 gallium
->set_clip_state
= panfrost_set_clip_state
;
2101 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2102 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2103 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2104 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2106 gallium
->create_query
= panfrost_create_query
;
2107 gallium
->destroy_query
= panfrost_destroy_query
;
2108 gallium
->begin_query
= panfrost_begin_query
;
2109 gallium
->end_query
= panfrost_end_query
;
2110 gallium
->get_query_result
= panfrost_get_query_result
;
2112 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2113 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2114 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2116 panfrost_resource_context_init(gallium
);
2117 panfrost_blend_context_init(gallium
);
2118 panfrost_compute_context_init(gallium
);
2121 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2122 gallium
->const_uploader
= gallium
->stream_uploader
;
2123 assert(gallium
->stream_uploader
);
2125 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2126 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2128 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2130 ctx
->blitter
= util_blitter_create(gallium
);
2131 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2133 assert(ctx
->blitter
);
2134 assert(ctx
->blitter_wallpaper
);
2136 /* Prepare for render! */
2138 panfrost_batch_init(ctx
);
2139 panfrost_emit_vertex_payload(ctx
);
2140 panfrost_invalidate_frame(ctx
);
2141 panfrost_default_shader_backend(ctx
);