2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
56 #include "pandecode/decode.h"
58 struct midgard_tiler_descriptor
59 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
61 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
62 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
63 struct midgard_tiler_descriptor t
= {0};
64 unsigned height
= batch
->key
.height
;
65 unsigned width
= batch
->key
.width
;
68 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
70 /* Compute the polygon header size and use that to offset the body */
72 unsigned header_size
= panfrost_tiler_header_size(
73 width
, height
, t
.hierarchy_mask
, hierarchy
);
75 t
.polygon_list_size
= panfrost_tiler_full_size(
76 width
, height
, t
.hierarchy_mask
, hierarchy
);
81 struct panfrost_bo
*tiler_heap
;
83 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
84 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
89 /* Allow the entire tiler heap */
90 t
.heap_start
= tiler_heap
->gpu
;
91 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
93 struct panfrost_bo
*tiler_dummy
;
95 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
96 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
98 /* The tiler is disabled, so don't allow the tiler heap */
99 t
.heap_start
= tiler_dummy
->gpu
;
100 t
.heap_end
= t
.heap_start
;
102 /* Use a dummy polygon list */
103 t
.polygon_list
= tiler_dummy
->gpu
;
105 /* Disable the tiler */
107 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
109 t
.hierarchy_mask
= MALI_TILER_USER
;
110 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
112 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
113 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
114 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
118 t
.polygon_list_body
=
119 t
.polygon_list
+ header_size
;
126 struct pipe_context
*pipe
,
128 const struct pipe_scissor_state
*scissor_state
,
129 const union pipe_color_union
*color
,
130 double depth
, unsigned stencil
)
132 struct panfrost_context
*ctx
= pan_context(pipe
);
134 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
135 * the existing batch targeting this FBO has draws. We could probably
136 * avoid that by replacing plain clears by quad-draws with a specific
137 * color/depth/stencil value, thus avoiding the generation of extra
140 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
142 panfrost_batch_add_fbo_bos(batch
);
143 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
146 /* Reset per-frame context, called on context initialisation as well as after
147 * flushing a frame */
150 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
152 /* TODO: When does this need to be handled? */
153 ctx
->active_queries
= true;
157 panfrost_writes_point_size(struct panfrost_context
*ctx
)
159 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
160 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
162 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
166 panfrost_vertex_state_upd_attr_offs(struct panfrost_context
*ctx
,
167 struct mali_vertex_tiler_postfix
*vertex_postfix
)
172 struct panfrost_vertex_state
*so
= ctx
->vertex
;
174 /* Fixup offsets for the second pass. Recall that the hardware
175 * calculates attribute addresses as:
177 * addr = base + (stride * vtx) + src_offset;
179 * However, on Mali, base must be aligned to 64-bytes, so we
182 * base' = base & ~63 = base - (base & 63)
184 * To compensate when using base' (see emit_vertex_data), we have
185 * to adjust src_offset by the masked off piece:
187 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
188 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
189 * = base + (stride * vtx) + src_offset
195 unsigned start
= vertex_postfix
->offset_start
;
197 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
198 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
199 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
201 /* Adjust by the masked off bits of the offset. Make sure we
202 * read src_offset from so->hw (which is not GPU visible)
203 * rather than target (which is) due to caching effects */
205 unsigned src_offset
= so
->pipe
[i
].src_offset
;
207 /* BOs aligned to 4k so guaranteed aligned to 64 */
208 src_offset
+= (buf
->buffer_offset
& 63);
210 /* Also, somewhat obscurely per-instance data needs to be
211 * offset in response to a delayed start in an indexed draw */
213 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
214 src_offset
-= buf
->stride
* start
;
216 so
->hw
[i
].src_offset
= src_offset
;
220 /* Compute number of UBOs active (more specifically, compute the highest UBO
221 * number addressable -- if there are gaps, include them in the count anyway).
222 * We always include UBO #0 in the count, since we *need* uniforms enabled for
226 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
228 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
229 return 32 - __builtin_clz(mask
);
232 /* The entire frame is in memory -- send it off to the kernel! */
236 struct pipe_context
*pipe
,
237 struct pipe_fence_handle
**fence
,
240 struct panfrost_context
*ctx
= pan_context(pipe
);
241 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
242 struct util_dynarray fences
;
244 /* We must collect the fences before the flush is done, otherwise we'll
245 * lose track of them.
248 util_dynarray_init(&fences
, NULL
);
249 hash_table_foreach(ctx
->batches
, hentry
) {
250 struct panfrost_batch
*batch
= hentry
->data
;
252 panfrost_batch_fence_reference(batch
->out_sync
);
253 util_dynarray_append(&fences
,
254 struct panfrost_batch_fence
*,
259 /* Submit all pending jobs */
260 panfrost_flush_all_batches(ctx
, false);
263 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
264 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
265 *fence
= (struct pipe_fence_handle
*)f
;
267 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
268 panfrost_batch_fence_unreference(*fence
);
270 util_dynarray_fini(&fences
);
273 if (dev
->debug
& PAN_DBG_TRACE
)
274 pandecode_next_frame();
277 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
280 g2m_draw_mode(enum pipe_prim_type mode
)
285 DEFINE_CASE(LINE_LOOP
);
286 DEFINE_CASE(LINE_STRIP
);
287 DEFINE_CASE(TRIANGLES
);
288 DEFINE_CASE(TRIANGLE_STRIP
);
289 DEFINE_CASE(TRIANGLE_FAN
);
291 DEFINE_CASE(QUAD_STRIP
);
292 DEFINE_CASE(POLYGON
);
295 unreachable("Invalid draw mode");
302 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
304 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
306 /* Check if we're scissoring at all */
308 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
311 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
314 /* Count generated primitives (when there is no geom/tess shaders) for
315 * transform feedback */
318 panfrost_statistics_record(
319 struct panfrost_context
*ctx
,
320 const struct pipe_draw_info
*info
)
322 if (!ctx
->active_queries
)
325 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
326 ctx
->prims_generated
+= prims
;
328 if (!ctx
->streamout
.num_targets
)
331 ctx
->tf_prims_generated
+= prims
;
335 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
337 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
340 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
342 ctx
->streamout
.offsets
[i
] += count
;
348 struct pipe_context
*pipe
,
349 const struct pipe_draw_info
*info
)
351 struct panfrost_context
*ctx
= pan_context(pipe
);
353 /* First of all, check the scissor to see if anything is drawn at all.
354 * If it's not, we drop the draw (mostly a conformance issue;
355 * well-behaved apps shouldn't hit this) */
357 if (panfrost_scissor_culls_everything(ctx
))
360 int mode
= info
->mode
;
362 /* Fallback unsupported restart index */
363 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
365 if (info
->primitive_restart
&& info
->index_size
366 && info
->restart_index
!= primitive_index
) {
367 util_draw_vbo_without_prim_restart(pipe
, info
);
371 /* Fallback for unsupported modes */
373 assert(ctx
->rasterizer
!= NULL
);
375 if (!(ctx
->draw_modes
& (1 << mode
))) {
376 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
377 mode
= PIPE_PRIM_TRIANGLE_FAN
;
379 if (info
->count
< 4) {
380 /* Degenerate case? */
384 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
385 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
390 /* Now that we have a guaranteed terminating path, find the job.
391 * Assignment commented out to prevent unused warning */
393 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
395 panfrost_batch_add_fbo_bos(batch
);
396 panfrost_batch_set_requirements(batch
);
398 /* Take into account a negative bias */
399 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
400 ctx
->instance_count
= info
->instance_count
;
401 ctx
->active_prim
= info
->mode
;
403 struct mali_vertex_tiler_prefix vertex_prefix
, tiler_prefix
;
404 struct mali_vertex_tiler_postfix vertex_postfix
, tiler_postfix
;
405 union midgard_primitive_size primitive_size
;
406 unsigned vertex_count
;
408 panfrost_vt_init(ctx
, PIPE_SHADER_VERTEX
, &vertex_prefix
, &vertex_postfix
);
409 panfrost_vt_init(ctx
, PIPE_SHADER_FRAGMENT
, &tiler_prefix
, &tiler_postfix
);
411 panfrost_vt_set_draw_info(ctx
, info
, g2m_draw_mode(mode
),
412 &vertex_postfix
, &tiler_prefix
,
413 &tiler_postfix
, &vertex_count
,
416 panfrost_statistics_record(ctx
, info
);
418 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
419 * vertex_count, 1) */
421 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
422 1, vertex_count
, info
->instance_count
,
425 /* Emit all sort of descriptors. */
426 panfrost_emit_vertex_data(batch
, &vertex_postfix
);
427 panfrost_emit_varying_descriptor(batch
,
430 &vertex_postfix
, &tiler_postfix
,
432 panfrost_emit_shader_meta(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
433 panfrost_emit_shader_meta(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
434 panfrost_emit_vertex_attr_meta(batch
, &vertex_postfix
);
435 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
436 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
437 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
438 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
439 panfrost_emit_const_buf(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
440 panfrost_emit_const_buf(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
441 panfrost_emit_viewport(batch
, &tiler_postfix
);
443 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
445 /* Fire off the draw itself */
446 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
447 &tiler_prefix
, &tiler_postfix
,
450 /* Adjust the batch stack size based on the new shader stack sizes. */
451 panfrost_batch_adjust_stack_size(batch
);
453 /* Increment transform feedback offsets */
454 panfrost_update_streamout_offsets(ctx
);
460 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
466 panfrost_create_rasterizer_state(
467 struct pipe_context
*pctx
,
468 const struct pipe_rasterizer_state
*cso
)
470 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
478 panfrost_bind_rasterizer_state(
479 struct pipe_context
*pctx
,
482 struct panfrost_context
*ctx
= pan_context(pctx
);
484 ctx
->rasterizer
= hwcso
;
489 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
490 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
492 /* Point sprites are emulated */
494 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
496 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
497 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
501 panfrost_create_vertex_elements_state(
502 struct pipe_context
*pctx
,
503 unsigned num_elements
,
504 const struct pipe_vertex_element
*elements
)
506 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
507 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
509 so
->num_elements
= num_elements
;
510 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
512 for (int i
= 0; i
< num_elements
; ++i
) {
515 enum pipe_format fmt
= elements
[i
].src_format
;
516 const struct util_format_description
*desc
= util_format_description(fmt
);
517 so
->hw
[i
].unknown1
= 0x2;
519 if (dev
->quirks
& HAS_SWIZZLES
)
520 so
->hw
[i
].swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
522 so
->hw
[i
].swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
524 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
525 so
->hw
[i
].format
= hw_format
;
529 /* Let's also prepare vertex builtins */
530 so
->hw
[PAN_VERTEX_ID
].format
= MALI_R32UI
;
531 if (dev
->quirks
& HAS_SWIZZLES
)
532 so
->hw
[PAN_VERTEX_ID
].swizzle
= panfrost_get_default_swizzle(1);
534 so
->hw
[PAN_VERTEX_ID
].swizzle
= panfrost_bifrost_swizzle(1);
536 so
->hw
[PAN_INSTANCE_ID
].format
= MALI_R32UI
;
537 if (dev
->quirks
& HAS_SWIZZLES
)
538 so
->hw
[PAN_INSTANCE_ID
].swizzle
= panfrost_get_default_swizzle(1);
540 so
->hw
[PAN_INSTANCE_ID
].swizzle
= panfrost_bifrost_swizzle(1);
546 panfrost_bind_vertex_elements_state(
547 struct pipe_context
*pctx
,
550 struct panfrost_context
*ctx
= pan_context(pctx
);
555 panfrost_create_shader_state(
556 struct pipe_context
*pctx
,
557 const struct pipe_shader_state
*cso
,
558 enum pipe_shader_type stage
)
560 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
561 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
564 /* Token deep copy to prevent memory corruption */
566 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
567 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
569 /* Precompile for shader-db if we need to */
570 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
571 struct panfrost_context
*ctx
= pan_context(pctx
);
573 struct panfrost_shader_state state
;
574 uint64_t outputs_written
;
576 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
578 tgsi_processor_to_shader_stage(stage
),
579 &state
, &outputs_written
);
586 panfrost_delete_shader_state(
587 struct pipe_context
*pctx
,
590 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
592 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
593 /* TODO: leaks TGSI tokens! */
596 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
597 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
598 panfrost_bo_unreference(shader_state
->bo
);
599 shader_state
->bo
= NULL
;
607 panfrost_create_sampler_state(
608 struct pipe_context
*pctx
,
609 const struct pipe_sampler_state
*cso
)
611 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
612 struct panfrost_device
*device
= pan_device(pctx
->screen
);
616 if (device
->quirks
& IS_BIFROST
)
617 panfrost_sampler_desc_init_bifrost(cso
, &so
->bifrost_hw
);
619 panfrost_sampler_desc_init(cso
, &so
->midgard_hw
);
625 panfrost_bind_sampler_states(
626 struct pipe_context
*pctx
,
627 enum pipe_shader_type shader
,
628 unsigned start_slot
, unsigned num_sampler
,
631 assert(start_slot
== 0);
633 struct panfrost_context
*ctx
= pan_context(pctx
);
635 /* XXX: Should upload, not just copy? */
636 ctx
->sampler_count
[shader
] = num_sampler
;
637 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
641 panfrost_variant_matches(
642 struct panfrost_context
*ctx
,
643 struct panfrost_shader_state
*variant
,
644 enum pipe_shader_type type
)
646 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
647 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
648 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
650 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
652 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
653 /* Make sure enable state is at least the same */
654 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
658 /* Check that the contents of the test are the same */
659 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
660 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
662 if (!(same_func
&& same_ref
)) {
667 /* Point sprites TODO on bifrost, always pass */
668 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
669 variant
->point_sprite_mask
)
670 && !(dev
->quirks
& IS_BIFROST
)) {
671 /* Ensure the same varyings are turned to point sprites */
672 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
675 /* Ensure the orientation is correct */
677 rasterizer
->sprite_coord_mode
==
678 PIPE_SPRITE_COORD_UPPER_LEFT
;
680 if (variant
->point_sprite_upper_left
!= upper_left
)
684 /* Otherwise, we're good to go */
689 * Fix an uncompiled shader's stream output info, and produce a bitmask
690 * of which VARYING_SLOT_* are captured for stream output.
692 * Core Gallium stores output->register_index as a "slot" number, where
693 * slots are assigned consecutively to all outputs in info->outputs_written.
694 * This naive packing of outputs doesn't work for us - we too have slots,
695 * but the layout is defined by the VUE map, which we won't have until we
696 * compile a specific shader variant. So, we remap these and simply store
697 * VARYING_SLOT_* in our copy's output->register_index fields.
699 * We then produce a bitmask of outputs which are used for SO.
701 * Implementation from iris.
705 update_so_info(struct pipe_stream_output_info
*so_info
,
706 uint64_t outputs_written
)
708 uint64_t so_outputs
= 0;
709 uint8_t reverse_map
[64] = {0};
712 while (outputs_written
)
713 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
715 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
716 struct pipe_stream_output
*output
= &so_info
->output
[i
];
718 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
719 output
->register_index
= reverse_map
[output
->register_index
];
721 so_outputs
|= 1ull << output
->register_index
;
728 panfrost_bind_shader_state(
729 struct pipe_context
*pctx
,
731 enum pipe_shader_type type
)
733 struct panfrost_context
*ctx
= pan_context(pctx
);
734 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
735 ctx
->shader
[type
] = hwcso
;
739 /* Match the appropriate variant */
742 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
744 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
745 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
752 /* No variant matched, so create a new one */
753 variant
= variants
->variant_count
++;
755 if (variants
->variant_count
> variants
->variant_space
) {
756 unsigned old_space
= variants
->variant_space
;
758 variants
->variant_space
*= 2;
759 if (variants
->variant_space
== 0)
760 variants
->variant_space
= 1;
762 /* Arbitrary limit to stop runaway programs from
763 * creating an unbounded number of shader variants. */
764 assert(variants
->variant_space
< 1024);
766 unsigned msize
= sizeof(struct panfrost_shader_state
);
767 variants
->variants
= realloc(variants
->variants
,
768 variants
->variant_space
* msize
);
770 memset(&variants
->variants
[old_space
], 0,
771 (variants
->variant_space
- old_space
) * msize
);
774 struct panfrost_shader_state
*v
=
775 &variants
->variants
[variant
];
777 if (type
== PIPE_SHADER_FRAGMENT
) {
778 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
780 /* Point sprites are TODO on Bifrost */
781 if (ctx
->rasterizer
&& !(dev
->quirks
& IS_BIFROST
)) {
782 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
783 v
->point_sprite_upper_left
=
784 ctx
->rasterizer
->base
.sprite_coord_mode
==
785 PIPE_SPRITE_COORD_UPPER_LEFT
;
790 /* Select this variant */
791 variants
->active_variant
= variant
;
793 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
794 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
796 /* We finally have a variant, so compile it */
798 if (!shader_state
->compiled
) {
799 uint64_t outputs_written
= 0;
801 panfrost_shader_compile(ctx
, variants
->base
.type
,
802 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
803 variants
->base
.ir
.nir
:
804 variants
->base
.tokens
,
805 tgsi_processor_to_shader_stage(type
),
809 shader_state
->compiled
= true;
811 /* Fixup the stream out information, since what Gallium returns
812 * normally is mildly insane */
814 shader_state
->stream_output
= variants
->base
.stream_output
;
815 shader_state
->so_mask
=
816 update_so_info(&shader_state
->stream_output
, outputs_written
);
821 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
823 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
827 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
829 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
833 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
835 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
839 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
841 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
845 panfrost_set_vertex_buffers(
846 struct pipe_context
*pctx
,
848 unsigned num_buffers
,
849 const struct pipe_vertex_buffer
*buffers
)
851 struct panfrost_context
*ctx
= pan_context(pctx
);
853 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
857 panfrost_set_constant_buffer(
858 struct pipe_context
*pctx
,
859 enum pipe_shader_type shader
, uint index
,
860 const struct pipe_constant_buffer
*buf
)
862 struct panfrost_context
*ctx
= pan_context(pctx
);
863 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
865 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
867 unsigned mask
= (1 << index
);
869 if (unlikely(!buf
)) {
870 pbuf
->enabled_mask
&= ~mask
;
871 pbuf
->dirty_mask
&= ~mask
;
875 pbuf
->enabled_mask
|= mask
;
876 pbuf
->dirty_mask
|= mask
;
880 panfrost_set_stencil_ref(
881 struct pipe_context
*pctx
,
882 const struct pipe_stencil_ref
*ref
)
884 struct panfrost_context
*ctx
= pan_context(pctx
);
885 ctx
->stencil_ref
= *ref
;
888 static enum mali_texture_type
889 panfrost_translate_texture_type(enum pipe_texture_target t
) {
893 case PIPE_TEXTURE_1D
:
894 case PIPE_TEXTURE_1D_ARRAY
:
897 case PIPE_TEXTURE_2D
:
898 case PIPE_TEXTURE_2D_ARRAY
:
899 case PIPE_TEXTURE_RECT
:
902 case PIPE_TEXTURE_3D
:
905 case PIPE_TEXTURE_CUBE
:
906 case PIPE_TEXTURE_CUBE_ARRAY
:
907 return MALI_TEX_CUBE
;
910 unreachable("Unknown target");
915 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
916 struct pipe_context
*pctx
,
917 struct pipe_resource
*texture
)
919 struct panfrost_device
*device
= pan_device(pctx
->screen
);
920 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
923 so
->texture_bo
= prsrc
->bo
->gpu
;
924 so
->layout
= prsrc
->layout
;
926 unsigned char user_swizzle
[4] = {
933 /* In the hardware, array_size refers specifically to array textures,
934 * whereas in Gallium, it also covers cubemaps */
936 unsigned array_size
= texture
->array_size
;
937 unsigned depth
= texture
->depth0
;
939 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
940 /* TODO: Cubemap arrays */
941 assert(array_size
== 6);
945 /* MSAA only supported for 2D textures (and 2D texture arrays via an
946 * extension currently unimplemented */
948 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
950 depth
= texture
->nr_samples
;
952 /* MSAA only supported for 2D textures */
953 assert(texture
->nr_samples
<= 1);
956 enum mali_texture_type type
=
957 panfrost_translate_texture_type(so
->base
.target
);
959 if (device
->quirks
& IS_BIFROST
) {
960 const struct util_format_description
*desc
=
961 util_format_description(so
->base
.format
);
962 unsigned char composed_swizzle
[4];
963 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
965 unsigned size
= panfrost_estimate_texture_payload_size(
966 so
->base
.u
.tex
.first_level
,
967 so
->base
.u
.tex
.last_level
,
968 so
->base
.u
.tex
.first_layer
,
969 so
->base
.u
.tex
.last_layer
,
970 type
, prsrc
->layout
);
972 so
->bo
= pan_bo_create(device
, size
, 0);
974 so
->bifrost_descriptor
= rzalloc(pctx
, struct bifrost_texture_descriptor
);
975 panfrost_new_texture_bifrost(
976 so
->bifrost_descriptor
,
977 texture
->width0
, texture
->height0
,
981 so
->base
.u
.tex
.first_level
,
982 so
->base
.u
.tex
.last_level
,
983 so
->base
.u
.tex
.first_layer
,
984 so
->base
.u
.tex
.last_layer
,
986 prsrc
->cubemap_stride
,
987 panfrost_translate_swizzle_4(composed_swizzle
),
992 unsigned size
= panfrost_estimate_texture_payload_size(
993 so
->base
.u
.tex
.first_level
,
994 so
->base
.u
.tex
.last_level
,
995 so
->base
.u
.tex
.first_layer
,
996 so
->base
.u
.tex
.last_layer
,
997 type
, prsrc
->layout
);
998 size
+= sizeof(struct mali_texture_descriptor
);
1000 so
->bo
= pan_bo_create(device
, size
, 0);
1002 panfrost_new_texture(
1004 texture
->width0
, texture
->height0
,
1007 type
, prsrc
->layout
,
1008 so
->base
.u
.tex
.first_level
,
1009 so
->base
.u
.tex
.last_level
,
1010 so
->base
.u
.tex
.first_layer
,
1011 so
->base
.u
.tex
.last_layer
,
1012 texture
->nr_samples
,
1013 prsrc
->cubemap_stride
,
1014 panfrost_translate_swizzle_4(user_swizzle
),
1020 static struct pipe_sampler_view
*
1021 panfrost_create_sampler_view(
1022 struct pipe_context
*pctx
,
1023 struct pipe_resource
*texture
,
1024 const struct pipe_sampler_view
*template)
1026 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
1028 pipe_reference(NULL
, &texture
->reference
);
1030 so
->base
= *template;
1031 so
->base
.texture
= texture
;
1032 so
->base
.reference
.count
= 1;
1033 so
->base
.context
= pctx
;
1035 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
1037 return (struct pipe_sampler_view
*) so
;
1041 panfrost_set_sampler_views(
1042 struct pipe_context
*pctx
,
1043 enum pipe_shader_type shader
,
1044 unsigned start_slot
, unsigned num_views
,
1045 struct pipe_sampler_view
**views
)
1047 struct panfrost_context
*ctx
= pan_context(pctx
);
1048 unsigned new_nr
= 0;
1051 assert(start_slot
== 0);
1053 for (i
= 0; i
< num_views
; ++i
) {
1056 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1060 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1061 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1064 ctx
->sampler_view_count
[shader
] = new_nr
;
1068 panfrost_sampler_view_destroy(
1069 struct pipe_context
*pctx
,
1070 struct pipe_sampler_view
*pview
)
1072 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1074 pipe_resource_reference(&pview
->texture
, NULL
);
1075 panfrost_bo_unreference(view
->bo
);
1076 if (view
->bifrost_descriptor
)
1077 ralloc_free(view
->bifrost_descriptor
);
1082 panfrost_set_shader_buffers(
1083 struct pipe_context
*pctx
,
1084 enum pipe_shader_type shader
,
1085 unsigned start
, unsigned count
,
1086 const struct pipe_shader_buffer
*buffers
,
1087 unsigned writable_bitmask
)
1089 struct panfrost_context
*ctx
= pan_context(pctx
);
1091 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1092 buffers
, start
, count
);
1095 /* Hints that a framebuffer should use AFBC where possible */
1099 struct panfrost_device
*device
,
1100 const struct pipe_framebuffer_state
*fb
)
1102 /* AFBC implemenation incomplete; hide it */
1103 if (!(device
->debug
& PAN_DBG_AFBC
)) return;
1105 /* Hint AFBC to the resources bound to each color buffer */
1107 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
1108 struct pipe_surface
*surf
= fb
->cbufs
[i
];
1109 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1110 panfrost_resource_hint_layout(device
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1113 /* Also hint it to the depth buffer */
1116 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
1117 panfrost_resource_hint_layout(device
, rsrc
, MALI_TEXTURE_AFBC
, 1);
1122 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1123 const struct pipe_framebuffer_state
*fb
)
1125 struct panfrost_context
*ctx
= pan_context(pctx
);
1127 panfrost_hint_afbc(pan_device(pctx
->screen
), fb
);
1128 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1130 panfrost_invalidate_frame(ctx
);
1134 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1135 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
1137 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
1141 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1144 struct panfrost_context
*ctx
= pan_context(pipe
);
1145 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
1146 ctx
->depth_stencil
= depth_stencil
;
1151 /* Alpha does not exist in the hardware (it's not in ES3), so it's
1152 * emulated in the fragment shader */
1154 if (depth_stencil
->alpha
.enabled
) {
1155 /* We need to trigger a new shader (maybe) */
1156 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1159 /* Bounds test not implemented */
1160 assert(!depth_stencil
->depth
.bounds_test
);
1164 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1170 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1171 unsigned sample_mask
)
1173 struct panfrost_context
*ctx
= pan_context(pipe
);
1174 ctx
->sample_mask
= sample_mask
;
1178 panfrost_set_clip_state(struct pipe_context
*pipe
,
1179 const struct pipe_clip_state
*clip
)
1181 //struct panfrost_context *panfrost = pan_context(pipe);
1185 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1186 unsigned start_slot
,
1187 unsigned num_viewports
,
1188 const struct pipe_viewport_state
*viewports
)
1190 struct panfrost_context
*ctx
= pan_context(pipe
);
1192 assert(start_slot
== 0);
1193 assert(num_viewports
== 1);
1195 ctx
->pipe_viewport
= *viewports
;
1199 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1200 unsigned start_slot
,
1201 unsigned num_scissors
,
1202 const struct pipe_scissor_state
*scissors
)
1204 struct panfrost_context
*ctx
= pan_context(pipe
);
1206 assert(start_slot
== 0);
1207 assert(num_scissors
== 1);
1209 ctx
->scissor
= *scissors
;
1213 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1214 const struct pipe_poly_stipple
*stipple
)
1216 //struct panfrost_context *panfrost = pan_context(pipe);
1220 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1223 struct panfrost_context
*ctx
= pan_context(pipe
);
1224 ctx
->active_queries
= enable
;
1228 panfrost_destroy(struct pipe_context
*pipe
)
1230 struct panfrost_context
*panfrost
= pan_context(pipe
);
1232 if (panfrost
->blitter
)
1233 util_blitter_destroy(panfrost
->blitter
);
1235 if (panfrost
->blitter_wallpaper
)
1236 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1238 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1239 u_upload_destroy(pipe
->stream_uploader
);
1244 static struct pipe_query
*
1245 panfrost_create_query(struct pipe_context
*pipe
,
1249 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1254 return (struct pipe_query
*) q
;
1258 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1260 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1263 panfrost_bo_unreference(query
->bo
);
1271 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1273 struct panfrost_context
*ctx
= pan_context(pipe
);
1274 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1276 switch (query
->type
) {
1277 case PIPE_QUERY_OCCLUSION_COUNTER
:
1278 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1279 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1280 /* Allocate a bo for the query results to be stored */
1282 query
->bo
= pan_bo_create(
1283 pan_device(ctx
->base
.screen
),
1284 sizeof(unsigned), 0);
1287 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1288 *result
= 0; /* Default to 0 if nothing at all drawn. */
1289 ctx
->occlusion_query
= query
;
1292 /* Geometry statistics are computed in the driver. XXX: geom/tess
1295 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1296 query
->start
= ctx
->prims_generated
;
1298 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1299 query
->start
= ctx
->tf_prims_generated
;
1303 /* TODO: timestamp queries, etc? */
1311 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1313 struct panfrost_context
*ctx
= pan_context(pipe
);
1314 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1316 switch (query
->type
) {
1317 case PIPE_QUERY_OCCLUSION_COUNTER
:
1318 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1319 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1320 ctx
->occlusion_query
= NULL
;
1322 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1323 query
->end
= ctx
->prims_generated
;
1325 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1326 query
->end
= ctx
->tf_prims_generated
;
1334 panfrost_get_query_result(struct pipe_context
*pipe
,
1335 struct pipe_query
*q
,
1337 union pipe_query_result
*vresult
)
1339 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1340 struct panfrost_context
*ctx
= pan_context(pipe
);
1343 switch (query
->type
) {
1344 case PIPE_QUERY_OCCLUSION_COUNTER
:
1345 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1346 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1347 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, PAN_BO_ACCESS_WRITE
);
1348 panfrost_bo_wait(query
->bo
, INT64_MAX
, PAN_BO_ACCESS_WRITE
);
1350 /* Read back the query results */
1351 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1352 unsigned passed
= *result
;
1354 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1355 vresult
->u64
= passed
;
1357 vresult
->b
= !!passed
;
1362 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1363 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1364 panfrost_flush_all_batches(ctx
, true);
1365 vresult
->u64
= query
->end
- query
->start
;
1369 /* TODO: more queries */
1376 static struct pipe_stream_output_target
*
1377 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1378 struct pipe_resource
*prsc
,
1379 unsigned buffer_offset
,
1380 unsigned buffer_size
)
1382 struct pipe_stream_output_target
*target
;
1384 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1389 pipe_reference_init(&target
->reference
, 1);
1390 pipe_resource_reference(&target
->buffer
, prsc
);
1392 target
->context
= pctx
;
1393 target
->buffer_offset
= buffer_offset
;
1394 target
->buffer_size
= buffer_size
;
1400 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1401 struct pipe_stream_output_target
*target
)
1403 pipe_resource_reference(&target
->buffer
, NULL
);
1404 ralloc_free(target
);
1408 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1409 unsigned num_targets
,
1410 struct pipe_stream_output_target
**targets
,
1411 const unsigned *offsets
)
1413 struct panfrost_context
*ctx
= pan_context(pctx
);
1414 struct panfrost_streamout
*so
= &ctx
->streamout
;
1416 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1418 for (unsigned i
= 0; i
< num_targets
; i
++) {
1419 if (offsets
[i
] != -1)
1420 so
->offsets
[i
] = offsets
[i
];
1422 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1425 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1426 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1428 so
->num_targets
= num_targets
;
1431 struct pipe_context
*
1432 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1434 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1435 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1436 struct panfrost_device
*dev
= pan_device(screen
);
1438 gallium
->screen
= screen
;
1440 gallium
->destroy
= panfrost_destroy
;
1442 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1444 gallium
->flush
= panfrost_flush
;
1445 gallium
->clear
= panfrost_clear
;
1446 gallium
->draw_vbo
= panfrost_draw_vbo
;
1448 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1449 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1450 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1452 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1454 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1455 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1456 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1458 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1459 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1460 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1462 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1463 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1464 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1466 gallium
->create_fs_state
= panfrost_create_fs_state
;
1467 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1468 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1470 gallium
->create_vs_state
= panfrost_create_vs_state
;
1471 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1472 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1474 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1475 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1476 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1478 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1479 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1480 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1482 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1484 gallium
->set_clip_state
= panfrost_set_clip_state
;
1485 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1486 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1487 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1488 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1490 gallium
->create_query
= panfrost_create_query
;
1491 gallium
->destroy_query
= panfrost_destroy_query
;
1492 gallium
->begin_query
= panfrost_begin_query
;
1493 gallium
->end_query
= panfrost_end_query
;
1494 gallium
->get_query_result
= panfrost_get_query_result
;
1496 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1497 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1498 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1500 panfrost_resource_context_init(gallium
);
1501 panfrost_blend_context_init(gallium
);
1502 panfrost_compute_context_init(gallium
);
1504 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1505 gallium
->const_uploader
= gallium
->stream_uploader
;
1506 assert(gallium
->stream_uploader
);
1508 /* All of our GPUs support ES mode. Midgard supports additionally
1509 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1511 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1513 if (!(dev
->quirks
& IS_BIFROST
)) {
1514 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1515 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1518 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1520 ctx
->blitter
= util_blitter_create(gallium
);
1521 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1523 assert(ctx
->blitter
);
1524 assert(ctx
->blitter_wallpaper
);
1526 /* Prepare for render! */
1528 panfrost_batch_init(ctx
);
1529 panfrost_invalidate_frame(ctx
);
1531 /* By default mask everything on */
1532 ctx
->sample_mask
= ~0;