src/gallium/drivers/panfrost/pan_resource.h

   1 /*
   2  * © Copyright2018-2019 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25
  26 #ifndef PAN_RESOURCE_H
  27 #define PAN_RESOURCE_H
  28
  29 #include <panfrost-job.h>
  30 #include "pan_screen.h"
  31 #include "pan_allocate.h"
  32 #include <drm.h>
  33
  34 struct panfrost_bo {
  35         /* Address to the BO in question */
  36
  37         uint8_t *cpu[MAX_MIP_LEVELS];
  38
  39         /* Not necessarily a GPU mapping of cpu! In case of texture tiling, gpu
  40          * points to the GPU-side, tiled texture, while cpu points to the
  41          * CPU-side, untiled texture from mesa */
  42
  43         mali_ptr gpu[MAX_MIP_LEVELS];
  44
  45         /* Memory entry corresponding to gpu above */
  46         struct panfrost_memory_entry *entry[MAX_MIP_LEVELS];
  47
  48         /* Set for tiled, clear for linear. */
  49         bool tiled;
  50
  51         /* Is something other than level 0 ever written? */
  52         bool is_mipmap;
  53
  54         /* If AFBC is enabled for this resource, we lug around an AFBC
  55          * metadata buffer as well. The actual AFBC resource is also in
  56          * afbc_slab (only defined for AFBC) at position afbc_main_offset */
  57
  58         bool has_afbc;
  59         struct panfrost_memory afbc_slab;
  60         int afbc_metadata_size;
  61
  62         /* Similarly for TE */
  63         bool has_checksum;
  64         struct panfrost_memory checksum_slab;
  65         int checksum_stride;
  66 };
  67
  68 struct panfrost_resource {
  69         struct pipe_resource base;
  70
  71         struct panfrost_bo *bo;
  72         struct renderonly_scanout *scanout;
  73 };
  74
  75 static inline struct panfrost_resource *
  76 pan_resource(struct pipe_resource *p)
  77 {
  78    return (struct panfrost_resource *)p;
  79 }
  80
  81 void panfrost_resource_screen_init(struct panfrost_screen *screen);
  82
  83 void panfrost_resource_context_init(struct pipe_context *pctx);
  84
  85 #endif /* PAN_RESOURCE_H */