src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format.h"
  32 #include "util/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55
  56 static const struct debug_named_value debug_options[] = {
  57         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  58         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  59         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  60         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  61         DEBUG_NAMED_VALUE_END
  62 };
  63
  64 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  65
  66 int pan_debug = 0;
  67
  68 static const char *
  69 panfrost_get_name(struct pipe_screen *screen)
  70 {
  71         return "panfrost";
  72 }
  73
  74 static const char *
  75 panfrost_get_vendor(struct pipe_screen *screen)
  76 {
  77         return "panfrost";
  78 }
  79
  80 static const char *
  81 panfrost_get_device_vendor(struct pipe_screen *screen)
  82 {
  83         return "Arm";
  84 }
  85
  86 static int
  87 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  88 {
  89         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  90         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  91
  92         switch (param) {
  93         case PIPE_CAP_NPOT_TEXTURES:
  94         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  95         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  96         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  97         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  98         case PIPE_CAP_POINT_SPRITE:
  99                 return 1;
 100
 101         case PIPE_CAP_MAX_RENDER_TARGETS:
 102                 return is_deqp ? 4 : 1;
 103
 104         /* Throttling frames breaks pipelining */
 105         case PIPE_CAP_THROTTLE:
 106                 return 0;
 107
 108         case PIPE_CAP_OCCLUSION_QUERY:
 109                 return 1;
 110         case PIPE_CAP_QUERY_TIME_ELAPSED:
 111         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 112         case PIPE_CAP_QUERY_TIMESTAMP:
 113         case PIPE_CAP_QUERY_SO_OVERFLOW:
 114                 return 0;
 115
 116         case PIPE_CAP_TEXTURE_SWIZZLE:
 117                 return 1;
 118
 119         case PIPE_CAP_TGSI_INSTANCEID:
 120         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 121                 return is_deqp ? 1 : 0;
 122
 123         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124                 return is_deqp ? 4 : 0;
 125         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127                 return is_deqp ? 64 : 0;
 128         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 129                 return 1;
 130
 131         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 132                 return is_deqp ? 256 : 0; /* for GL3 */
 133
 134         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 135         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 136                 return is_deqp ? 140 : 120;
 137         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 138                 return is_deqp ? 300 : 120;
 139
 140         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 141                 return is_deqp ? 16 : 0;
 142
 143         case PIPE_CAP_CUBE_MAP_ARRAY:
 144                 return is_deqp;
 145
 146         /* For faking GLES 3.1 for dEQP-GLES31 */
 147         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 148         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 149         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 150         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 151                 return is_deqp;
 152
 153         /* For faking compute shaders */
 154         case PIPE_CAP_COMPUTE:
 155                 return is_deqp;
 156
 157         /* TODO: Where does this req come from in practice? */
 158         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 159                 return 1;
 160
 161         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 162                 return 4096;
 163         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 164         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 165                 return 13;
 166
 167         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 168         case PIPE_CAP_INDEP_BLEND_ENABLE:
 169         case PIPE_CAP_INDEP_BLEND_FUNC:
 170                 return 1;
 171
 172         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 173                 /* Hardware is natively upper left */
 174                 return 0;
 175
 176         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 177         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 178         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 179         case PIPE_CAP_GENERATE_MIPMAP:
 180                 return 1;
 181
 182         /* We would prefer varyings */
 183         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 184         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 185                 return 0;
 186
 187         /* I really don't want to set this CAP but let's not swim against the
 188          * tide.. */
 189         case PIPE_CAP_TGSI_TEXCOORD:
 190                 return 1;
 191
 192         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 193         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 194                 return 1;
 195
 196         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 197                 return 0xffff;
 198
 199         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 200                 return 1;
 201
 202         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 203                 return 65536;
 204
 205         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 206                 return 0;
 207
 208         case PIPE_CAP_ENDIANNESS:
 209                 return PIPE_ENDIAN_NATIVE;
 210
 211         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 212                 return 1;
 213
 214         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 215                 return -8;
 216
 217         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 218                 return 7;
 219
 220         case PIPE_CAP_VENDOR_ID:
 221         case PIPE_CAP_DEVICE_ID:
 222                 return 0xFFFFFFFF;
 223
 224         case PIPE_CAP_ACCELERATED:
 225         case PIPE_CAP_UMA:
 226         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 227         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 228         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 229         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 230                 return 1;
 231
 232         case PIPE_CAP_VIDEO_MEMORY: {
 233                 uint64_t system_memory;
 234
 235                 if (!os_get_total_physical_memory(&system_memory))
 236                         return 0;
 237
 238                 return (int)(system_memory >> 20);
 239         }
 240
 241         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 242                 return 4;
 243
 244         case PIPE_CAP_MAX_VARYINGS:
 245                 return 16;
 246
 247         default:
 248                 return u_pipe_screen_get_param_defaults(screen, param);
 249         }
 250 }
 251
 252 static int
 253 panfrost_get_shader_param(struct pipe_screen *screen,
 254                           enum pipe_shader_type shader,
 255                           enum pipe_shader_cap param)
 256 {
 257         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 258
 259         if (shader != PIPE_SHADER_VERTEX &&
 260             shader != PIPE_SHADER_FRAGMENT &&
 261             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 262                 return 0;
 263
 264         /* this is probably not totally correct.. but it's a start: */
 265         switch (param) {
 266         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 267         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 268         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 269         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 270                 return 16384;
 271
 272         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 273                 return 1024;
 274
 275         case PIPE_SHADER_CAP_MAX_INPUTS:
 276                 return 16;
 277
 278         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 279                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 8;
 280
 281         case PIPE_SHADER_CAP_MAX_TEMPS:
 282                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 283
 284         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 285                 return 16 * 1024 * sizeof(float);
 286
 287         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 288                 return PAN_MAX_CONST_BUFFERS;
 289
 290         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 291                 return 0;
 292
 293         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 294                 return 1;
 295         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 296                 return 0;
 297
 298         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 299                 return 0;
 300
 301         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 302                 return 1;
 303
 304         case PIPE_SHADER_CAP_SUBROUTINES:
 305                 return 0;
 306
 307         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 308                 return 0;
 309
 310         case PIPE_SHADER_CAP_INTEGERS:
 311                 return 1;
 312
 313         case PIPE_SHADER_CAP_INT64_ATOMICS:
 314         case PIPE_SHADER_CAP_FP16:
 315         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 316         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 317         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 318         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 319         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 320                 return 0;
 321
 322         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 323         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 324                 return 16; /* XXX: How many? */
 325
 326         case PIPE_SHADER_CAP_PREFERRED_IR:
 327                 return PIPE_SHADER_IR_NIR;
 328
 329         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 330                 return (1 << PIPE_SHADER_IR_NIR);
 331
 332         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 333                 return 32;
 334
 335         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 336         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 337                 return is_deqp ? 4 : 0;
 338         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 339         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 340                 return 0;
 341
 342         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 343         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 344                 return 0;
 345
 346         default:
 347                 fprintf(stderr, "unknown shader param %d\n", param);
 348                 return 0;
 349         }
 350
 351         return 0;
 352 }
 353
 354 static float
 355 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 356 {
 357         switch (param) {
 358         case PIPE_CAPF_MAX_LINE_WIDTH:
 359
 360         /* fall-through */
 361         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 362                 return 255.0; /* arbitrary */
 363
 364         case PIPE_CAPF_MAX_POINT_WIDTH:
 365
 366         /* fall-through */
 367         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 368                 return 1024.0;
 369
 370         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 371                 return 16.0;
 372
 373         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 374                 return 16.0; /* arbitrary */
 375
 376         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 377         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 378         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 379                 return 0.0f;
 380
 381         default:
 382                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 383                 return 0.0;
 384         }
 385 }
 386
 387 /**
 388  * Query format support for creating a texture, drawing surface, etc.
 389  * \param format  the format to test
 390  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 391  */
 392 static bool
 393 panfrost_is_format_supported( struct pipe_screen *screen,
 394                               enum pipe_format format,
 395                               enum pipe_texture_target target,
 396                               unsigned sample_count,
 397                               unsigned storage_sample_count,
 398                               unsigned bind)
 399 {
 400         const struct util_format_description *format_desc;
 401
 402         assert(target == PIPE_BUFFER ||
 403                target == PIPE_TEXTURE_1D ||
 404                target == PIPE_TEXTURE_1D_ARRAY ||
 405                target == PIPE_TEXTURE_2D ||
 406                target == PIPE_TEXTURE_2D_ARRAY ||
 407                target == PIPE_TEXTURE_RECT ||
 408                target == PIPE_TEXTURE_3D ||
 409                target == PIPE_TEXTURE_CUBE ||
 410                target == PIPE_TEXTURE_CUBE_ARRAY);
 411
 412         format_desc = util_format_description(format);
 413
 414         if (!format_desc)
 415                 return false;
 416
 417         if (sample_count > 1)
 418                 return false;
 419
 420         /* Format wishlist */
 421         if (format == PIPE_FORMAT_X8Z24_UNORM)
 422                 return false;
 423
 424         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 425                 return false;
 426
 427         /* TODO */
 428         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 429                 return FALSE;
 430
 431         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 432          * more alpha than they ask for */
 433
 434         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 435         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 436
 437         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 438                 return false;
 439
 440         if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
 441             format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
 442                 /* Compressed formats not yet hooked up. */
 443                 return false;
 444         }
 445
 446         /* Internally, formats that are depth/stencil renderable are limited.
 447          *
 448          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 449          * rendering perspective. That is, we render to Z24S8 (which we can
 450          * AFBC compress), ignore the different when texturing (who cares?),
 451          * and then in the off-chance there's a CPU read we blit back to
 452          * staging.
 453          *
 454          * ...alternatively, we can make the state tracker deal with that. */
 455
 456         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 457                 switch (format) {
 458                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 459                         case PIPE_FORMAT_Z24X8_UNORM:
 460                         case PIPE_FORMAT_Z32_UNORM:
 461                         case PIPE_FORMAT_Z32_FLOAT:
 462                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 463                                 return true;
 464
 465                         default:
 466                                 return false;
 467                 }
 468         }
 469
 470         return true;
 471 }
 472
 473 static int
 474 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 475                 enum pipe_compute_cap param, void *ret)
 476 {
 477         const char * const ir = "panfrost";
 478
 479         if (!(pan_debug & PAN_DBG_DEQP))
 480                 return 0;
 481
 482 #define RET(x) do {                  \
 483    if (ret)                          \
 484       memcpy(ret, x, sizeof(x));     \
 485    return sizeof(x);                 \
 486 } while (0)
 487
 488         switch (param) {
 489         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 490                 /* TODO: We'll want 64-bit pointers soon */
 491                 RET((uint32_t []){ 32 });
 492
 493         case PIPE_COMPUTE_CAP_IR_TARGET:
 494                 if (ret)
 495                         sprintf(ret, "%s", ir);
 496                 return strlen(ir) * sizeof(char);
 497
 498         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 499                 RET((uint64_t []) { 3 });
 500
 501         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 502                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 503
 504         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 505                 RET(((uint64_t []) { 1024, 1024, 64 }));
 506
 507         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 508                 RET((uint64_t []) { 1024 });
 509
 510         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 511                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 512
 513         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 514                 RET((uint64_t []) { 32768 });
 515
 516         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 517         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 518                 RET((uint64_t []) { 4096 });
 519
 520         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 521                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 522
 523         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 524                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 525
 526         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 527                 RET((uint32_t []) { 9999 });  // TODO
 528
 529         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 530                 RET((uint32_t []) { 1 }); // TODO
 531
 532         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 533                 RET((uint32_t []) { 32 });  // TODO
 534
 535         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 536                 RET((uint64_t []) { 1024 }); // TODO
 537         }
 538
 539         return 0;
 540 }
 541
 542 static void
 543 panfrost_destroy_screen(struct pipe_screen *pscreen)
 544 {
 545         struct panfrost_screen *screen = pan_screen(pscreen);
 546         panfrost_bo_cache_evict_all(screen);
 547         pthread_mutex_destroy(&screen->bo_cache_lock);
 548         drmFreeVersion(screen->kernel_version);
 549         ralloc_free(screen);
 550 }
 551
 552 static void
 553 panfrost_flush_frontbuffer(struct pipe_screen *_screen,
 554                            struct pipe_resource *resource,
 555                            unsigned level, unsigned layer,
 556                            void *context_private,
 557                            struct pipe_box *sub_box)
 558 {
 559         /* TODO: Display target integration */
 560 }
 561
 562 static uint64_t
 563 panfrost_get_timestamp(struct pipe_screen *_screen)
 564 {
 565         return os_time_get_nano();
 566 }
 567
 568 static void
 569 panfrost_fence_reference(struct pipe_screen *pscreen,
 570                          struct pipe_fence_handle **ptr,
 571                          struct pipe_fence_handle *fence)
 572 {
 573         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 574         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 575         struct panfrost_fence *old = *p;
 576
 577         if (pipe_reference(&(*p)->reference, &f->reference)) {
 578                 util_dynarray_foreach(&old->syncfds, int, fd)
 579                         close(*fd);
 580                 util_dynarray_fini(&old->syncfds);
 581                 free(old);
 582         }
 583         *p = f;
 584 }
 585
 586 static bool
 587 panfrost_fence_finish(struct pipe_screen *pscreen,
 588                       struct pipe_context *ctx,
 589                       struct pipe_fence_handle *fence,
 590                       uint64_t timeout)
 591 {
 592         struct panfrost_screen *screen = pan_screen(pscreen);
 593         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 594         struct util_dynarray syncobjs;
 595         int ret;
 596
 597         /* All fences were already signaled */
 598         if (!util_dynarray_num_elements(&f->syncfds, int))
 599                 return true;
 600
 601         util_dynarray_init(&syncobjs, NULL);
 602         util_dynarray_foreach(&f->syncfds, int, fd) {
 603                 uint32_t syncobj;
 604
 605                 ret = drmSyncobjCreate(screen->fd, 0, &syncobj);
 606                 assert(!ret);
 607
 608                 ret = drmSyncobjImportSyncFile(screen->fd, syncobj, *fd);
 609                 assert(!ret);
 610                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 611         }
 612
 613         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 614         if (abs_timeout == OS_TIMEOUT_INFINITE)
 615                 abs_timeout = INT64_MAX;
 616
 617         ret = drmSyncobjWait(screen->fd, util_dynarray_begin(&syncobjs),
 618                              util_dynarray_num_elements(&syncobjs, uint32_t),
 619                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 620                              NULL);
 621
 622         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 623                 drmSyncobjDestroy(screen->fd, *syncobj);
 624
 625         return ret >= 0;
 626 }
 627
 628 struct panfrost_fence *
 629 panfrost_fence_create(struct panfrost_context *ctx,
 630                       struct util_dynarray *fences)
 631 {
 632         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
 633         struct panfrost_fence *f = calloc(1, sizeof(*f));
 634         if (!f)
 635                 return NULL;
 636
 637         util_dynarray_init(&f->syncfds, NULL);
 638
 639         /* Export fences from all pending batches. */
 640         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 641                 int fd = -1;
 642
 643                 /* The fence is already signaled, no need to export it. */
 644                 if ((*fence)->signaled)
 645                         continue;
 646
 647                 drmSyncobjExportSyncFile(screen->fd, (*fence)->syncobj, &fd);
 648                 if (fd == -1)
 649                         fprintf(stderr, "export failed: %m\n");
 650
 651                 assert(fd != -1);
 652                 util_dynarray_append(&f->syncfds, int, fd);
 653         }
 654
 655         pipe_reference_init(&f->reference, 1);
 656
 657         return f;
 658 }
 659
 660 static const void *
 661 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 662                                      enum pipe_shader_ir ir,
 663                                      enum pipe_shader_type shader)
 664 {
 665         return &midgard_nir_options;
 666 }
 667
 668 static unsigned
 669 panfrost_query_gpu_version(struct panfrost_screen *screen)
 670 {
 671         struct drm_panfrost_get_param get_param = {0,};
 672         ASSERTED int ret;
 673
 674         get_param.param = DRM_PANFROST_PARAM_GPU_PROD_ID;
 675         ret = drmIoctl(screen->fd, DRM_IOCTL_PANFROST_GET_PARAM, &get_param);
 676         assert(!ret);
 677
 678         return get_param.value;
 679 }
 680
 681 struct pipe_screen *
 682 panfrost_create_screen(int fd, struct renderonly *ro)
 683 {
 684         pan_debug = debug_get_option_pan_debug();
 685
 686         /* Blacklist apps known to be buggy under Panfrost */
 687         const char *proc = util_get_process_name();
 688         const char *blacklist[] = {
 689                 "chromium",
 690                 "chrome",
 691         };
 692
 693         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 694                 if ((strcmp(blacklist[i], proc) == 0))
 695                         return NULL;
 696         }
 697
 698         /* Create the screen */
 699         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 700
 701         if (!screen)
 702                 return NULL;
 703
 704         if (ro) {
 705                 screen->ro = renderonly_dup(ro);
 706                 if (!screen->ro) {
 707                         fprintf(stderr, "Failed to dup renderonly object\n");
 708                         free(screen);
 709                         return NULL;
 710                 }
 711         }
 712
 713         screen->fd = fd;
 714
 715         screen->gpu_id = panfrost_query_gpu_version(screen);
 716         screen->require_sfbd = screen->gpu_id < 0x0750; /* T760 is the first to support MFBD */
 717         screen->kernel_version = drmGetVersion(fd);
 718
 719         /* Check if we're loading against a supported GPU model. */
 720
 721         switch (screen->gpu_id) {
 722         case 0x750: /* T760 */
 723         case 0x820: /* T820 */
 724         case 0x860: /* T860 */
 725                 break;
 726         default:
 727                 /* Fail to load against untested models */
 728                 debug_printf("panfrost: Unsupported model %X",
 729                              screen->gpu_id);
 730                 return NULL;
 731         }
 732
 733         pthread_mutex_init(&screen->bo_cache_lock, NULL);
 734         for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache); ++i)
 735                 list_inithead(&screen->bo_cache[i]);
 736
 737         if (pan_debug & PAN_DBG_TRACE)
 738                 pandecode_initialize();
 739
 740         screen->base.destroy = panfrost_destroy_screen;
 741
 742         screen->base.get_name = panfrost_get_name;
 743         screen->base.get_vendor = panfrost_get_vendor;
 744         screen->base.get_device_vendor = panfrost_get_device_vendor;
 745         screen->base.get_param = panfrost_get_param;
 746         screen->base.get_shader_param = panfrost_get_shader_param;
 747         screen->base.get_compute_param = panfrost_get_compute_param;
 748         screen->base.get_paramf = panfrost_get_paramf;
 749         screen->base.get_timestamp = panfrost_get_timestamp;
 750         screen->base.is_format_supported = panfrost_is_format_supported;
 751         screen->base.context_create = panfrost_create_context;
 752         screen->base.flush_frontbuffer = panfrost_flush_frontbuffer;
 753         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 754         screen->base.fence_reference = panfrost_fence_reference;
 755         screen->base.fence_finish = panfrost_fence_finish;
 756         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 757
 758         panfrost_resource_screen_init(screen);
 759
 760         return &screen->base;
 761 }