src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55
  56 static const struct debug_named_value debug_options[] = {
  57         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  58         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  59         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  60         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  61         DEBUG_NAMED_VALUE_END
  62 };
  63
  64 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  65
  66 int pan_debug = 0;
  67
  68 static const char *
  69 panfrost_get_name(struct pipe_screen *screen)
  70 {
  71         return "panfrost";
  72 }
  73
  74 static const char *
  75 panfrost_get_vendor(struct pipe_screen *screen)
  76 {
  77         return "panfrost";
  78 }
  79
  80 static const char *
  81 panfrost_get_device_vendor(struct pipe_screen *screen)
  82 {
  83         return "Arm";
  84 }
  85
  86 static int
  87 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  88 {
  89         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  90         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  91
  92         switch (param) {
  93         case PIPE_CAP_NPOT_TEXTURES:
  94         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  95         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  96         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  97         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  98         case PIPE_CAP_POINT_SPRITE:
  99                 return 1;
 100
 101         case PIPE_CAP_MAX_RENDER_TARGETS:
 102                 return is_deqp ? 4 : 1;
 103
 104         /* Throttling frames breaks pipelining */
 105         case PIPE_CAP_THROTTLE:
 106                 return 0;
 107
 108         case PIPE_CAP_OCCLUSION_QUERY:
 109                 return 1;
 110         case PIPE_CAP_QUERY_TIME_ELAPSED:
 111         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 112         case PIPE_CAP_QUERY_TIMESTAMP:
 113         case PIPE_CAP_QUERY_SO_OVERFLOW:
 114                 return 0;
 115
 116         case PIPE_CAP_TEXTURE_SWIZZLE:
 117                 return 1;
 118
 119         case PIPE_CAP_TGSI_INSTANCEID:
 120         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 121                 return is_deqp ? 1 : 0;
 122
 123         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124                 return is_deqp ? 4 : 0;
 125         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127                 return is_deqp ? 64 : 0;
 128         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 129                 return 1;
 130
 131         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 132                 return is_deqp ? 256 : 0; /* for GL3 */
 133
 134         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 135         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 136                 return is_deqp ? 140 : 120;
 137         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 138                 return is_deqp ? 300 : 120;
 139
 140         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 141                 return is_deqp ? 16 : 0;
 142
 143         case PIPE_CAP_CUBE_MAP_ARRAY:
 144                 return is_deqp;
 145
 146         /* For faking GLES 3.1 for dEQP-GLES31 */
 147         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 148         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 149         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 150         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 151                 return is_deqp;
 152
 153         /* For faking compute shaders */
 154         case PIPE_CAP_COMPUTE:
 155                 return is_deqp;
 156
 157         /* TODO: Where does this req come from in practice? */
 158         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 159                 return 1;
 160
 161         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 162                 return 4096;
 163         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 164         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 165                 return 13;
 166
 167         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 168         case PIPE_CAP_INDEP_BLEND_ENABLE:
 169         case PIPE_CAP_INDEP_BLEND_FUNC:
 170                 return 1;
 171
 172         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 173                 /* Hardware is natively upper left */
 174                 return 0;
 175
 176         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 177         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 178         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 179         case PIPE_CAP_GENERATE_MIPMAP:
 180                 return 1;
 181
 182         /* We would prefer varyings */
 183         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 184         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 185                 return 0;
 186
 187         /* I really don't want to set this CAP but let's not swim against the
 188          * tide.. */
 189         case PIPE_CAP_TGSI_TEXCOORD:
 190                 return 1;
 191
 192         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 193         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 194                 return 1;
 195
 196         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 197                 return 0xffff;
 198
 199         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 200                 return 1;
 201
 202         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 203                 return 65536;
 204
 205         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 206                 return 0;
 207
 208         case PIPE_CAP_ENDIANNESS:
 209                 return PIPE_ENDIAN_NATIVE;
 210
 211         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 212                 return 1;
 213
 214         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 215                 return -8;
 216
 217         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 218                 return 7;
 219
 220         case PIPE_CAP_VENDOR_ID:
 221         case PIPE_CAP_DEVICE_ID:
 222                 return 0xFFFFFFFF;
 223
 224         case PIPE_CAP_ACCELERATED:
 225         case PIPE_CAP_UMA:
 226         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 227         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 228         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 229         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 230                 return 1;
 231
 232         case PIPE_CAP_VIDEO_MEMORY: {
 233                 uint64_t system_memory;
 234
 235                 if (!os_get_total_physical_memory(&system_memory))
 236                         return 0;
 237
 238                 return (int)(system_memory >> 20);
 239         }
 240
 241         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 242                 return 4;
 243
 244         case PIPE_CAP_MAX_VARYINGS:
 245                 return 16;
 246
 247         case PIPE_CAP_ALPHA_TEST:
 248                 return 0;
 249
 250         default:
 251                 return u_pipe_screen_get_param_defaults(screen, param);
 252         }
 253 }
 254
 255 static int
 256 panfrost_get_shader_param(struct pipe_screen *screen,
 257                           enum pipe_shader_type shader,
 258                           enum pipe_shader_cap param)
 259 {
 260         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 261
 262         if (shader != PIPE_SHADER_VERTEX &&
 263             shader != PIPE_SHADER_FRAGMENT &&
 264             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 265                 return 0;
 266
 267         /* this is probably not totally correct.. but it's a start: */
 268         switch (param) {
 269         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 270         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 271         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 272         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 273                 return 16384;
 274
 275         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 276                 return 1024;
 277
 278         case PIPE_SHADER_CAP_MAX_INPUTS:
 279                 return 16;
 280
 281         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 282                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 8;
 283
 284         case PIPE_SHADER_CAP_MAX_TEMPS:
 285                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 286
 287         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 288                 return 16 * 1024 * sizeof(float);
 289
 290         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 291                 return PAN_MAX_CONST_BUFFERS;
 292
 293         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 294                 return 0;
 295
 296         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 297                 return 1;
 298         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 299                 return 0;
 300
 301         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 302                 return 0;
 303
 304         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 305                 return 1;
 306
 307         case PIPE_SHADER_CAP_SUBROUTINES:
 308                 return 0;
 309
 310         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 311                 return 0;
 312
 313         case PIPE_SHADER_CAP_INTEGERS:
 314                 return 1;
 315
 316         case PIPE_SHADER_CAP_INT64_ATOMICS:
 317         case PIPE_SHADER_CAP_FP16:
 318         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 319         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 320         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 321         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 322         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 323                 return 0;
 324
 325         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 326         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 327                 return 16; /* XXX: How many? */
 328
 329         case PIPE_SHADER_CAP_PREFERRED_IR:
 330                 return PIPE_SHADER_IR_NIR;
 331
 332         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 333                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 334
 335         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 336                 return 32;
 337
 338         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 339         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 340                 return is_deqp ? 4 : 0;
 341         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 342         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 343                 return 0;
 344
 345         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 346         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 347                 return 0;
 348
 349         default:
 350                 fprintf(stderr, "unknown shader param %d\n", param);
 351                 return 0;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static float
 358 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 359 {
 360         switch (param) {
 361         case PIPE_CAPF_MAX_LINE_WIDTH:
 362
 363         /* fall-through */
 364         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 365                 return 255.0; /* arbitrary */
 366
 367         case PIPE_CAPF_MAX_POINT_WIDTH:
 368
 369         /* fall-through */
 370         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 371                 return 1024.0;
 372
 373         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 374                 return 16.0;
 375
 376         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 377                 return 16.0; /* arbitrary */
 378
 379         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 380         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 381         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 382                 return 0.0f;
 383
 384         default:
 385                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 386                 return 0.0;
 387         }
 388 }
 389
 390 /**
 391  * Query format support for creating a texture, drawing surface, etc.
 392  * \param format  the format to test
 393  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 394  */
 395 static bool
 396 panfrost_is_format_supported( struct pipe_screen *screen,
 397                               enum pipe_format format,
 398                               enum pipe_texture_target target,
 399                               unsigned sample_count,
 400                               unsigned storage_sample_count,
 401                               unsigned bind)
 402 {
 403         const struct util_format_description *format_desc;
 404
 405         assert(target == PIPE_BUFFER ||
 406                target == PIPE_TEXTURE_1D ||
 407                target == PIPE_TEXTURE_1D_ARRAY ||
 408                target == PIPE_TEXTURE_2D ||
 409                target == PIPE_TEXTURE_2D_ARRAY ||
 410                target == PIPE_TEXTURE_RECT ||
 411                target == PIPE_TEXTURE_3D ||
 412                target == PIPE_TEXTURE_CUBE ||
 413                target == PIPE_TEXTURE_CUBE_ARRAY);
 414
 415         format_desc = util_format_description(format);
 416
 417         if (!format_desc)
 418                 return false;
 419
 420         if (sample_count > 1)
 421                 return false;
 422
 423         /* Format wishlist */
 424         if (format == PIPE_FORMAT_X8Z24_UNORM)
 425                 return false;
 426
 427         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 428                 return false;
 429
 430         /* TODO */
 431         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 432                 return FALSE;
 433
 434         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 435          * more alpha than they ask for */
 436
 437         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 438         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 439
 440         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 441                 return false;
 442
 443         if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
 444             format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
 445                 /* Compressed formats not yet hooked up. */
 446                 return false;
 447         }
 448
 449         /* Internally, formats that are depth/stencil renderable are limited.
 450          *
 451          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 452          * rendering perspective. That is, we render to Z24S8 (which we can
 453          * AFBC compress), ignore the different when texturing (who cares?),
 454          * and then in the off-chance there's a CPU read we blit back to
 455          * staging.
 456          *
 457          * ...alternatively, we can make the state tracker deal with that. */
 458
 459         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 460                 switch (format) {
 461                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 462                         case PIPE_FORMAT_Z24X8_UNORM:
 463                         case PIPE_FORMAT_Z32_UNORM:
 464                         case PIPE_FORMAT_Z32_FLOAT:
 465                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 466                                 return true;
 467
 468                         default:
 469                                 return false;
 470                 }
 471         }
 472
 473         return true;
 474 }
 475
 476 static int
 477 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 478                 enum pipe_compute_cap param, void *ret)
 479 {
 480         const char * const ir = "panfrost";
 481
 482         if (!(pan_debug & PAN_DBG_DEQP))
 483                 return 0;
 484
 485 #define RET(x) do {                  \
 486    if (ret)                          \
 487       memcpy(ret, x, sizeof(x));     \
 488    return sizeof(x);                 \
 489 } while (0)
 490
 491         switch (param) {
 492         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 493                 RET((uint32_t []){ 64 });
 494
 495         case PIPE_COMPUTE_CAP_IR_TARGET:
 496                 if (ret)
 497                         sprintf(ret, "%s", ir);
 498                 return strlen(ir) * sizeof(char);
 499
 500         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 501                 RET((uint64_t []) { 3 });
 502
 503         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 504                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 505
 506         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 507                 RET(((uint64_t []) { 1024, 1024, 64 }));
 508
 509         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 510                 RET((uint64_t []) { 1024 });
 511
 512         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 513                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 514
 515         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 516                 RET((uint64_t []) { 32768 });
 517
 518         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 519         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 520                 RET((uint64_t []) { 4096 });
 521
 522         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 523                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 524
 525         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 526                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 527
 528         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 529                 RET((uint32_t []) { 9999 });  // TODO
 530
 531         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 532                 RET((uint32_t []) { 1 }); // TODO
 533
 534         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 535                 RET((uint32_t []) { 32 });  // TODO
 536
 537         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 538                 RET((uint64_t []) { 1024 }); // TODO
 539         }
 540
 541         return 0;
 542 }
 543
 544 static void
 545 panfrost_destroy_screen(struct pipe_screen *pscreen)
 546 {
 547         struct panfrost_screen *screen = pan_screen(pscreen);
 548         panfrost_bo_cache_evict_all(screen);
 549         pthread_mutex_destroy(&screen->bo_cache.lock);
 550         pthread_mutex_destroy(&screen->active_bos_lock);
 551         drmFreeVersion(screen->kernel_version);
 552         ralloc_free(screen);
 553 }
 554
 555 static void
 556 panfrost_flush_frontbuffer(struct pipe_screen *_screen,
 557                            struct pipe_resource *resource,
 558                            unsigned level, unsigned layer,
 559                            void *context_private,
 560                            struct pipe_box *sub_box)
 561 {
 562         /* TODO: Display target integration */
 563 }
 564
 565 static uint64_t
 566 panfrost_get_timestamp(struct pipe_screen *_screen)
 567 {
 568         return os_time_get_nano();
 569 }
 570
 571 static void
 572 panfrost_fence_reference(struct pipe_screen *pscreen,
 573                          struct pipe_fence_handle **ptr,
 574                          struct pipe_fence_handle *fence)
 575 {
 576         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 577         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 578         struct panfrost_fence *old = *p;
 579
 580         if (pipe_reference(&(*p)->reference, &f->reference)) {
 581                 util_dynarray_foreach(&old->syncfds, int, fd)
 582                         close(*fd);
 583                 util_dynarray_fini(&old->syncfds);
 584                 free(old);
 585         }
 586         *p = f;
 587 }
 588
 589 static bool
 590 panfrost_fence_finish(struct pipe_screen *pscreen,
 591                       struct pipe_context *ctx,
 592                       struct pipe_fence_handle *fence,
 593                       uint64_t timeout)
 594 {
 595         struct panfrost_screen *screen = pan_screen(pscreen);
 596         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 597         struct util_dynarray syncobjs;
 598         int ret;
 599
 600         /* All fences were already signaled */
 601         if (!util_dynarray_num_elements(&f->syncfds, int))
 602                 return true;
 603
 604         util_dynarray_init(&syncobjs, NULL);
 605         util_dynarray_foreach(&f->syncfds, int, fd) {
 606                 uint32_t syncobj;
 607
 608                 ret = drmSyncobjCreate(screen->fd, 0, &syncobj);
 609                 assert(!ret);
 610
 611                 ret = drmSyncobjImportSyncFile(screen->fd, syncobj, *fd);
 612                 assert(!ret);
 613                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 614         }
 615
 616         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 617         if (abs_timeout == OS_TIMEOUT_INFINITE)
 618                 abs_timeout = INT64_MAX;
 619
 620         ret = drmSyncobjWait(screen->fd, util_dynarray_begin(&syncobjs),
 621                              util_dynarray_num_elements(&syncobjs, uint32_t),
 622                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 623                              NULL);
 624
 625         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 626                 drmSyncobjDestroy(screen->fd, *syncobj);
 627
 628         return ret >= 0;
 629 }
 630
 631 struct panfrost_fence *
 632 panfrost_fence_create(struct panfrost_context *ctx,
 633                       struct util_dynarray *fences)
 634 {
 635         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
 636         struct panfrost_fence *f = calloc(1, sizeof(*f));
 637         if (!f)
 638                 return NULL;
 639
 640         util_dynarray_init(&f->syncfds, NULL);
 641
 642         /* Export fences from all pending batches. */
 643         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 644                 int fd = -1;
 645
 646                 /* The fence is already signaled, no need to export it. */
 647                 if ((*fence)->signaled)
 648                         continue;
 649
 650                 drmSyncobjExportSyncFile(screen->fd, (*fence)->syncobj, &fd);
 651                 if (fd == -1)
 652                         fprintf(stderr, "export failed: %m\n");
 653
 654                 assert(fd != -1);
 655                 util_dynarray_append(&f->syncfds, int, fd);
 656         }
 657
 658         pipe_reference_init(&f->reference, 1);
 659
 660         return f;
 661 }
 662
 663 static const void *
 664 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 665                                      enum pipe_shader_ir ir,
 666                                      enum pipe_shader_type shader)
 667 {
 668         return &midgard_nir_options;
 669 }
 670
 671 static unsigned
 672 panfrost_query_gpu_version(struct panfrost_screen *screen)
 673 {
 674         struct drm_panfrost_get_param get_param = {0,};
 675         ASSERTED int ret;
 676
 677         get_param.param = DRM_PANFROST_PARAM_GPU_PROD_ID;
 678         ret = drmIoctl(screen->fd, DRM_IOCTL_PANFROST_GET_PARAM, &get_param);
 679         assert(!ret);
 680
 681         return get_param.value;
 682 }
 683
 684 static uint32_t
 685 panfrost_active_bos_hash(const void *key)
 686 {
 687         const struct panfrost_bo *bo = key;
 688
 689         return _mesa_hash_data(&bo->gem_handle, sizeof(bo->gem_handle));
 690 }
 691
 692 static bool
 693 panfrost_active_bos_cmp(const void *keya, const void *keyb)
 694 {
 695         const struct panfrost_bo *a = keya, *b = keyb;
 696
 697         return a->gem_handle == b->gem_handle;
 698 }
 699
 700 struct pipe_screen *
 701 panfrost_create_screen(int fd, struct renderonly *ro)
 702 {
 703         pan_debug = debug_get_option_pan_debug();
 704
 705         /* Blacklist apps known to be buggy under Panfrost */
 706         const char *proc = util_get_process_name();
 707         const char *blacklist[] = {
 708                 "chromium",
 709                 "chrome",
 710         };
 711
 712         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 713                 if ((strcmp(blacklist[i], proc) == 0))
 714                         return NULL;
 715         }
 716
 717         /* Create the screen */
 718         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 719
 720         if (!screen)
 721                 return NULL;
 722
 723         if (ro) {
 724                 screen->ro = renderonly_dup(ro);
 725                 if (!screen->ro) {
 726                         fprintf(stderr, "Failed to dup renderonly object\n");
 727                         free(screen);
 728                         return NULL;
 729                 }
 730         }
 731
 732         screen->fd = fd;
 733
 734         screen->gpu_id = panfrost_query_gpu_version(screen);
 735         screen->require_sfbd = screen->gpu_id < 0x0750; /* T760 is the first to support MFBD */
 736         screen->kernel_version = drmGetVersion(fd);
 737
 738         /* Check if we're loading against a supported GPU model. */
 739
 740         switch (screen->gpu_id) {
 741         case 0x750: /* T760 */
 742         case 0x820: /* T820 */
 743         case 0x860: /* T860 */
 744                 break;
 745         default:
 746                 /* Fail to load against untested models */
 747                 debug_printf("panfrost: Unsupported model %X",
 748                              screen->gpu_id);
 749                 return NULL;
 750         }
 751
 752         pthread_mutex_init(&screen->active_bos_lock, NULL);
 753         screen->active_bos = _mesa_set_create(screen, panfrost_active_bos_hash,
 754                                               panfrost_active_bos_cmp);
 755
 756         pthread_mutex_init(&screen->bo_cache.lock, NULL);
 757         list_inithead(&screen->bo_cache.lru);
 758         for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache.buckets); ++i)
 759                 list_inithead(&screen->bo_cache.buckets[i]);
 760
 761         if (pan_debug & PAN_DBG_TRACE)
 762                 pandecode_initialize();
 763
 764         screen->base.destroy = panfrost_destroy_screen;
 765
 766         screen->base.get_name = panfrost_get_name;
 767         screen->base.get_vendor = panfrost_get_vendor;
 768         screen->base.get_device_vendor = panfrost_get_device_vendor;
 769         screen->base.get_param = panfrost_get_param;
 770         screen->base.get_shader_param = panfrost_get_shader_param;
 771         screen->base.get_compute_param = panfrost_get_compute_param;
 772         screen->base.get_paramf = panfrost_get_paramf;
 773         screen->base.get_timestamp = panfrost_get_timestamp;
 774         screen->base.is_format_supported = panfrost_is_format_supported;
 775         screen->base.context_create = panfrost_create_context;
 776         screen->base.flush_frontbuffer = panfrost_flush_frontbuffer;
 777         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 778         screen->base.fence_reference = panfrost_fence_reference;
 779         screen->base.fence_finish = panfrost_fence_finish;
 780         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 781
 782         panfrost_resource_screen_init(screen);
 783
 784         return &screen->base;
 785 }