2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
43 #include "drm-uapi/drm_fourcc.h"
44 #include "drm-uapi/panfrost_drm.h"
47 #include "pan_screen.h"
48 #include "pan_resource.h"
49 #include "pan_public.h"
51 #include "pandecode/decode.h"
53 #include "pan_context.h"
54 #include "midgard/midgard_compile.h"
56 static const struct debug_named_value debug_options
[] = {
57 {"msgs", PAN_DBG_MSGS
, "Print debug messages"},
58 {"trace", PAN_DBG_TRACE
, "Trace the command stream"},
59 {"deqp", PAN_DBG_DEQP
, "Hacks for dEQP"},
60 {"afbc", PAN_DBG_AFBC
, "Enable non-conformant AFBC impl"},
64 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug
, "PAN_MESA_DEBUG", debug_options
, 0)
69 panfrost_get_name(struct pipe_screen
*screen
)
75 panfrost_get_vendor(struct pipe_screen
*screen
)
81 panfrost_get_device_vendor(struct pipe_screen
*screen
)
87 panfrost_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
89 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
90 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
93 case PIPE_CAP_NPOT_TEXTURES
:
94 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
95 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
96 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
97 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
98 case PIPE_CAP_POINT_SPRITE
:
101 case PIPE_CAP_MAX_RENDER_TARGETS
:
102 return is_deqp
? 4 : 1;
105 case PIPE_CAP_OCCLUSION_QUERY
:
107 case PIPE_CAP_QUERY_TIME_ELAPSED
:
108 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
109 case PIPE_CAP_QUERY_TIMESTAMP
:
110 case PIPE_CAP_QUERY_SO_OVERFLOW
:
113 case PIPE_CAP_TEXTURE_SWIZZLE
:
116 case PIPE_CAP_TGSI_INSTANCEID
:
117 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
118 return is_deqp
? 1 : 0;
120 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
121 return is_deqp
? 4 : 0;
122 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
123 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
124 return is_deqp
? 64 : 0;
125 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
128 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
129 return is_deqp
? 256 : 0; /* for GL3 */
131 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
132 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
133 return is_deqp
? 140 : 120;
134 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
135 return is_deqp
? 300 : 120;
137 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
138 return is_deqp
? 16 : 0;
140 case PIPE_CAP_CUBE_MAP_ARRAY
:
143 /* For faking GLES 3.1 for dEQP-GLES31 */
144 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
145 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
146 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
147 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
150 /* For faking compute shaders */
151 case PIPE_CAP_COMPUTE
:
154 /* TODO: Where does this req come from in practice? */
155 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
158 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
160 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
161 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
164 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
165 case PIPE_CAP_INDEP_BLEND_ENABLE
:
166 case PIPE_CAP_INDEP_BLEND_FUNC
:
169 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
170 /* Hardware is natively upper left */
173 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
174 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
175 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
176 case PIPE_CAP_GENERATE_MIPMAP
:
179 /* We would prefer varyings */
180 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
181 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
184 /* I really don't want to set this CAP but let's not swim against the
186 case PIPE_CAP_TGSI_TEXCOORD
:
189 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
190 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
193 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
196 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
199 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
202 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
205 case PIPE_CAP_ENDIANNESS
:
206 return PIPE_ENDIAN_NATIVE
;
208 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
211 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
214 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
217 case PIPE_CAP_VENDOR_ID
:
218 case PIPE_CAP_DEVICE_ID
:
221 case PIPE_CAP_ACCELERATED
:
223 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
224 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
225 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
226 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
229 case PIPE_CAP_VIDEO_MEMORY
: {
230 uint64_t system_memory
;
232 if (!os_get_total_physical_memory(&system_memory
))
235 return (int)(system_memory
>> 20);
238 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
241 case PIPE_CAP_MAX_VARYINGS
:
245 return u_pipe_screen_get_param_defaults(screen
, param
);
250 panfrost_get_shader_param(struct pipe_screen
*screen
,
251 enum pipe_shader_type shader
,
252 enum pipe_shader_cap param
)
254 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
256 if (shader
!= PIPE_SHADER_VERTEX
&&
257 shader
!= PIPE_SHADER_FRAGMENT
&&
258 !(shader
== PIPE_SHADER_COMPUTE
&& is_deqp
))
261 /* this is probably not totally correct.. but it's a start: */
263 case PIPE_SHADER_CAP_SCALAR_ISA
:
266 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
267 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
268 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
269 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
272 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
275 case PIPE_SHADER_CAP_MAX_INPUTS
:
278 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
279 return shader
== PIPE_SHADER_FRAGMENT
? 4 : 8;
281 case PIPE_SHADER_CAP_MAX_TEMPS
:
282 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
284 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
285 return 16 * 1024 * sizeof(float);
287 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
288 return PAN_MAX_CONST_BUFFERS
;
290 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
293 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
295 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
298 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
301 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
304 case PIPE_SHADER_CAP_SUBROUTINES
:
307 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
310 case PIPE_SHADER_CAP_INTEGERS
:
313 case PIPE_SHADER_CAP_INT64_ATOMICS
:
314 case PIPE_SHADER_CAP_FP16
:
315 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
316 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
317 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
318 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
319 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
322 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
323 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
324 return 16; /* XXX: How many? */
326 case PIPE_SHADER_CAP_PREFERRED_IR
:
327 return PIPE_SHADER_IR_NIR
;
329 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
330 return (1 << PIPE_SHADER_IR_NIR
);
332 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
335 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
336 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
337 return is_deqp
? 4 : 0;
338 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
339 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
342 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
343 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
347 fprintf(stderr
, "unknown shader param %d\n", param
);
355 panfrost_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
358 case PIPE_CAPF_MAX_LINE_WIDTH
:
361 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
362 return 255.0; /* arbitrary */
364 case PIPE_CAPF_MAX_POINT_WIDTH
:
367 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
370 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
373 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
374 return 16.0; /* arbitrary */
376 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
377 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
378 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
382 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
388 * Query format support for creating a texture, drawing surface, etc.
389 * \param format the format to test
390 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
393 panfrost_is_format_supported( struct pipe_screen
*screen
,
394 enum pipe_format format
,
395 enum pipe_texture_target target
,
396 unsigned sample_count
,
397 unsigned storage_sample_count
,
400 const struct util_format_description
*format_desc
;
402 assert(target
== PIPE_BUFFER
||
403 target
== PIPE_TEXTURE_1D
||
404 target
== PIPE_TEXTURE_1D_ARRAY
||
405 target
== PIPE_TEXTURE_2D
||
406 target
== PIPE_TEXTURE_2D_ARRAY
||
407 target
== PIPE_TEXTURE_RECT
||
408 target
== PIPE_TEXTURE_3D
||
409 target
== PIPE_TEXTURE_CUBE
||
410 target
== PIPE_TEXTURE_CUBE_ARRAY
);
412 format_desc
= util_format_description(format
);
417 if (sample_count
> 1)
420 /* Format wishlist */
421 if (format
== PIPE_FORMAT_X8Z24_UNORM
)
424 if (format
== PIPE_FORMAT_A1B5G5R5_UNORM
|| format
== PIPE_FORMAT_X1B5G5R5_UNORM
)
428 if (format
== PIPE_FORMAT_B5G5R5A1_UNORM
)
431 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
432 * more alpha than they ask for */
434 bool scanout
= bind
& (PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
| PIPE_BIND_DISPLAY_TARGET
);
435 bool renderable
= bind
& PIPE_BIND_RENDER_TARGET
;
437 if (scanout
&& renderable
&& !util_format_is_rgba8_variant(format_desc
))
440 if (format_desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
&&
441 format_desc
->layout
!= UTIL_FORMAT_LAYOUT_OTHER
) {
442 /* Compressed formats not yet hooked up. */
446 /* Internally, formats that are depth/stencil renderable are limited.
448 * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
449 * rendering perspective. That is, we render to Z24S8 (which we can
450 * AFBC compress), ignore the different when texturing (who cares?),
451 * and then in the off-chance there's a CPU read we blit back to
454 * ...alternatively, we can make the state tracker deal with that. */
456 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
458 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
459 case PIPE_FORMAT_Z24X8_UNORM
:
460 case PIPE_FORMAT_Z32_UNORM
:
461 case PIPE_FORMAT_Z32_FLOAT
:
462 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
474 panfrost_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
475 enum pipe_compute_cap param
, void *ret
)
477 const char * const ir
= "panfrost";
479 if (!(pan_debug
& PAN_DBG_DEQP
))
482 #define RET(x) do { \
484 memcpy(ret, x, sizeof(x)); \
489 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
490 /* TODO: We'll want 64-bit pointers soon */
491 RET((uint32_t []){ 32 });
493 case PIPE_COMPUTE_CAP_IR_TARGET
:
495 sprintf(ret
, "%s", ir
);
496 return strlen(ir
) * sizeof(char);
498 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
499 RET((uint64_t []) { 3 });
501 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
502 RET(((uint64_t []) { 65535, 65535, 65535 }));
504 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
505 RET(((uint64_t []) { 1024, 1024, 64 }));
507 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
508 RET((uint64_t []) { 1024 });
510 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
511 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
513 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
514 RET((uint64_t []) { 32768 });
516 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
517 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
518 RET((uint64_t []) { 4096 });
520 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
521 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
523 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
524 RET((uint32_t []) { 800 /* MHz -- TODO */ });
526 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
527 RET((uint32_t []) { 9999 }); // TODO
529 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
530 RET((uint32_t []) { 1 }); // TODO
532 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
533 RET((uint32_t []) { 32 }); // TODO
535 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
536 RET((uint64_t []) { 1024 }); // TODO
543 panfrost_destroy_screen(struct pipe_screen
*pscreen
)
545 struct panfrost_screen
*screen
= pan_screen(pscreen
);
546 panfrost_bo_cache_evict_all(screen
);
547 pthread_mutex_destroy(&screen
->bo_cache_lock
);
548 drmFreeVersion(screen
->kernel_version
);
553 panfrost_flush_frontbuffer(struct pipe_screen
*_screen
,
554 struct pipe_resource
*resource
,
555 unsigned level
, unsigned layer
,
556 void *context_private
,
557 struct pipe_box
*sub_box
)
559 /* TODO: Display target integration */
563 panfrost_get_timestamp(struct pipe_screen
*_screen
)
565 return os_time_get_nano();
569 panfrost_fence_reference(struct pipe_screen
*pscreen
,
570 struct pipe_fence_handle
**ptr
,
571 struct pipe_fence_handle
*fence
)
573 struct panfrost_fence
**p
= (struct panfrost_fence
**)ptr
;
574 struct panfrost_fence
*f
= (struct panfrost_fence
*)fence
;
575 struct panfrost_fence
*old
= *p
;
577 if (pipe_reference(&(*p
)->reference
, &f
->reference
)) {
578 util_dynarray_foreach(&old
->syncfds
, int, fd
)
580 util_dynarray_fini(&old
->syncfds
);
587 panfrost_fence_finish(struct pipe_screen
*pscreen
,
588 struct pipe_context
*ctx
,
589 struct pipe_fence_handle
*fence
,
592 struct panfrost_screen
*screen
= pan_screen(pscreen
);
593 struct panfrost_fence
*f
= (struct panfrost_fence
*)fence
;
594 struct util_dynarray syncobjs
;
597 /* All fences were already signaled */
598 if (!util_dynarray_num_elements(&f
->syncfds
, int))
601 util_dynarray_init(&syncobjs
, NULL
);
602 util_dynarray_foreach(&f
->syncfds
, int, fd
) {
605 ret
= drmSyncobjCreate(screen
->fd
, 0, &syncobj
);
608 ret
= drmSyncobjImportSyncFile(screen
->fd
, syncobj
, *fd
);
610 util_dynarray_append(&syncobjs
, uint32_t, syncobj
);
613 uint64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
614 if (abs_timeout
== OS_TIMEOUT_INFINITE
)
615 abs_timeout
= INT64_MAX
;
617 ret
= drmSyncobjWait(screen
->fd
, util_dynarray_begin(&syncobjs
),
618 util_dynarray_num_elements(&syncobjs
, uint32_t),
619 abs_timeout
, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
,
622 util_dynarray_foreach(&syncobjs
, uint32_t, syncobj
)
623 drmSyncobjDestroy(screen
->fd
, *syncobj
);
628 struct panfrost_fence
*
629 panfrost_fence_create(struct panfrost_context
*ctx
,
630 struct util_dynarray
*fences
)
632 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
633 struct panfrost_fence
*f
= calloc(1, sizeof(*f
));
637 util_dynarray_init(&f
->syncfds
, NULL
);
639 /* Export fences from all pending batches. */
640 util_dynarray_foreach(fences
, struct panfrost_batch_fence
*, fence
) {
643 /* The fence is already signaled, no need to export it. */
644 if ((*fence
)->signaled
)
647 drmSyncobjExportSyncFile(screen
->fd
, (*fence
)->syncobj
, &fd
);
649 fprintf(stderr
, "export failed: %m\n");
652 util_dynarray_append(&f
->syncfds
, int, fd
);
655 pipe_reference_init(&f
->reference
, 1);
661 panfrost_screen_get_compiler_options(struct pipe_screen
*pscreen
,
662 enum pipe_shader_ir ir
,
663 enum pipe_shader_type shader
)
665 return &midgard_nir_options
;
669 panfrost_query_gpu_version(struct panfrost_screen
*screen
)
671 struct drm_panfrost_get_param get_param
= {0,};
674 get_param
.param
= DRM_PANFROST_PARAM_GPU_PROD_ID
;
675 ret
= drmIoctl(screen
->fd
, DRM_IOCTL_PANFROST_GET_PARAM
, &get_param
);
678 return get_param
.value
;
682 panfrost_create_screen(int fd
, struct renderonly
*ro
)
684 pan_debug
= debug_get_option_pan_debug();
686 /* Blacklist apps known to be buggy under Panfrost */
687 const char *proc
= util_get_process_name();
688 const char *blacklist
[] = {
693 for (unsigned i
= 0; i
< ARRAY_SIZE(blacklist
); ++i
) {
694 if ((strcmp(blacklist
[i
], proc
) == 0))
698 /* Create the screen */
699 struct panfrost_screen
*screen
= rzalloc(NULL
, struct panfrost_screen
);
705 screen
->ro
= renderonly_dup(ro
);
707 fprintf(stderr
, "Failed to dup renderonly object\n");
715 screen
->gpu_id
= panfrost_query_gpu_version(screen
);
716 screen
->require_sfbd
= screen
->gpu_id
< 0x0750; /* T760 is the first to support MFBD */
717 screen
->kernel_version
= drmGetVersion(fd
);
719 /* Check if we're loading against a supported GPU model. */
721 switch (screen
->gpu_id
) {
722 case 0x750: /* T760 */
723 case 0x820: /* T820 */
724 case 0x860: /* T860 */
727 /* Fail to load against untested models */
728 debug_printf("panfrost: Unsupported model %X",
733 pthread_mutex_init(&screen
->bo_cache_lock
, NULL
);
734 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->bo_cache
); ++i
)
735 list_inithead(&screen
->bo_cache
[i
]);
737 if (pan_debug
& PAN_DBG_TRACE
)
738 pandecode_initialize();
740 screen
->base
.destroy
= panfrost_destroy_screen
;
742 screen
->base
.get_name
= panfrost_get_name
;
743 screen
->base
.get_vendor
= panfrost_get_vendor
;
744 screen
->base
.get_device_vendor
= panfrost_get_device_vendor
;
745 screen
->base
.get_param
= panfrost_get_param
;
746 screen
->base
.get_shader_param
= panfrost_get_shader_param
;
747 screen
->base
.get_compute_param
= panfrost_get_compute_param
;
748 screen
->base
.get_paramf
= panfrost_get_paramf
;
749 screen
->base
.get_timestamp
= panfrost_get_timestamp
;
750 screen
->base
.is_format_supported
= panfrost_is_format_supported
;
751 screen
->base
.context_create
= panfrost_create_context
;
752 screen
->base
.flush_frontbuffer
= panfrost_flush_frontbuffer
;
753 screen
->base
.get_compiler_options
= panfrost_screen_get_compiler_options
;
754 screen
->base
.fence_reference
= panfrost_fence_reference
;
755 screen
->base
.fence_finish
= panfrost_fence_finish
;
756 screen
->base
.set_damage_region
= panfrost_resource_set_damage_region
;
758 panfrost_resource_screen_init(screen
);
760 return &screen
->base
;